Abstract: Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.

Abstract: A method and system whereby an initiator device discovers the user-friendly name of another device in a wireless network of devices, such as a Bluetooth network. Initially, the initiator device broadcasts an inquiry message that is received by the other device (the responding device). The responding device provides its address in response to the inquiry. The initiator device then transmits a page, followed by a name request, to the responding device. The responding device provides its user-friendly name in response to the name request. The initiator device stores (e.g., caches) the address and the associated user-friendly name in a memory cache. When the initiator device subsequently sends an inquiry message that is received by the responding device, the responding device will provide its address to the initiator device. However, instead of sending a name request, the initiator device can retrieve the user-friendly name from the memory cache based on the address.

Abstract: A system, an apparatus, and a method for dividing an address into at least two parts and searching for an address from a table that matches at least a significant portion of one of those parts. Where a table address having an exact match to a part of the address is found, additional parts of the address may be matched to one or more table addresses iteratively.

Abstract: An address translation apparatus and method that can convert a limited-range memory address from a peripheral device to an expanded-range memory address on the fly. The invention can expand the limited address capability of a peripheral bus, such as a PCI bus with a 4 GB address range, to a much larger address capability, such as a 64 GB address range. This conversion can be performed on the fly by hardware, so that no appreciable delay in transfer time is created. The conversion can be performed by adding features to a conventional graphics controller interface, thus minimizing the impact on circuit complexity and system cost.

Abstract: Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address comprised of a base address and an offset, obtains a base value for the base address, sums the base value with the offset, and provides an absolute address corresponding to the relative address. The storage unit receives the base address and provides the base value to the address generator. The storage unit also receives the absolute address and provides data at this address. The address generator may derive the absolute address in a first clock cycle of a memory access. The storage unit may provide the data in a second clock cycle of the memory access. The storage unit may have multiple (e.g., two) read ports to support concurrent address generation and data retrieval.

Abstract: A method is provided for processing a virtual address for a program requesting a DMA transfer. The program is designed to be run in user mode on a system on a chip that includes a central processing unit, a memory management unit, and a DMA controller. The virtual address is a source virtual address or a destination virtual address and has a size of N bits. According to the method, the virtual address is divided into at least two fields of bits. For each of the fields, there is created an N-bit address word comprising a prefix having a given value associated with the field and having more than 1 bit, and the field. The DMA controller is programmed using multiple store instructions that include one store instruction relating to each of the address words created.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

Abstract: Apparatus and methods for an improved priority encoder using only static circuit components. Features and aspects hereof rely exclusively on static logic circuits exclusive ROM and other memory structures as relied on in prior structures. The exemplary static circuit structures relied upon in accordance with features and aspects hereof are less susceptible to leakage current and other issues common in high density integrated circuit applications. Thus, features and aspects hereof avoid use of ROM and other similar memory devices in favor of digital encoders comprised of static logic circuits cascaded through multiplexers to provide priority encoding in digital circuit applications coupling multiple devices to a shared, common bus structure.

Abstract: Embodiments of the invention provide a method, devices, and system for issuing commands from a first device to a second device. In one embodiment, the method includes receiving, by the first device, a first command which writes a second command to a memory location within the first device. The second command includes a command code, a first value identifying an operand offset for operands of the second command, and a second value identifying a number of the operands of the second command. The method also includes providing the second command to the second device. In one embodiment, the second device loads the operands of the second command using the offset and the number provided by the second command.

Abstract: A method for managing an external memory of a microprocessor so that the external memory only contains one copy of a common area. By providing an address translator, mapping the page and the address of the common area of the page pointed by a microprocessor to the physical address of the common area of the external memory, using the address translator to translate a page and an address pointed by a microprocessor to a physical address of the external memory, and using the microprocessor to access data stored at the physical address of the external memory; the memory can be more efficiently used.

Abstract: A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.

Abstract: An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits a data cache into multiple regions and each region is selected according to a thread ID indicator in an instruction register. The data cache is split when the apparatus is in the multi-threading execution mode indicated by an enable cache split bit.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

Abstract: Various embodiments of a method, apparatus and article of manufacture to manage an index are provided. A circular index, having an index size, is provided. The circular index stores information to reference data in a sequential list. Accesses to the index and the list are monitored to provide at least one performance indicator. The performance indicator represents an effect of the index on accessing items in the list. The index size is changed based on the at least one performance indicator. The monitoring of the accesses and the changing of the index size are repeated.

Abstract: According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of the at least one memory device, determining a second memory location based on the first value and loading a second value from the second memory location of the at least one memory device, wherein the step of loading a first value is performed by a first processing unit and wherein the steps of determining a second memory location and loading a second value are performed by at least one other processing unit.

Abstract: To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.

Abstract: A memory controller which can perform a series of data write operation to a flash memory device fast is disclosed. The memory controller according to an embodiment of the present invention is the memory controller for accessing a memory having a plurality of physical blocks based on a host address provided from a host computer. The memory controller has means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to different groups, the virtual blocks can be divided into at least a first class and a second class, and means for assigning adjacent host addresses into different physical blocks belonging to the same virtual block of the first class and assigning adjacent host addresses into the same physical blocks belonging to the same virtual block of the second class.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.

Abstract: Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.

Abstract: A computer has access to a system-formatted data storage unit (DSU) containing a file system and to a raw DSU. A file within the file system constitutes a raw DSU mapping that facilitates access to the raw DSU. The raw DSU mapping appears to be an ordinary file to a storage user, but with the size of the raw DSU. An attempted access to the raw DSU mapping is translated into a corresponding access to the raw DSU. Access to the raw DSU by the storage user may be restricted to a specified region of the raw DSU, by defining an extent within the raw DSU mapping. The raw DSU mapping provides access to the raw DSU with many of the advantages of using a file system, including name persistency, permissions, persistent attributes, locking information for a distributed file system and other extended metadata.

Abstract: Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using separate addresses, in one mode of operation, and accessed using a common single address in another mode of operation.

Abstract: A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address. The current address corresponds to a current location in the memory. In addition, the method includes performing a data swap on data stored at the current location with data stored at the new location.

Abstract: The Internet data defining destinations accessible by a router are partitioned into a portion containing the address search information and a portion containing forwarding option data. The address search information is stored in fast memory in a tree search format and the set of possible next destinations are stored as forwarding option data in slower memory at addresses derived algorithmically from the tree search address information. Internet data packets are received and data therein is compared to determine the best match address in the fast memory to the set of possible best next destinations. The multiple accesses necessary to determine the best match address are confined to high speed memory. An algorithm receives option data from an Internet packet and option threshold data from the best match address of the high speed memory and determines which address of the slower memory has the desired forwarding data using one access.

Abstract: When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus controller BSC makes address translation according to information on the relation between addresses of both memory spaces. The invention assures wider latitude in CPU type selection and makes it easy to reuse an existing program or develop a new program.

Abstract: A method and apparatus to route information in a network is described. A technique is described to search for routine information that uses a first technique on at least a portion of a first value of a network address and a second technique on at least a portion of a second section of an address. In particular, the first value is associated with an aggregation identifier, and compared to a unique prefix. In this way, address identifiers may be generated, and this identifier is used to search for routing information.

Abstract: This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base address. A fractional shifter is also included and is configured to shift the index value up to three bit places, and output a byte offset. An adder is configured to add the byte offset with the base address and output a final address. Further included is a general purpose shifter that is configured to rotate left and right, and shift left and right. A selector is configured to select either the final address or an output signal from the general purpose shifter.

Abstract: A semiconductor system according to an embodiment of the present invention comprises a shared memory; a plurality of processing units each of which designates a memory size and a memory address, and which uses the shared memory; an address allocation unit which allocates memory addresses having the memory size designated by the each processing unit to the processing unit; and an address conversion unit which converts the memory address designated by the each processing unit into one of the memory addresses allocated to the processing unit, the converted memory address being including in the shared memory and being accessed by the processing unit.

Abstract: A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.

Abstract: A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.

Abstract: Methods and systems are provided for determining the physical address of an allocated and locked memory buffer. An application program may request the allocation of a memory buffer. A virtual memory address for the memory buffer is then returned. The virtual memory address is adjusted to correspond to a page boundary within a physical memory address space. The memory buffer is then locked to the physical memory. A predetermined bit pattern is then written to the memory buffer. A search may then be made of the physical memory for the bit pattern to determine the location within the physical memory address space of the allocated memory buffer. Once the physical address of the memory buffer has been determined, it may be utilized to reference the memory buffer by a program that would not otherwise have access to the virtual address space.

Abstract: A scheduler for a set of data packet storage devices (e.g., FIFOs) implements a scheduling algorithm embodied in a look-up table (LUT) that identifies the next FIFO to select for service based on the current status of the FIFOs. In one embodiment, in addition to a memory device used to store the LUT, the scheduler has (1) a latch adapted to store and forward the LUT output and (2) an extractor that implements a finite state machine that determines (1) when to enable the latch and (2) when to forward the identification of the next FIFO to select for service to the set of FIFOs. Using a LUT enables relatively complicated scheduling algorithms to be implemented for relatively large numbers of FIFOs without significantly increasing the execution time of the scheduler.

Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilising a 12-bit offset field but with a fixed addressing mode and a second form utilising a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.

Abstract: Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.

Abstract: The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.

Abstract: A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

Abstract: A cache control program that reduces cache control load. The cache control programs functions as a multi-bind cache (MBC) manager of a file server. The MBC manager manages a cache memory as a plurality of extents. The MBC manager generates cache IDs including object identifications for identifying the objects of each hierarchical level. Further, the MBC manager generates a cache header table indicating the relation of the cache IDs and the cache extents for each hierarchical level.

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit defines partial configuration requirements, and contains at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. The configuration loading unit provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements without providing commands corresponding to any addresses outside of said configuration requirements.

Abstract: Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.

Abstract: A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.

Abstract: A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.

Abstract: A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.

Abstract: A method for detecting an invalid pointer including a source component and a target component, involving selecting a virtual source memory address for the source component wherein the virtual source memory address is within a first valid virtual address range, selecting a virtual target memory address for the target component wherein the virtual target memory address is within a second valid virtual address range, numerically combining the virtual source memory address and the virtual target memory address to obtain a new virtual source memory address, and writing the virtual target memory address into a memory location referenced by the new virtual source memory address, wherein writing the virtual target memory address triggers an action by a memory management unit (MMU) if the new virtual source memory address is an invalid memory location.

Abstract: Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with a predefined modes of indexing. The counters support slipping when counting to support convolutional filters in one-dimension (1D) and two-dimension (2D). For 2D indexing, a first counter indexes in the X direction and a second counter indexes in the Y direction in memory. The values from the first and second counter are combined with an offset value to form an address directly to memory.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.

Abstract: An address decoding method and related apparatus for deciding which section of a memory device a given address belongs. The memory device has a plurality of sections, each section has a plurality of memory units, and each memory unit has a unique address. The method includes: comparing some specific bits of the given address with predetermined values for deciding which section the given address belongs.

Abstract: An address converter has a base address register and address mask register for setting the start address and range, respectively, of a transparent mode access permitted area. By using the values of these base address register and address mask register, the address converter converts an address signal (address value) supplied from an external bus master into an address signal within a predetermined range from the start position of the transparent mode access permitted area. A transparency controller executes transparent mode access by using the converted address signal. This makes it possible to connect devices having different address bus widths to an external bus without forming any new external circuit, and to set an arbitrary transparent mode access permitted area.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status vector, and generates a match vector as a function of the status vector and a set of stored compare vectors. In response, the OA selects for output one of a set of a control vector as a function of the match vector. A state vector portion of the selected control vector is forwarded to the CAM as a portion of the status vector. An output vector portion of the selected control vector controls the operation of external components. Both the set of stored compare vectors and the set of control vectors are fully re-programmable.