Abstract: The presented systems enable efficient and effective network communications. The presented systems enable efficient and effective network communications. In one embodiment a memory device includes a memory module, including a plurality of memory chips configured to store information; and an inter-chip network (ICN)/shared smart memory extension (SMX) memory interface controller (ICN/SMX memory interface controller) configured to interface between the memory module and an inter-chip network (ICN), wherein the ICN is configured to communicatively couple the memory device to a parallel processing unit (PPU). In one exemplary implementation, the ICN/SMX memory controller includes a plurality of package buffers, an ICN physical layer interface, a PRC/MAC interface, and a switch. The memory device and be a memory card including memory module (e.g., DDR DIMM, etc.).

Abstract: This application describes systems and methods for facilitating memory access in flash drives. An example method performed by a memory controller may include receiving, from a host, a write command comprising data to be written into a flash memory; splitting the data into a first portion and a second portion; storing the first portion into a static random-access memory (SRAM) in the memory controller; storing the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller; initiating a configuration operation corresponding to the write command; fetching the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory; combining the fetched first portion and the fetched second portion; and storing the combined first portion and the second portion into the flash memory.

Abstract: A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

Abstract: An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Abstract: Switches and methods for utilizing the switches are described. The switch has ports, a memory and a scheduler. Packets ingress and egress the switch through the ports. Each packet is divisible into packet segments. The memory includes banks. The scheduler is coupled with the ports and the memory. The scheduler is configured to allocate memory to store the packet segments in the banks such that a beginning packet segment of a packet is stored in a selected bank and each subsequent packet segment in the packet is stored in order in a next adjacent bank.

Abstract: Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

Abstract: In a memory sub-system, data can be received to be stored at a 3-dimensional (3D) memory component in response to a write operation. A first location of a first layer of the 3D memory component is determined at which to store a first portion of the data, where the first layer is within a first logical unit. A second location of a second layer of the 3D memory component is determined at which to store a second portion of the data, where the second layer is within a second logical unit that is different than the first logical unit. The first portion of the data is caused to be stored in first memory cells at the first location within the first layer. The second portion of the data is caused to be stored in second memory cells at the second location within the second layer.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor. The storage product can receive via the network interface first messages and second messages for network storage services. The bus switch is operable to provide a first bus between the processing device and the random-access memory to buffer the first messages into the random-access memory, a second bus between the processing device and the storage device to buffer the second messages into a local memory of the storage device, and a third bus between the processor and the random-access memory to retrieve the first messages from the random-access memory and generate third messages. The storage device is configured to process the second and third messages to provide network storage services.

Abstract: A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

Abstract: A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

Abstract: A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Abstract: Data recovery in a virtual storage system, including: detecting, within storage provided by a first tier of storage of the virtual storage system, data loss within a dataset, wherein recovery data for the dataset is stored in a second tier of storage; determining a recovery point for the dataset up to which a consistent version of the dataset is recoverable from the recovery data stored in the second tier of storage; and restoring, within the storage provided by the first tier of storage of the virtual storage system, the consistent version of the dataset.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.

Abstract: A method to transfer an artificial intelligence (AI) model includes identifying a plurality of layers of an AI model, wherein each layer of the plurality of layers is associated with a memory address. The method further includes randomizing the memory address associated with each layer of the plurality of layers, and transferring the plurality of layers with the randomized memory addresses to a data processing accelerator to execute the AI model.

Abstract: To enable efficient uplink transmission. A terminal apparatus includes: a coder configured to code a UCI payload and perform rate matching of coded bits of the UCI payload; and a transmitter configured to transmit the UCI payload by using a PUSCH, the UCI payload includes at least HARQ-ACK information and/or CSI, a length of an output sequence EUCI of the rate matching is provided based on a first number of CRC bits LUCI, the first number of CRC bits LUCI is provided based on a size of the payload, and a size of second CRC bits added to the payload is provided based on the size of the payload and the length of the output sequence EUCI of the rate matching.

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Abstract: A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The memory device includes a memory block having a plurality of banks, wherein each of the banks has a plurality of memory cells, and wherein the memory block has multiple ports. An output interface provides data on a second plurality of serial links. A cache coupled to the IO interface and to the plurality of banks, stores write data designated for a given memory cell location when the given memory cell location is currently being accessed, thereby avoiding a collision. Memory device includes one or more memory access controllers (MACs) coupled to the memory block and one or more arithmetic logic units (ALUs) coupled to the MACs.

Abstract: A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency.

Abstract: Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described herein includes a system for integrated sub-block interleaving and rate matching, which includes a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm and a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm, such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm or in the order that the data would be produced by the interleaving algorithm as modified by a rate matching algorithm.

Abstract: Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log2(Y)) and C=ceiling(log2(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S<Y, the system sets E=S. Otherwise, if S?Y, the system sets E=S?Y.

Abstract: The present patent application discloses a method and apparatus for using external and internal memory for cancelling traffic interference comprising storing data in an external memory; and processing the data samples on an internal memory, wherein the external memory is low bandwidth memory; and the internal memory is high bandwidth on board cache. The present method and apparatus also comprises caching portions of the data on the internal memory, filling the internal memory by reading the newest data from the external memory and updating the internal memory; and writing the older data back to the external memory from the internal memory, wherein the data is incoming data samples.

Abstract: An interleaving method includes: generating multiple read-addresses for respective bits of multiple write-words; queuing the read-addresses in parallel in multiple address queues; selecting an address queue among the address queues that is not empty based on status of each address queue; decoding the address from the selected address queue to a read-address and a bit-address; extracting a read-word from data to be interleaved based on the read-address; selecting a write-bit from the read-word based on the bit-address; arbitrating an individual write-bit to one of the write-words based on an address queue ID of the selected address queue; and generating write-addresses for respective write-words.

Abstract: A storage controller including a processor and a memory controller. The processor is configured to generate a command corresponding to a first write operation and a second write operation, in which the first write operation is contiguous to the second write operation, and the first write operation is received prior to the second write operation. The command arranges the second write operation prior to the first write operation. The memory controller is configured to, in response to the command, execute each of the first write operation and the second write operation. The second write operation is executed by the memory controller prior to the first write operation.

Abstract: A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory.

Abstract: A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract: A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

Abstract: A flash memory control circuit including a microprocessor unit, a first interface unit, a second interface unit, a buffer memory, a memory management unit, and a data read/write unit is provided. The memory management unit manages a plurality of flash memory units, wherein each of the flash memory units has a plurality of flash memories, each of the flash memories has a plurality of memory cell arrays, and each of the memory cell arrays at least has an upper page and a lower page. The memory management unit groups the memory cell arrays of the corresponding flash memories into a plurality of data transfer unit sets (DTUSs). The data read/write unit interleavingly transfers data to the flash memory units in units of the DTUSs. Thereby, the flash memory control circuit can transfer the data stably and the usage of the buffer memory can be reduced.

Abstract: An apparatus and associated methodology for a data storage system having a data storage space operably transferring user data via input/output (I/O) commands between the data storage system and another device. The data storage space includes a first memory device operably storing location information for a selected user data set corresponding to one of the I/O commands. The first memory also operably stores a first amount of the selected user data set. The data storage space also includes a second memory device different than the first memory device and operably storing a different second amount of the selected user data set. The data storage system has a controller that interleaves an entirety of the selected user data set from the first and second memory devices during execution of another of the I/O commands.

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract: A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time.

Abstract: A method, system, and computer usable program product for managing thermal condition of a memory are provided in the illustrative embodiments. A condition that a threshold value of a thermal condition of the memory has been exceeded or is likely to be exceeded is identified. A portion of a first workload is identified as being a cause of exceeding the threshold. A second portion of a second workload is identified, the second portion not causing the threshold to be exceeded when executed. A set of operations corresponding to the first portion is interleaved with a second set of operations corresponding to the second portion. The interleaved first and second portions of the first and second workloads are executed, causing the thermal condition of the memory to remain below the threshold. The second portion may use a second memory, a second area of the memory, or a combination thereof when executing.

Abstract: Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described herein includes a system for integrated sub-block interleaving and rate matching, which includes a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm and a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm, such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm or in the order that the data would be produced by the interleaving algorithm as modified by a rate matching algorithm.

Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating transferring of fixed size portions of the file data to a first buffer and a second buffer, alternating processing of data blocks of the fixed sized portions in parallel from the first and second buffers by a plurality of processing threads, and outputting the processed data blocks.

Abstract: A method for data storage includes receiving a plurality of data items for storage in a memory, including at least first data items that are associated with a first data source and second data items that are associated with a second data source, such that the first and second data items are interleaved with one another over time. The first data items are de-interleaved from the second data items, by identifying a respective data source with which each received data item is associated. The de-interleaved first data items and the de-interleaved second data items are stored in the memory.

Abstract: A distributed shared memory multiprocessor system that supports both fine- and coarse- grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain interleaved and coarse-grain interleaved memory regions of the distributed shared memory. A method for satisfying a memory access request in a distributed shared memory subsystem of a multiprocessor system having both fine- and coarse-grain interleaved memory segments. Certain low or high order address bits, depending on whether the memory segment is fine- or coarse-grain interleaved, respectively, are used to determine if the memory address is local to a processor node. A method for setting the ceiling mask of a distributed shared memory multiprocessor system to optimize performance of a first application run on a single node and performance of a second application run on a plurality of nodes.

Abstract: Various embodiments of the present invention are related to methods and apparatuses for interleaving data, and more particularly to methods and apparatuses for interleaving variably sized blocks of data. For example, in one embodiment an apparatus includes a data partitioner operable to partition the block of data into a real data portion and a missing bits portion. The real data portion is adapted to contain data bits from the variably sized block of data and the missing bits portion is adapted to be filled with a variable number of the data bits. The apparatus also includes at least one local interleaver operable to apply a permutation across each of a plurality of sub-portions of the real data portion and the missing bits portion, and a global interleaver operable to apply a global permutation across the real data portion.

Abstract: An apparatus comprising a plurality of memory components each comprising a plurality of memory banks, a memory controller coupled to the memory components and configured to control and select a one of the plurality of memory components for a memory operation, a plurality of address/command buses coupled to the plurality of memory components and the memory controller comprising at least one shared address/command bus between at least some of the plurality of memory components, and a plurality of data buses coupled to the memory components and the memory controller comprising at least one data bus between at least some of the memory components, wherein the memory controller uses a memory interleaving and bank arbitration scheme in a time-division multiplexing (TDM) fashion to access the plurality of memory components and the memory banks.

Abstract: A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract: Bus transactions in a computer network are improved by utilizing a multicast transaction from a single initiator to multiple targets. The multiple targets simultaneously execute the transaction and provide a return transaction to the initiator. The transaction cycle time is reduced as individual request to each target is replace with a single request to a collective target group, addressable by a single base memory address. Interleaved read or write operation is provided to allow the multiple targets of a particular target group to independently execute a portion of the transaction request. Improved bus performance is achieve by utilizing the higher throughput capacity of the system bus providing a higher number of shorter data segments from each target executing its portion of the larger transaction.

Abstract: An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.

Abstract: Computers and other computing machines and information appliances having a modified computer architecture and program structure which enables the operation of an application program concurrently or simultaneously on a plurality of computers interconnected via a communications link or network using a special distributed runtime (DRT), and that provides for a redundant array of independent computing systems that include computer code distribution using code-striping onto the plurality of the computers or computing machines. A redundant array of independent computing systems operating in concert and code-striping features.

Abstract: An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device.

Abstract: Among others, techniques and apparatus are described for de-interleaving. A data processing apparatus includes a buffer to store interleaved data; an interleaving index producing unit to produce an interleaving index of the interleaved data; and an output control unit to output the data stored in the buffer using the interleaving index.

Abstract: A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor.