Addressing Physical Block Of Locations, E.g., Base Addressing, Module Addressing, Memory Dedication, Etc. (epo) Patents (Class 711/E12.078)
  • Patent number: 9032150
    Abstract: Storage drives of a plurality of types are mounted on a storage device together. A storage apparatus includes: an I/O controller that receives an access request sent from an information apparatus and writes data to or reads data from a storage drive; a storage drive mounting unit in which the storage drive is detachably mounted; a drive power supplying unit that supplies drive power to the storage drive mounted in the storage drive mounting unit; and a drive voltage identifying unit that identifies a voltage allowing data write to or data read from the storage drive mounted in the storage drive mounting unit, by raising a drive voltage applied to the storage drive from a voltage below a rated drive voltage of the storage drive. When the I/O controller writes data to or reads data from the storage drive, the drive power supplying unit applies the identified voltage to the storage drive to drive the storage drive.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: May 12, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Homare Okamoto, Mitsuhide Sato
  • Patent number: 9003153
    Abstract: A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 7, 2015
    Assignee: Greenliant LLC
    Inventor: Siamak Arya
  • Patent number: 8984246
    Abstract: In response to a query of a decision tree, a first packed node of the decision tree is copied from a system memory into a direct memory access (“DMA”) memory. In response to copying the first packed node from the system memory into the DMA memory, copying is initiated of a second packed node of the decision tree from the system memory into the DMA memory, up to a limit of then-currently available space within the DMA memory. Concurrently with copying the second packed node from the system memory into the DMA memory, the first packed node is evaluated in the DMA memory. In response to evaluating the first packed node, the second packed node is evaluated in the DMA memory without waiting for additional copying of the second packed node from the system memory into the DMA memory.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Goksel Dedeoglu
  • Patent number: 8984032
    Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 17, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Joseph Edward Halpern, III, Henry Hutton, Judah Gamliel Hahn, Moshe Raz, In-Soo Yoon
  • Patent number: 8972620
    Abstract: Systems and methods to simplify population of modular components in an information handling system are disclosed. A method of populating modular components in an information handling system comprises a first step of initializing a populating sequence. A first socket corresponding to a first modular component is then identified. The first socket is flagged if it does not contain the first modular component. The first modular component is then installed in the first socket which is flagged.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: March 3, 2015
    Assignee: Dell Products L.P.
    Inventors: Stephen Billick, Robert Bassman
  • Patent number: 8949522
    Abstract: Systems, apparatusses, and methods are disclosed for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU). The present disclosure teaches a processor system that employs out-of-order stride prefetch units. The out-of-order stride prefetch units are utilized for issuing prefetches for out-of-order stride access patterns. In one or more embodiments, the out-of-order stride prefetch units examine the offsets between past virtual address (VA) accesses and the directions of the past VA accesses in order to generate an estimate of the underlying VA access stride of the executed program code (PC). In at least one embodiment, the out-of-order stride prefetch units use the estimate of the VA access stride in order to generate a prediction of future VA accesses. In some embodiments, after the out-of-order stride prefetch units have generated the prediction of future VA accesses, the out-of-order stride prefetch units prefetch the predicted future VA accesses.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: February 3, 2015
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Gaurav Garg, David T. Hass
  • Patent number: 8918585
    Abstract: A storage apparatus coupled to a host device comprises a virtual volume which is a virtual logical volume configured of multiple virtual areas and a pool configured of multiple actual area groups of different performances. A controller manages pool status information which is the information showing which actual area is allocated to which virtual area and access load related to the virtual areas. A management system of the storage apparatus, with reference to the pool status information at multiple points of time from past to present and an access load threshold which is equal to or larger than 1, estimates the used capacity of each actual area group at points of time in the future, calculates the installed/removed amount of each actual area group which is the difference between the estimated used capacity and the current storage capacity, and performs the processing based on the calculated result.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: December 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Naganuma, Hirokazu Ikeda, Hironori Emaru, Koichi Murayama, Shinichiro Kanno
  • Patent number: 8918621
    Abstract: The performance and efficiency of file systems for data allocation access in random-access storage media is enhanced by isolating block addresses from other metadata and the actual data itself in a separate address space. Block addresses are stored in memory and file system structures that are separate from those structures that store other metadata and the actual data. This affords faster address lookup and access to data storage locations, and more efficient storage allocation and accessing algorithms. The block address isolation may be implemented in separate logic, in a hardware controller for a storage drive, or in software in a storage hierarchy.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: December 23, 2014
    Assignee: EMC Corporation
    Inventor: Cimarron D. Taylor
  • Patent number: 8914606
    Abstract: According to at least one embodiment, a method comprises partitioning a computer system into a plurality of soft partitions that each run an operating system. The method further comprises instantiating a separate firmware instance for each of the plurality of soft partitions, wherein each of the firmware instances provides a pre-defined firmware interface for the operating system of its respective soft partition.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: December 16, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Bradley G. Culter
  • Patent number: 8909900
    Abstract: A storage device and method for updating data stored in a partition of the storage device are provided. In one embodiment, a storage device is provided that contains a logical-to-physical address map and a memory with a first partition storing original data and a second partition. The storage device receives from a host device (i) a command to write updated data to a first logical address and (ii) a signature for verifying integrity of the updated data, wherein the first logical address is mapped to a physical address of the first partition. The storage device then stores the updated data in the second partition instead of the first partition and attempts to verify the signature of the updated data. If the attempt to verify the signature is successful, the storage device updates the logical-to-physical address map to map the first logical address to a physical address of the second partition.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: December 9, 2014
    Assignee: SanDisk IL Ltd.
    Inventors: Boris Dolgunov, Nir Ekhauz, Nir Paz
  • Patent number: 8862813
    Abstract: Responding to IO requests made by an application to an operating system within a computing device implements IO performance acceleration that interfaces with the logical and physical disk management components of the operating system and within that pathway provides a system memory based disk block cache. The logical disk management component of the operating system identifies logical disk addresses for IO requests sent from the application to the operating system. These addresses are translated to physical disk addresses that correspond to disk blocks available on a physical storage resource. The disk block cache stores cached disk blocks that correspond to the disk blocks available on the physical storage resource, such that IO requests may be fulfilled from the disk block cache.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: October 14, 2014
    Assignee: DataCore Software Corporation
    Inventors: Ziya Aral, Roni Putra
  • Patent number: 8856458
    Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: October 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Patent number: 8843702
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Jlm Kardach, Nikos Kaburlasos
  • Patent number: 8825945
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Shashi Kiran Chilappagari, Xueshi Yang, Gregory Burd
  • Patent number: 8819387
    Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 26, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Wei-Chen Teo
  • Patent number: 8806116
    Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: August 12, 2014
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy
  • Patent number: 8799617
    Abstract: A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: August 5, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephen Pickering, Edward J. Hathaway, Christian Vetterli, Michael C. Wood
  • Patent number: 8787101
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Patent number: 8782332
    Abstract: A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: July 15, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chung-Ching Chen, Hsian-Feng Liu, Yu-Lin Chen
  • Patent number: 8775745
    Abstract: A process variation tolerant collision detection apparatus for use in detecting collisions in a multibank memory. The apparatus may receive a plurality of memory commands for execution at the multibank memory. The plurality of memory commands may be compared by an index address comparator and a bank address comparator to generate an index match signal and a bank match signal. The index match signal and the bank match signal may be analyzed by a timing correction module such that errors associated with process variation of the signals used in the system may be eliminated. Accordingly, a corrected index match signal and a corrected bank match signal may be provided to a collision detection circuit to determine whether a collision exits.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 8, 2014
    Assignee: Oracle International Corporation
    Inventors: Jungyong Lee, Singrong Li, Heechoul Park
  • Patent number: 8762685
    Abstract: A data writing method for writing updated data from a host into a memory module is provided. Herein, some physical units of the memory module are gotten to be global random physical units for storing data from the host. The method includes determining whether the updated data is sequential data and determining whether a logical page corresponding to the updated data is a start logical page. The method further includes getting a blank physical unit from the physical units as a new global random physical unit and writing the updated data into the new global random physical unit when the updated data is the sequential data and the logical page corresponding to the updated data is the start logical page. Accordingly, the method can write updated data belonging to the same logical unit into the same physical unit, thereby shortening the time for executing write commands.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: June 24, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8738885
    Abstract: The invention relates to a method for selecting an available memory size of a circuit including at least a CPU and a total memory, the method includes a stage for the selection of an available memory size that is smaller than or equal to that of the total memory. The selection stage is implemented by the manufacturer of the product incorporating the said circuit, different from the circuit manufacturer, and includes a stage for the generation of a configuration signature intended for the circuit manufacturer, which information is representative of the size of available memory size selected in this way by the product manufacturer.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: May 27, 2014
    Assignee: Gemalto SA
    Inventor: Benoit Arnal
  • Patent number: 8732395
    Abstract: In an information recording medium in which storage capacity per recording layer has increased so much that the size of an SBM varies with those of spare areas, there is mutual dependence between a DDS and an SBM and it is difficult to retrieve disc management information as intended. In an information recording medium according to the present invention, if the largest space is allocated to an user data area, the number of blocks to store a space bitmap is Ni (where Ni?2). But if the smallest space is allocated to the user data area, the number of blocks to use is smaller than Ni.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 20, 2014
    Assignee: Panasonic Corporation
    Inventors: Hisae Kato, Yoshihisa Takahashi, Motoshi Ito
  • Patent number: 8700839
    Abstract: A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 15, 2014
    Assignee: Genesys Logic, Inc.
    Inventors: Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo, Cheng-Chih Yang
  • Patent number: 8700844
    Abstract: A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: April 15, 2014
    Assignee: Via Technologies, Inc.
    Inventor: Ming-Xing Gao
  • Publication number: 20140101409
    Abstract: Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: ALTERA CORPORATION
    Inventor: ALTERA CORPORATION
  • Patent number: 8688890
    Abstract: A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: April 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Blaine D. Gaither, Verna Knapp
  • Patent number: 8671265
    Abstract: An access request including a client address for data is received. A metadata server determines a mapping between the client address and storage unit identifiers for the data. Each of the one or more storage unit identifiers uniquely identifies content of a storage unit and the metadata server stores mappings on storage unit identifiers that are referenced by client addresses. The one or more storage unit identifiers are sent to one or more block servers. The one or more block servers service the request using the one or more storage unit identifiers where the one or more block servers store information on where a storage unit is stored on a block server for a storage unit identifier. Also, multiple client addresses associated with a storage unit with a same storage unit identifier are mapped to a single storage unit stored in a storage medium for a block server.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 11, 2014
    Assignee: SolidFire, Inc.
    Inventor: David D. Wright
  • Patent number: 8671254
    Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: March 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • Publication number: 20140047214
    Abstract: An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair
  • Publication number: 20140047208
    Abstract: A method of controlling the capacity of a virtual storage system provided on a physical storage system, the method including: providing a control program on the physical storage system; coupling additional virtual storage to the virtual storage system on the physical storage system; providing control data on the additional virtual storage; with the control program, reading the control data and configuring the virtual storage system accordingly. A corresponding virtual storage system is also provided.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: XYRATEX TECHNOLOGY LIMITED
    Inventor: James S.M. Morse
  • Patent number: 8645620
    Abstract: An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peter Buchmann, Martin Leo Schmatz, Jan Van Lunteren
  • Publication number: 20140032872
    Abstract: Systems, computer readable media, and methods are provided. An example method can include classifying a plurality of storage mapping systems as a plurality of storage tiers in a datacenter, assigning a chargeback level to each of the plurality of storage tiers, analyzing a plurality of storage volumes of a plurality of servers in the datacenter to obtain characteristics of each of the plurality of storage volumes where the characteristics include one of the plurality of storage mapping systems, assigning the chargeback level to each of the plurality of storage volumes based on the storage mapping system for each of the plurality of storage volumes, and determining a storage recommendation for a number of configuration item (CIs) based on a criticality of the number of CIs where the criticality corresponds to at least one of the chargeback levels assigned to each of the plurality of storage tiers.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Inventors: Sagi Vasavi, Rajashekar Dasari
  • Publication number: 20130332694
    Abstract: Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: NetApp, Inc.
    Inventor: Michael Reissner
  • Patent number: 8606991
    Abstract: A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal to 1. A threshold of available retention time for each group of banks is determined. Each row of banks in each group of banks is refreshed. Refreshing one row of a bank in one group of banks includes determining whether a refresh operation for the row of the bank conflicts with an access operation for the bank where the row of the bank is located. If there is a conflict, then it is determined whether to perform the refresh operation or the access operation for the current row of the bank. If it is determined to perform the access operation, the access operation is continued. If it is determined to perform the recess operation, the current row of the bank is refreshed. DRAM access performance is improved.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Xu Guang Sun, Hong Wei Wang, Hou Gang Li, Kai Zhang
  • Publication number: 20130318322
    Abstract: A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.
    Type: Application
    Filed: May 28, 2012
    Publication date: November 28, 2013
    Applicant: LSI CORPORATION
    Inventors: Varun Shetty, Dipankar Das, Debjit Roy Choudhury, Ashank Reddy
  • Patent number: 8595414
    Abstract: Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 26, 2013
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Nir J. Wakrat, Vadim Khmelnitsky
  • Publication number: 20130282969
    Abstract: A method and controller for implementing storage adapter performance optimization with chained hardware operations completion coalescence, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines, and a processor. A plurality of the command blocks are selectively arranged by firmware in a predefined chain including a plurality of simultaneous command blocks. All of the simultaneous command blocks are completed in any order by respective hardware engines, then the next command block in the predefined chain is started under hardware control without any hardware-firmware (HW-FW) interlocking with the simultaneous command block completion coalescence.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adrian C. Gerhard, Lyle E. Grosbach, Daniel F. Moertl
  • Publication number: 20130282974
    Abstract: A shiftable memory that supports array merging employs built-in shifting capability to produce a merged array from a first array of data and a second array of data. The shiftable memory includes a memory to store data. The memory provides the built-in shifting capability to shift a contiguous subset of the data from a first location to a second location within the memory. The shiftable memory further includes an array-merging operator to produce the merged array using the built-in shifting capability. The contiguous subset of the data includes the first array.
    Type: Application
    Filed: April 23, 2012
    Publication date: October 24, 2013
    Inventor: Pramod G. Joisha
  • Patent number: 8566562
    Abstract: An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: October 22, 2013
    Assignee: Skymedi Corporation
    Inventors: Yu Mao Kao, Yung Li Ji, Chih Nan Yen, Fuja Shone
  • Publication number: 20130268715
    Abstract: One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.
    Type: Application
    Filed: April 5, 2012
    Publication date: October 10, 2013
    Inventors: Michael FETTERMAN, Stewart Glenn Carlton, Douglas J. Hahn, Rajeshwaran Selvanesan, Shirish Gadre, Steven James Heinrich
  • Patent number: 8554986
    Abstract: Disclosed is a flash memory controlling method and controlling device. The flash memory controlling method including calculating a cost for each of available block recycling schemes based on a multi-block erase function when the multi-block erase function is supported, the multi-block erase function being a function that simultaneously erases data stored in a plurality of blocks of a flash memory and selecting at least one scheme from among the available block recycling schemes based on the calculated cost, and managing at least one block using the at least one method selected from among the available block recycling schemes.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: October 8, 2013
    Assignee: OCZ Technology Group Inc.
    Inventors: Jongmin Lee, Donghee Lee, Hanmook Park
  • Publication number: 20130246732
    Abstract: A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells.
    Type: Application
    Filed: June 21, 2012
    Publication date: September 19, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kian-Fui Seng, Ming-Hui Tseng, Ching-Hsien Wang
  • Patent number: 8539142
    Abstract: Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Junji Ogawa, Atsushi Kawamura
  • Patent number: 8533422
    Abstract: An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Samantika Subramaniam, Aamer Jaleel, Simon C. Steely, Jr.
  • Patent number: 8527737
    Abstract: The described embodiments determine if two addressed memory regions overlap. First, a first address for a first memory region and a second address for a second memory region are received. Then a composite address is generated from the first and second addresses. Next, an upper subset and a lower subset of the bits in the addresses are determined. Then, using the upper and lower subsets of the addresses, a determination is made whether the addresses meet a condition from a set of conditions. If so, a determination is made whether the lower subset of the bits in the addresses meet a criteria from a set of criteria. Based on the determination whether the lower subset of the bits in the addresses meet a criteria, a determination is made whether the memory regions overlap or do not overlap.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 3, 2013
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 8503258
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Patent number: 8499115
    Abstract: A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: July 30, 2013
    Assignee: Via Technologies, Inc.
    Inventor: Ming-Xing Gao
  • Patent number: 8495292
    Abstract: An apparatus and system are disclosed for an in-server storage area network (“SAN”). A first storage controller is included within a first server. The first storage controller controls at least one storage device. The first server includes a network interface shared by the first server and the first storage controller. A storage communication module is included that facilitates communication between the first storage controller and at least one device external to the first server, where the communication between the first storage controller and the external device is independent from the first server. An in-server SAN module is included that services a storage request using at least one of a network protocol and a bus protocol. The in-server SAN module services the storage request independent from the first server, the service request received from a client.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: July 23, 2013
    Assignee: Fusion-io, Inc.
    Inventors: David Flynn, David Atkisson, Bert Lagerstedt, John Strasser, Jonathan Thatcher, Michael Zappe
  • Publication number: 20130185493
    Abstract: Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Paul H. Muench, Cheng-Chung Song