Abstract: A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

Abstract: The disclosure provides a method and for cloud service migration. The method comprises: obtaining a migration request related to a cloud service hosted in a source cluster, the migration request comprising a scheduled migration time to migrate the cloud service from the source cluster to a target cluster; migrating, based on the scheduled migration time, disk data associated with an original instance of the cloud service to a disk for servicing a new instance of the cloud service instantiated in the target cluster, the migration of the disk data being performed based on a migration priority order of the disk data; and configuring a data operation of the cloud service for a disk for servicing the original instance as a data operation for the disk for servicing the new instance.

Abstract: In an apparatus, a memory controller, a memory device, and a method for switching frequencies of clock signals to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, a frequency of a clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to assertion of a status signal that indicates a busy operation status of the memory device according to the command, and switches the frequency of the clock signal to a high frequency according to de-assertion of the status signal that indicates a ready operation status of the memory device.

Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

Abstract: Examples include a system comprising a non-volatile memory to store a machine-learning data structure. Examples access the machine-learning data structure with a first processing resource, and examples access the machine-learning data structure with a second processing resource, which includes at least one graphics processing core, such that the machine-learning data structure is a shared memory space of the first processing resource and the second processing resource.

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a volatile memory, a non-volatile storage unit, and a controller. The data storage device further includes a plurality of virtual functions, where at least one of the virtual functions is only accessible by the data storage device and the remainder of the virtual functions are accessible by both the data storage and a host device. At least one of the virtual functions may be dedicated to completing data storage device storage management operations.

Abstract: Various implementations described herein relate to systems and methods for managing metadata for power loss, including determining first metadata for first data, sending the first data to the non-volatile memory to be programmed to the first new locations of the non-volatile memory, and discarding the first metadata in response to detecting an imminent interruption to operations of the storage device. The first completion status for programming of the first data is unknown at the time of detecting the imminent interruption. The first data is read from first original locations of a non-volatile memory. The first metadata includes a first physical address for each of first new regions of the non-volatile memory.

Abstract: According to one embodiment, a memory circuit includes a plurality of nonvolatile memory cells and a control circuit. Each of the plurality of nonvolatile memory cells loses stored data when the stored data is read. The control circuit reads data from a first memory cell among the plurality of memory cells as designated by a first instruction but does not write the data read from the first memory cell back to the first memory cell after the first instruction is received. The control circuit reads data from a second memory cell among the plurality of memory cells as designated by a second instruction and writes the data read from the second memory cell back to the second memory cell after the second instruction is received.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.

Abstract: In some examples, a system detects recovery, from an unavailable state, of a communication link between a first storage system that includes a first storage volume and a second storage system that includes a second storage volume that is to be a synchronized version of the first storage volume, where while the communication link is in the unavailable state the second storage volume is in an offline state and the first storage volume is in an online state.

Abstract: Methods and systems for managing data storage strategies for continuous video segment recordings on a video recording device are disclosed. The data storage strategies include the detection of various trigger events and ending events detected from the video recordings or measurements detected from sensor devices that are included in the video recording device.

Abstract: A method is used in sizing volatile memory (VM) cache based on flash-based cache usage. A user selection for a flash-based cache is received. Based on the selection, configuration and sizing factors are provided, by a flash based cache driver, to VM cache size determination logic. Based on the configuration and sizing factors and a sizing formula and rules, a requested VM cache size is produced by the VM cache size determination logic. Based on the requested VM cache size, the VM cache is caused, via VM cache resizing logic, to be resized to the requested VM cache size.

Abstract: A multi-tiered system of data storage includes a plurality of data storage solutions. The data storage solutions are organized such that the each progressively faster, more expensive solution serves as a cache for the previous solution, and each solution includes a dedicated data block to store individual data sets, newly written in a plurality of write operations, for later migration to slower data storage solutions in a single write operation.

Abstract: In a particular embodiment, a controller is adapted to perform a garbage collection operation to remove redundant data, to predict a performance parameter associated with performance of the garbage collection operation, and to abort the garbage collection operation when the predicted performance parameter exceeds a threshold.

Abstract: A solid state disk controller includes a volatile memory having a memory area storing sector bit map values, and a memory controller. In a read operation, the memory controller selectively reads at least one sector among a plurality of sectors forming a page of an external non-volatile memory based on the sector bit map values stored in the memory area, indicated by a pointer.

Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.

Abstract: A method of changing a program for controlling a disk drive that includes an EEPROM. The method includes storing a program block to a disk area such that the program block is associated with a second area for storing the program block that is not utilized for a read operation from the disk area. The method also includes storing a program block that is associated with a first area to an area that includes at least a portion of the second area in the EEPROM such that the first area contained a program block that is utilized for a read operation from the disk area. In addition, the method includes changing the program block in the first area after storing to the second area. Moreover, the method includes storing to the second area the program block that is not utilized for a read operation from the disk area after storing to the first area.

Abstract: The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.

Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

Abstract: A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic receives an address and predicts in which one of the cache ways the data associated with the address is likely to be stored. The way prediction logic causes an enabling signal to be supplied only to the way predicted to contain the requested data. The remaining (N?1) of the cache ways do not receive the enabling signal. The power consumed by the cache is thus significantly reduced.

Abstract: A data access method for an application circuit to access a memory. The method includes steps of: receiving a first data from the application circuit; duplicating the first data to obtain a duplicated first data; and writing the first data and the duplicated first data into the memory at continuously accessible addresses. For accessing to the first data, the first data and the duplicated first data are read from the memory in response to a rising edge and a falling edge of a data-triggering signal; and one of the first data and the duplicated first data is outputted while the other of the first data and the duplicated first data is discarded.

Abstract: A memory apparatus is provided. The memory apparatus includes a first memory chip, a second memory chip and a control unit configured to manage a first mapping table for the first memory chip and a second mapping table for the second memory chip. If a first physical address of the second memory chip is allocated to a first logical address of the first memory chip, the control unit is configured to update a second logical address of the second memory chip to correspond to the first physical address of the second memory chip in the second mapping table and update the first logical address of the first memory chip to correspond to the second logical address of the second memory chip in the first mapping table.

Abstract: In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.

Abstract: Embodiments of the present invention provide a semiconductor storage device (SSD) system based on asymmetric RAID storage. Specifically, embodiments of this invention provide a set of (at least one) of RAID controllers coupled to a host computer. A set of storage drives is coupled to each asymmetric RAID controller. The RAID method and configuration of each storage device are dynamically adapted based on user policy parameters and storage performance characteristics.

Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.

Abstract: A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a memory control unit. The memory control unit is commonly connected to the first and second memory devices via a command/address bus and a portion of a data bus, and is connected to the second memory device via another portion of the data bus.

Abstract: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.

Abstract: A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section, the memory array section and the interface section being sealed in a package. The interface section includes a plurality of interface modules configured to correspond to a plurality of memory types on a one-to-one basis, and a clock generation section configured to generate a plurality of clock signals based on a system clock signal supplied by the external memory controller. The generated clock signals are used by the plurality of interface modules. The interface section further includes a mode interpretation section configured to interpret an input mode designation signal as indicative of one of the memory types in order to output a mode signal denoting the interpreted memory type.

Abstract: An information retrieval apparatus includes an acquiring unit that acquires a numerical value defining a boundary of a numerical range; a detecting unit that detects a number of places in and a head numeral of the numerical value; an extracting unit that extracts from a bit string group, a bit string indicating whether a numerical value in a numerical value group having the number of places and the head numeral is present in files subject to retrieval; a specifying unit that specifies a file corresponding to a bit in the extracted bit string, the bit indicating the presence of a numerical value of the numerical value group; a determining unit that determines whether a numerical value in the specified file meets the boundary condition; and a designating unit that, based on a determination by the determining unit designates the specified file to have a numerical value within the numerical range.

Abstract: A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to an indicator corresponding to the microcode architectural register and indicating that a pointer to the physical register and corresponding to the microcode architectural register is an active pointer.

Abstract: Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.

Abstract: Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed.

Abstract: Methods and systems capable of capitalizing on fast access capabilities (low initial access latencies) of nonvolatile memory technologies for use in a host system, such as computers and other processing apparatuses. The host system has a central processing unit, processor cache, and a system main memory. The system main memory includes first and second memory slots, a volatile memory subsystem having at least one DRAM-based memory module received in the first memory slot and addressed by the central processing unit, and a nonvolatile memory subsystem having at least a first nonvolatile-based memory module in the second memory slot and addressed by the central processing unit. At least one memory controller is integrated onto the central processing unit for controlling the processor cache, the volatile memory subsystem, and the nonvolatile memory subsystem.

Abstract: A technique for efficiently preserving the ordering of data being written to a nonvolatile memory through a subsystem of a network storage system in the event of a power disruption, where the subsystem does not inherently guarantee that the ordering of the data will be preserved. The subsystem can be, for example, a memory controller hub. During normal operation of the system, data is written to the nonvolatile memory without flushing the data to the nonvolatile memory. In response to a power disruption in the system, data sources in the system that can initiate write transactions destined for the nonvolatile memory are inhibited from initiating write transactions destined for the nonvolatile memory, and pending write data within the subsystem is allowed to be committed to the nonvolatile memory. The nonvolatile memory is then placed into a self-refresh state.

Abstract: A method of converting a hybrid hard disk drive (HDD) to a normal HDD when a system is powered on depending on whether the total number of defective blocks in a non-volatile cache (NVC) exceeds a predetermined threshold. The method of converting a hard disk drive (HDD) from a hybrid HDD to a normal HDD where the HDD has a normal hard disk and a non-volatile cache includes the steps of determining whether a mode conversion flag is enabled during a power-on period. When the mode conversion flag is enabled, operating the HDD as a normal HDD. When the mode conversion flag is disabled, determining whether an operating mode of the HDD is a normal mode or a hybrid mode. When the operating mode of the HDD is in the normal mode, the HDD operates as a normal HDD. A determination is made when the HDD is in the hybrid mode as to whether the total number of defective blocks in the non-volatile cache is greater than a predetermined threshold.

Abstract: Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed.

Abstract: A system allows one or more hybrid hard disks or any other storage devices to share a logical nonvolatile device formed by one or more non-volatile memory devices. The system comprises a control logic to reserve on a hybrid hard disk a space that corresponds to a non-volatile memory device in the hybrid hard disk and to use a space access instruction to access the non-volatile memory device. The control logic accesses the logical non-volatile memory device in an event that a content of a storage device is stored in the logical non-volatile memory device in response to an instruction to access the storage device.

Abstract: Systems and methods to manage database data are provided. A particular method includes automatically identifying a plurality of storage devices. The storage devices include a first device of a first type and a second device of a second type. The first type includes a solid state memory device. The method may further identify a high priority data set of the database. A rebalancing operation is conducted that includes moving the high priority data set to the solid state memory device and substantially evening distribution of other data of the database among the storage devices.

Abstract: Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed.

Abstract: An apparatus for accessing a memory is provided, and comprises a first device, a second device, an adjusting unit, a buffer and a memory. The first device operates at a first clock. The second device operates at a second clock. The buffer reads data from the second device to be written to the memory unit and reads from the memory unit to be read by the first device. The adjusting unit masks a portion of pulses of the first clock to generate an adjusted clock, wherein the first device reads the buffer according to the adjusted clock. The apparatus for accessing a memory is a video processor, and the first device and the second device are an input unit and an output unit of the video processor.

Abstract: In one example embodiment, a system and method are shown for receiving data that include a time stamp. The system and method also include building an Online Analytical Processing (OLAP) cube that includes a dimension, the dimension acting as a schema for the data that include the time stamp. The system and method may also include populating the OLAP cube with an object, the object including the data and the time stamp as at least one attribute. The system and method may also include storing the OLAP cube.

Abstract: In one embodiment, a hybrid storage device including a persistent memory, a volatile memory, a processor, a memory loader module that enables the processor to load a first set of information from the persistent memory device to the volatile memory device, to organize the first set of information according to a predetermined format, and a storage drive interface controller that enables the processor to receive information access requests from a host computer, to provide a second set of information from the volatile memory device to the host computer, and to provide a metadata descriptive of the first set of information to the host computer is disclosed. A host computer is enabled to access the first set of information using metadata provided by the storage drive interface controller without having the first set of information in a local memory of the host computer.

Abstract: A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.

Abstract: A method for reallocating blocks in a storage pool involves copying multiple source blocks to multiple replacement blocks, where the source blocks are stored on a source disk in the storage pool, and where the replacement blocks are stored on one or more replacement disks in the storage pool, and generating an indirection object, where the indirection object includes a mapping of locations of the source blocks to locations of the replacement blocks.

Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.