Abstract: A microcontroller includes a memory, direct memory access (DMA) controllers and a microprocessor. The microprocessor maintains one or more memory protection (MP) configurations to control access to protected memory areas of the microcontroller. In response to a secure service call of an unsecure user-application, the microprocessor executes a state machine which disables interrupt requests, determining whether DMA controller configurations and MP configurations satisfy secure-service criteria. When the secure-service criteria are satisfied, at least one secure operation associated with the secure service call is performed, and memory areas accessed during the execution of the at least one secure operation are cleaned. The interrupt requests are re-enabled and a response to the secure service call is generated.

Abstract: Multi-mode protected memory in accordance with the present description includes a permanent mode and a transient mode of operation. In one embodiment of the permanent mode, an authentication key is programmable once and a write counter is not decrementable or resettable. In one embodiment of the transient mode, an authentication key may be programmed many times and a write counter may be reset many times. Other features and advantages may be realized, depending upon the particular application.

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

Abstract: An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.

Abstract: Disclosed is a register data checking device including: an original parity-bit generator generating an original parity bit according to register data to be inputted into a register, and then writing the original parity bit to the register; and a detecting circuit. The detecting circuit includes: a scanning circuit reading the register data and the original parity-bit from the register; an arbitrator enabling the scanning circuit when an access status of the register is free, and thereby forwarding the register data and the original parity bit from the scanning circuit; at least one controlled parity-bit generator generating a controlled parity bit according to the register data from the arbitrator when the access status of the register is free; and at least one parity-bit checking circuit comparing the original parity bit from the arbitrator with the controlled parity bit when the access status is free, and thereby outputting a check result.

Abstract: A control device of the present embodiment has a communication I/F, a built-in non-volatile memory, a controller, an external-serial-memory I/F, a security management module, and an access controller. The communication I/F enables communication with outside. The built-in non-volatile memory has a first storage region, which stores an initialization program which carries out initialization operation, and a second storage region, which stores currently used firmware which is executed after the initialization operation and acquires firmware for update via the communication I/F. The controller executes the initialization program and the currently used firmware. The external-serial-memory I/F communicably connects the device of its own to an external non-volatile memory via a serial bus. The security-mode management module fixes an access control setting of the built-in non-volatile memory and the external non-volatile memory. The access controller outputs a level signal different from the serial bus.

Abstract: A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.

Abstract: An erasing device includes: a first connector that is detachably connected to a storage device; a second connector that is detachably connected to an information processing device; a data eraser that erases information stored in the storage device after the storage device and the information processing device are connected to one another; and an access controller that, after the information stored in the storage device is erased by the data eraser, brings the information processing device from a state where the information processing device cannot access the storage device into a state where the information processing device can access the storage device.

Abstract: Register restoration using recovery buffers. A restore request initiated by an application to restore one or more registers indicated by the restore request is obtained. The one or more registers are restored using a recovery buffer. The restoring scans the recovery buffer for the one or more registers indicated by the restore request, and restores the one or more registers using one or more values obtained from the recovery buffer.

Abstract: A mechanism and method for accessing message data in a shared memory by at least one client, includes an allocation of data in the shared memory, the memory configured in a plurality of buffers, and accessing the data by a client or a server without locking or restricting access to the data.

Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.

Abstract: A method of processing exceptions in an exception-driven computing-based system that operates in either initialization mode or exception-driven mode. The method includes, upon detecting an exception has occurred, causing the processor to execute exception handling instructions. When the system is operating in initialization mode the exception handling instructions invoke a first exception handler that causes a main register set to be saved before processing the exception and restored after processing the exception, and when the system is operating in exception-driven mode the exception handling instructions invoke a second exception handler that does not cause the main register set to be saved and restored. In some examples, the exception handling instructions are initially configured to invoke the first exception handler and are dynamically updated when the system switches from initialization mode to exception-driven mode to invoke the second exception handler.

Abstract: One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction. The datapath is configured to provide the opcode and the operand to the arithmetic logic unit. The address violation detection logic determines whether a heap memory access is a violation according to the operand and the final address on receiving the compare signal from the arithmetic logic unit.

Abstract: A data processing system 2 including processing circuitry 4 operating in either a first mode or a second mode. Page table data 30 including access control bits 40, 42, is used to control permissions for memory access to memory pages. In the first mode, the access control bits include at least one instance of a redundant encoding. In the second mode, the redundant encoding is removed to provide more efficient use of the access control bit encoding space.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set.

Abstract: Various embodiments of the present invention provide systems and methods for selecting data encoding. As an example, some embodiments of the present invention provide methods that include receiving a data set to be written to a plurality of multi-bit memory cells that are each operable to hold at least two bits. In addition, the methods include determining a characteristic of the data set, and encoding the data set. The level of encoding is selected based at least in part on the characteristic of the data set. In some instances of the aforementioned embodiments, the characteristic of the data set indicates an expected frequency of access of the data set from the plurality of multi-bit memory cells.

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Abstract: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.

Abstract: An external storage medium management system takes into account the maintenance of data security in case an external storage medium has been taken out on emergency. It comprises an external storage medium device and an enclosure device, which is connected to a host side device and which accommodates the external storage medium device, the external storage medium device reports the result of authentication to the enclosure device in case authentication operation is done. On detection of extraction of the external storage medium device from the enclosure device, the external storage medium device of inhibits access to retained data and allows access to the data only in case the authentication in accordance with a preset system has met success.

Abstract: This invention relates to a method permanently write protecting a portion of a memory card. According to the invention a bit indicating permanent write protection or permanent write protection of a portion of the memory card is set in the specific data register of the memory card to indicate that all the write protect groups protected with write protecting command are permanently write protected. In another embodiments of the invention special commands are used to control the write protection of the portion of the memory card. This invention also relates to a partially permanently write protected memory card. The invention further relates to an electronic device, a software, a system and a module utilizing the method of the invention.

Abstract: A system and method for managing space availability in a distributed striped file system is provided. A master data server is configured to send space availability detection messages to a plurality of data volumes servers hosting constituent volumes of a striped volume set. If one of the constituent volumes in the striped volume set has a low-in-space flag set, then the master data volume instructs all of the constituent volumes to set a low-in-space required flag, and no further writes are accepted for the striped volume set. The low-in-space and low-in-space required flags represent two states, and these states are returned in response to subsequent space availability detection messages from the master data server. A procedure for utilizing reserved space to complete an accepted cross stripe write operation is also provided.

Abstract: While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the semiconductor memory comes into a second operation mode where the level of security is lower than that of the first operation mode, a command is inputted. Then, the second address information is acquired from the command. A control circuit in the semiconductor memory generates an address of 10 bits by using the first address information as a high-order 4 bits and the second address information as a low-order 6 bits and outputs the address to a memory array. With this operation, it becomes possible to read/write data from/to the memory array.

Abstract: Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.