Abstract: Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a single cycle which includes nodes on opposite sides of lower dimension tori. The cycles in adjacent backplanes hop different numbers of nodes.

Abstract: In a self-configuring store-and-forward computer network, a plurality of processors are each housed in an enclosure having a top surface and a bottom surface. Each processor has an associated block identification number. An array of m by n radially symmetric connectors are arranged on the top surface and on the bottom surface of each enclosure. Each connector has an associated connector identification number. The connectors physically and electronically couple the plurality of processors as a three-dimensional structure. Communications controller in each of the processors exchange the block and connector identification numbers between the processors and a host computer to determine an ordered list of connector numbers that is used to route messages between any of the processors and the host computer.

Abstract: A computer program receives a large plurality of module design parameters and provides as output a graphical representation of the design together with text files that rate module wireability, including die pad position, attachment of each die pad to its BGA pad, and net cross-over; summarizes input parameters; creates a truth table for rating wireability and thermal requirements; provides cost sensitive parameters such as gold area, drill size and number requirements.

Abstract: A device having a variable output electrical characteristic includes first and second output terminals and a number of switching circuits, each switching circuit having two states. One of the states produces a first electrical effect (such as an increased resistance) between the first and second output terminals, and the other state produces a second electrical effect (such as no change in resistance) between the first and second output terminals. A processor generates control signals that are applied to the switching circuits to place the switching circuits into a desired state such that the variable output characteristic between the first and second terminals is set to a desired value, which may be input from a user.

Abstract: A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.

Abstract: A method/operator is disclosed that modifies dimension structures and relations during processing in a multidimensional data cube. The online “blowup” operator disclosed uses one or more hierarchical structures to expand a hypercube in order to reveal internal connections between attributes in relations associated with the hypercube. The operator is generic and may be applied to any dimension using hierarchical structures to guide the process. Furthermore, it is applicable to any data warehouse design. The methods enable a user, performing multidimensional analysis, to view, online, internal connections between attributes when going from one level to another in the hierarchical structures. Such as when comparing complex health related statistics for individuals across different age periods or for individuals versus their ancestors. The methods disclosed, facilitate OLAP for more complex data than current designs do.

Abstract: A method/operator is disclosed that adjusts measurements during processing in a multidimensional data cube. The online “depth-of-field” operator disclosed varies the density of points in a representation of the multidimensional cube. The operator may be applied to any collection of dimensions and relations supported by the dimensions, using hierarchical structures to control the adjustments. It allows one to experiment online with the definition of relations during multidimensional possessing, thereby controlling the output of the synthesizing process. The operator may be used to equate attributes based on their hierarchical positions when processing measurements in a hypercube. Furthermore, it may be used to reveal hidden dependencies between variables when working with measurements with varying levels of granularity.

Abstract: A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4×8×4 torus topology.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the associative processor memory array while storing temporary results and parameters in the random access memory for a fully programmable, low-cost die suitable for consumer electronics applications. Parallel communication between thousands of memory words in the associative memory array and the random access memory is provided via logic hardware operative as source and destination for associative search and modify (compare and write) processing operations and also operative to read and write thousands of data elements from and to the random access memory. The tags register also serves as a communication bus for parallel communication between associative memory words.

Abstract: A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.

Abstract: An interconnection network used for a multiprocessor system. An indirect n-dimensional rotator graph network having a transmission path of arbitrary nodes in a multiprocessor system including n! nodes includes n! input ports, n! output ports, a first stage switch module including n! demultiplexers, second through (n-1)th stage switch modules each having n! n.times.n crossbar switches, and an nth stage switch module including n! multiplexers, in which the switches or the demultiplexers composing switch modules of first to (n-1)th stages comprise n generators g.sub.1, g.sub.2, . . . , g.sub.n, the g.sub.1 is connected to a switch or multiplexer of a later stage having an identifier identical to that of a demultiplexer or switch, to which the g.sub.1 is included, and the g.sub.i (2.ltoreq.i.ltoreq.

Abstract: A node disjoint path forming method for a hypercube having a damaged node which is capable of using unused nodes (surplus nodes) in an n-number of node disjoint paths each having a length of n with respect to n-dimensional hypercubes more than 4-cube, so that it is possible to obtain an n-number of node disjoint paths each having a length of n even though there are damaged nodes. The method includes the steps of a first step for forming a linear arrangement consisting of an n-number of integers (0, 1, 2, . . .

Abstract: A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The computer has a plurality of processing elements, each including a memory. Each memory includes a plurality of storage locations for storing a data item, each storage location within the computer being identified by an address, comprising a plurality of address bits having a global portion comprising a processing element identification portion and a local portion identifying the storage location within the memory of the particular processing element. The system generates a program to facilitate use of a predetermined set of tools to effect a reassignment of data items among processing elements and storage location to, in turn, effect a predetermined rearrangement of address bits. The system includes a global processing portion and a local processing portion.

Abstract: In a parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of the processor elements has a storage unit to store data to be processed, the controller controls operation of the processor elements, and the parallel computer system performs processing of the data based on a calculation control signal transmitted from the controller. The parallel computer system further a data collection unit connected between the processor elements and the controller for receiving output data from the processor elements, performing a predetermined calculation, and outputting calculated data to the controller; and a calculation control unit connected between the data collection unit and the controller for transmitting the calculation control signal from the controller to the data calculation unit to make it possible to perform the predetermined calculation in the data collection circuit.