Abstract: A method and system are provided for providing a service address space for diagnostics collection. The system includes: a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and a storage update receiving component for updating the service address space by receiving storage update packets from the main processor and applying these to the service address space. An instruction pipe may be provided between the main processor and the service co-processor. The main processor may include: a service delegation component for delegating collection of diagnostic data to the co-processor by sending a collection command from the main processor to the service co-processor for collection of data from the service address space.

Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract: A radiofrequency transceiver device includes at least one reconfigurable integrated circuit (RIC) and a system controller that is able to reconfigure the at least one RIC to perform specific processing tasks. The specific processing tasks may be related to processing at least one radiofrequency signal that is received by, stored on, retrieved from and/or transmitted by the radiofrequency transceiver device. Embodiments may also include one or more reconfigurable integrated circuit applications (RIC Apps) that may be executed, at least in part, on the at least one RIC.

Abstract: A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.

Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.

Abstract: Example implementations described herein are related to methods for dynamically throttling host commands (up or down) to disk drives that include cache memory and rotating media, based on environmental conditions and/or drain rate from the cache memory to the rotating media, to provide consistent throughput for extended periods of time, and to avoid dramatic swings in performance from the pre-saturation state to the post-saturation state. The example implementations may be further extended to dynamically throttling host commands to devices that have HDD and SSD portions.

Abstract: Techniques for metadata-driven dynamic content serving. Metadata content is stored as a source instance, the metadata content is to be utilized to provide dynamically-constructed pages of content. The metadata content is published to one or more runtime pods communicatively coupled to receive the metadata content. A request for content is received with a selected one of the one or more runtime pods. Content is provided in response to the request as a response with the selected runtime pod utilizing the metadata content published from the source instance.

Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.

Abstract: A reconfigurable data processor architecture. The processor architecture includes: a first plurality of data processing elements, each having a respective synchronization unit, a data link structure adapted for dynamically interconnecting a number of the data processing elements, at least one configuration register, and at least one control unit in operative connection with the configuration register for controlling a contents thereof, wherein, based on the contents, the first plurality of data processing elements is adapted for temporarily constituting at runtime at least one group of one or more of said data processing elements from said first plurality of data processing elements dynamically via the data link structure. The synchronization units are adapted for synchronizing data processing by individual data processing elements within the group. The first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime.

Abstract: Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.

Abstract: An exemplary aspect relates generally to graphics processing systems and more specifically relates to executing vertex and fragment shading operations to a pixel blender device. The technology is at least applicable to graphics processing systems in which vertex and fragment shading operations are executed by dedicated fragment and vertex units or by unified shading units. The graphics processing unit driver is responsible to determine if a shading operation can be assigned to a multi-threaded, multi-format pixel blender. Based on the determination, the fragment shading operations or the vertex shading operations or both are assigned to the pixel blender for execution; the execution of the fragment and/or vertex shading operations by the shader unit(s) is skipped. The determination is based on a code analysis. Forwarding shading operations from the fragment and vertex shaders, i.e.

Abstract: A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue empty flags are grouped using programmable circuit means to form self-synchronised threads. Data from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data-paths allowing the array to be configured for use in various applications.

Abstract: The disclosed invention provides a solution for the problem of blending colors in a graphics processing unit. The plurality of blending equations used in various graphics layers is performed with a programmable streaming processor. Multiple simultaneous threads are used to eliminate pipeline latency and memory stalls. Overlays of predefined blending modes are used to minimize the time instruction memory is updated. The processing unit includes: (a) an instruction memory (b) hardware context registers for each executing stream (c) pipelined arithmetic units of predefined precision, including support for floating point (d) units that convert multi-format data to and from floating point precision (e) Look-up tables for quick color space transformations.

Abstract: An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements.

Abstract: A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.

Abstract: A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code.

Abstract: The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions.

Abstract: The illustrative embodiments provide for a system and recordable type medium for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and columns. Ones of the columns represent corresponding ones of computer applications that can start or stop in parallel with each other in a data processing system. Ones of the rows represent corresponding ones of sequences of actions within a corresponding column. Additionally, the table represents a definition of relationships among memory address spaces, wherein the table represents when each particular address space is started or stopped during one of a start-up process, a recovery process, and a shut-down process. The resulting table is stored.

Abstract: A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, each module being connectable to receive input operands indicated in an instruction, and a programmable lookup table connectable to receive dynamic configuration information determined from an opcode portion of the instruction and capable of generating operator configuration settings defining an aspect of the function or behavior of a configurable operator module, responsive to said dynamic configuration information in the instruction.

Abstract: A technique for performing power management for configurable processor resources of a processor determining whether to increase, decrease, or maintain resource units for each of the configurable processor resources based on utilization of each of the configurable processor resources. A total weighted power number for the processor is substantially maintained while resource units for each of the configurable processor resources whose utilization is above a first level is increased and resource units for each of the configurable processor resources whose utilization is below a second level is decreased. The total weighted power number corresponds to a sum of weighted power numbers for the configurable processor resources.

Abstract: A user can manage battery consumption of a mobile device using a mobile device battery management program which provides improved battery management functions, such as a dynamic battery use estimator, a battery threshold manager, and a profile based battery manager. Using the dynamic battery use estimator, the user can input different configuration settings of the mobile device and get estimates of the projected remaining battery life for the inputted configuration settings before applying any change to the operational configuration setting. The battery threshold manager allows the user to select a trigger and set its associated condition for turning off at least one application, service, or component of the mobile device when the condition is reached. Using the profile based battery manager, the user can select one of multiple profiles and set the mobile device to operate in an operational configuration setting corresponding to the selected profile.

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20a through 20n from each other.

Abstract: The invention provides a method of compiling computer program instructions for implementation on a reconfigurable processor comprising a plurality of operational cells, each operational cell being connectable to and disconnectable from one or more of the other operational cells via a programmable interconnect, the method comprising: a routing step in which one or more signal processing paths are determined for performing one or more signal processing operations defined by the computer program instructions, each signal processing path comprising two or more of the operational cells connected via the programmable interconnect, the said signal processing paths being capable of implementation on the said operational cells and the said interconnect of the reconfigurable processor to perform the said one or more signal processing operations; and a post-routing step performed subsequent to the routing step in which an extended signal processing path is determined by extending one of the said signal processing paths

Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

Abstract: A method of manufacture of a computing system includes: executing a first application, active and implemented as hardware within a hardware component having of one or more of reconfigurable hardware devices; detecting a trigger event in a first microkernel; generating a first hardware descriptor based on the trigger event, the first hardware descriptor to configure a portion of the hardware component for the first application or a second application; and configuring the portion of the hardware component with the first hardware descriptor while the first application executes concurrently.

Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.

Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.

Abstract: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Abstract: Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.

Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.

Abstract: For storage area network configuration across redundant fabrics, a set of redundant fabrics is defined. A fabric is a network between devices of a storage area network. A first fabric communicates with the other fabrics in a set of redundant fabrics to send configuration information. Each redundant fabric examines the first fabric's configuration information for devices to which the redundant fabric is also connected and resolves ports for devices to which the first fabric and the redundant fabric are connected to provide ports on the redundant fabric equivalent to the ports on the first fabric.

Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: An image processing apparatus includes plural auxiliary processing devices and a distribution section. The plural auxiliary processing devices perform predetermined processing on image data. The distribution section divides image data for one page into plural processing units, and distributes the plural processing units respectively to the auxiliary processing devices. The distribution section calculates the number of divisions indicating the number of pieces into which image data for one page is to be divided, in accordance with the number of auxiliary processing devices, the number of processing units that one auxiliary processing device is capable of simultaneously receiving and processing, and a degree of page parallelism indicating the number of pages of image data to be input while one auxiliary processing device processes image data for one page; divides the image data for one page into processing units; and distributes the processing units respectively to the auxiliary processing devices.

Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.

Abstract: A print control apparatus includes rendering units performing rendering in response to a print instruction described in a page description language; a print instruction storage unit storing the print instruction for printing pages; a distribution unit sequentially distributing process requests, each specifying which page is to be rendered, and reference information for accessing the print instruction, to the rendering units; and a process request storage unit storing process requests. The rendering units each execute rendering by accessing the print instruction based on the reference information, and extracting a part of the print instruction of a specified page to image data. The distribution unit distributes a process request when there is a rendering unit to which the process request is distributable in ascending order, and, when there is no such rendering unit, stores the process request, and selects and distributes a smallest-page-number process request to one rendering unit.

Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.

Abstract: A method and apparatus for providing a scalable computing array are provided herein. The method includes determining a width of a processor based on a software program, and a specified policy. The processor may be configured to comprise a number of lanes based on the width, and a thread of the software program may be executed using the configured processor.

Abstract: Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time when the configuration of each of the implementation systems is adopted and determines the optimum one of the implementation systems based on a combination of the estimated processing time and the circuit scale of the configuration.

Abstract: To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.

Abstract: An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements.

Abstract: Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.

Abstract: Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.

Abstract: An internal buffer is provided for a DRP core. A selector SEL switches input/output destination of the DRP core between external memory and an internal buffer. Control software executed by a CPU core receives information a pipeline of configurations for a sequence of target processing and generates combinations as to whether the processing result is transferred between the configurations via the external memory or via the internal buffer as transfer manners. Next, for each manner, bandwidth and performance of the external memory used by the DRP core in the manner are calculated. The manner of the best performance satisfying a previously specified bandwidth restriction is selected among the manners and the selector SEL is switched in accordance with the manner.

Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Abstract: Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules packets for transmission. The network processor generates tasks corresponding to each received packet associated with a data flow. A traffic manager receives tasks provided by one of the processing modules and determines a queue of the scheduling hierarchy corresponding to the task. The queue has a parent scheduler at each of one or more next levels of the scheduling hierarchy up to a root scheduler, forming a branch of the hierarchy. The traffic manager determines if the queue and one or more of the parent schedulers of the branch should be restructured. If so, the traffic manager drops subsequently received tasks for the branch, drains all tasks of the branch, and removes the corresponding nodes of the branch from the scheduling hierarchy.

Abstract: A dynamic reconfigurable circuit including a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port, a data network that is coupled to the arithmetic data input ports and the output ports of the plurality of processing elements, a configuration memory that is coupled via a configuration path to the configuration data input port of a first processor element being at least one of the plurality of processing elements, and an immediate value network that is independent from the data network and that is coupled to the configuration data input port of a second processor element being at least one of the plurality of processing elements. An internal register of a third processor element is coupled to the immediate value network so that data stored in the internal register can be outputted to the immediate value network.