Reconfiguring Patents (Class 712/15)
  • Patent number: 10540284
    Abstract: A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Dirk Wendel, Oliver Bibel, Joachim Fader, Wilhard Christophorus Von Wendorff
  • Patent number: 10467183
    Abstract: Methods and apparatuses relating to pipelined runtime services in spatial arrays are described.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Kermin Fleming, Jr., Simon C. Steely, Jr., Kent D. Glossop
  • Patent number: 10445451
    Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Kermin Fleming, Kent D. Glossop, Simon C. Steely, Jr., Ping Tak Peter Tang
  • Patent number: 10380969
    Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: August 13, 2019
    Assignee: Google LLC
    Inventors: Albert Meixner, Neeti Desai, Dilan Manatunga, Jason Rupert Redgrave, William Mark
  • Patent number: 10354031
    Abstract: An information processing method is disclosed, including: determining a module for which a design for testability (DFT) processing is needed, in a chip; establishing, in an including manner, a DFT signal transmission channel in the module for which the DFT processing is needed, and generating a channel file by using a corresponding port signal; and interpenetrating the DFT signal transmission channel layer by layer until the top layer of the chip, according to an instantiated reference relationship. An information processing device and a computer storage medium are also disclosed.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: July 16, 2019
    Assignee: Sanechips Technology Co., Ltd.
    Inventor: Fan Zhang
  • Patent number: 10275244
    Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 30, 2019
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
  • Patent number: 10268478
    Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
  • Patent number: 10224934
    Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 5, 2019
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 10185608
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: January 22, 2019
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
  • Patent number: 10074143
    Abstract: Techniques for determining a location of an entity are described. A determination module using member profile data may determine the location of the entity. Member profile data can include information about a member's employer and the employer's location. The determination module accesses member profiles from a social network. Additionally, the determination module may create a subgroup of entity-related member profiles from the accessed member profiles. The entity-related member profiles can be associated with a specific entity. Furthermore, the determination module may determine a suggested location for the specific entity based on location information derived from the related member profiles. Moreover, the determination module may calculate a connection density for the specific entity based on connections associated with the entity-related member profiles.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 11, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ke Wang, Songtao Guo, Baoshi Yan, Alex Ching Lai
  • Patent number: 9874923
    Abstract: A device comprising a battery, a memory, a data acquisition circuit and a processor. The sensors may sample a current state of a dynamic process. The data acquisition circuit may have a first clock rate based on a sampling rate of the dynamic process. The data acquisition circuit may read sensor information from the sensors. The processor may have a second clock rate. The processor may process the sensor information and generate a monitoring signal based on at least one of the sensor information, a model of the dynamic process and a desired state of the dynamic process. The processor may schedule procedures for the device and determine computation times for the procedures based on context information. The second clock rate is faster than the first clock rate. The procedures are scheduled based on the sampling rate, the computation times for the procedures and opportunities to enter a standby mode to conserve power.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: January 23, 2018
    Assignee: Invent.ly, LLC
    Inventors: Stephen J. Brown, Daylyn M. Meade, Timothy P. Flood, Clive A. Hallatt, Holden D. Jessup, Hector H. Gonzalez-Banos
  • Patent number: 9805152
    Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 31, 2017
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 9703708
    Abstract: Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 11, 2017
    Assignee: INTEL CORPORATION
    Inventors: Alaa R. Alameldeen, Christopher B. Wilkerson, Eugene Gorbatov, Zeshan A. Chishti
  • Patent number: 9632833
    Abstract: Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 25, 2017
    Assignee: Throughputer, Inc.
    Inventor: Mark Henrik Sandstrom
  • Patent number: 9495310
    Abstract: A method of operation of a computing system includes: reconfigurable hardware devices having first application fragment and second application fragment; configuring virtual bus module having virtual bus for electrically coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for coupling the first application fragment and the second application fragment through the virtual bus; implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment; activating a signal buffer interface by the virtual bus module: activating a pin buffer dispatch module for storing the application data from application input buffer, and activating memory request port by roll-back table module, storing the application data, in response to the pin buffer dispatch module; and alerting a roll-back detector including dismissing the application data exceeds a roll-back threshold or
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 15, 2016
    Assignee: Xcelemor, Inc.
    Inventor: Peter J. Zievers
  • Patent number: 9470760
    Abstract: A method of wafer-level testing of a register programmable integrated circuit may be provided. The method may comprise transforming a microcode instruction and related data from an initializing processor format into tester format data, and applying the tester format data to the integrated circuit on a wafer.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Birol Akdemir, Onur Keles
  • Patent number: 9448911
    Abstract: A method and system are provided for providing a service address space for diagnostics collection. The system includes: a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and a storage update receiving component for updating the service address space by receiving storage update packets from the main processor and applying these to the service address space. An instruction pipe may be provided between the main processor and the service co-processor. The main processor may include: a service delegation component for delegating collection of diagnostic data to the co-processor by sending a collection command from the main processor to the service co-processor for collection of data from the service address space.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Harman, Neil W. Leedham, Kim P. Walsh, Andrew Wright
  • Patent number: 9417879
    Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Christopher B. Wilkerson, Alaa R. Alameldeen, Eugene Gorbatov, Zeshan A. Chishti
  • Patent number: 9356642
    Abstract: A radiofrequency transceiver device includes at least one reconfigurable integrated circuit (RIC) and a system controller that is able to reconfigure the at least one RIC to perform specific processing tasks. The specific processing tasks may be related to processing at least one radiofrequency signal that is received by, stored on, retrieved from and/or transmitted by the radiofrequency transceiver device. Embodiments may also include one or more reconfigurable integrated circuit applications (RIC Apps) that may be executed, at least in part, on the at least one RIC.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 31, 2016
    Assignee: QRC, INC. DBA QRC TECHNOLOGIES
    Inventors: Sinisa Peric, Thomas F. Callahan, III, Richard Louis Cellucci
  • Patent number: 9317475
    Abstract: A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: April 19, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Tsuguchika Tabaru
  • Patent number: 9292293
    Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: March 22, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Hee-Jun Park, Steven S Thomson, Ronald Frank Alton, Edoardo Regini, Satish Goverdhan, Pieter-Louis Dam Backer
  • Patent number: 9274984
    Abstract: A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: March 1, 2016
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventor: Martin Vorbach
  • Patent number: 9276995
    Abstract: Techniques for metadata-driven dynamic content serving. Metadata content is stored as a source instance, the metadata content is to be utilized to provide dynamically-constructed pages of content. The metadata content is published to one or more runtime pods communicatively coupled to receive the metadata content. A request for content is received with a selected one of the one or more runtime pods. Content is provided in response to the request as a response with the selected runtime pod utilizing the metadata content published from the source instance.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 1, 2016
    Assignee: salesforce.com, inc.
    Inventors: Philip N. Calvin, Brian Zotter, Eric G. Dorgelo
  • Patent number: 9274966
    Abstract: Example implementations described herein are related to methods for dynamically throttling host commands (up or down) to disk drives that include cache memory and rotating media, based on environmental conditions and/or drain rate from the cache memory to the rotating media, to provide consistent throughput for extended periods of time, and to avoid dramatic swings in performance from the pre-saturation state to the post-saturation state. The example implementations may be further extended to dynamically throttling host commands to devices that have HDD and SSD portions.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 1, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alain Chahwan, Jonathan V. Nguyen
  • Patent number: 9213677
    Abstract: A reconfigurable data processor architecture. The processor architecture includes: a first plurality of data processing elements, each having a respective synchronization unit, a data link structure adapted for dynamically interconnecting a number of the data processing elements, at least one configuration register, and at least one control unit in operative connection with the configuration register for controlling a contents thereof, wherein, based on the contents, the first plurality of data processing elements is adapted for temporarily constituting at runtime at least one group of one or more of said data processing elements from said first plurality of data processing elements dynamically via the data link structure. The synchronization units are adapted for synchronizing data processing by individual data processing elements within the group. The first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: December 15, 2015
    Assignee: Karlsruher Institut für Technologie
    Inventors: Ralf Konig, Timo Stripf, Jurgen Becker
  • Patent number: 9208008
    Abstract: Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 8, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan Shirlen, Victor Wong
  • Patent number: 9202308
    Abstract: An exemplary aspect relates generally to graphics processing systems and more specifically relates to executing vertex and fragment shading operations to a pixel blender device. The technology is at least applicable to graphics processing systems in which vertex and fragment shading operations are executed by dedicated fragment and vertex units or by unified shading units. The graphics processing unit driver is responsible to determine if a shading operation can be assigned to a multi-threaded, multi-format pixel blender. Based on the determination, the fragment shading operations or the vertex shading operations or both are assigned to the pixel blender for execution; the execution of the fragment and/or vertex shading operations by the shader unit(s) is skipped. The determination is based on a code analysis. Forwarding shading operations from the fragment and vertex shaders, i.e.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: December 1, 2015
    Assignee: THINK SILICON SA
    Inventors: Georgios Keramidas, Iakovos Stamoulis, George Sidiropoulos, Michael Koziotis
  • Patent number: 9158575
    Abstract: A shared resource multi-thread processor array wherein an array of heterogeneous function blocks are interconnected via a self-routing switch fabric, in which the individual function blocks have an associated switch port address. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. Thread queue empty flags are grouped using programmable circuit means to form self-synchronised threads. Data from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data-paths allowing the array to be configured for use in various applications.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: October 13, 2015
    Inventor: Graeme Roy Smith
  • Patent number: 9058680
    Abstract: The disclosed invention provides a solution for the problem of blending colors in a graphics processing unit. The plurality of blending equations used in various graphics layers is performed with a programmable streaming processor. Multiple simultaneous threads are used to eliminate pipeline latency and memory stalls. Overlays of predefined blending modes are used to minimize the time instruction memory is updated. The processing unit includes: (a) an instruction memory (b) hardware context registers for each executing stream (c) pipelined arithmetic units of predefined precision, including support for floating point (d) units that convert multi-format data to and from floating point precision (e) Look-up tables for quick color space transformations.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 16, 2015
    Assignee: THINK SILICON LTD
    Inventors: Iakovos Stamoulis, George Sidiropoulos, Theodore Roudas, Nikolaos Strikos
  • Patent number: 9037834
    Abstract: An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 19, 2015
    Assignee: Altera Corporation
    Inventors: Robert T. Plunkett, Ghobad Heidari, Paul L. Master
  • Patent number: 9021234
    Abstract: A computing section is provided with a plurality of computing units and correlatively stores entries of configuration information that describes configurations of the plurality of computing units with physical configuration numbers that represent the entries of configuration information and executes a computation in a configuration corresponding to a designated physical configuration number. A status management section designates a physical configuration number corresponding to a status to which the computing section needs to advance the next time for the computing section and outputs the status to which the computing section needs to advance the next time as a logical status number that uniquely identifies the status to which the computing section needs to advance the next time in an object code.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: April 28, 2015
    Assignee: NEC Corporation
    Inventors: Takeshi Inuo, Kengo Nishino, Nobuki Kajihara
  • Patent number: 9021235
    Abstract: A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 28, 2015
    Assignee: NEC Corporation
    Inventor: Kengo Nishino
  • Patent number: 9003274
    Abstract: The illustrative embodiments provide for a system and recordable type medium for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and columns. Ones of the columns represent corresponding ones of computer applications that can start or stop in parallel with each other in a data processing system. Ones of the rows represent corresponding ones of sequences of actions within a corresponding column. Additionally, the table represents a definition of relationships among memory address spaces, wherein the table represents when each particular address space is started or stopped during one of a start-up process, a recovery process, and a shut-down process. The resulting table is stored.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Joseph John Katnic
  • Patent number: 9002998
    Abstract: The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Altera Corporation
    Inventors: Paul L. Master, Bohumir Uvacek
  • Patent number: 8966223
    Abstract: A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, each module being connectable to receive input operands indicated in an instruction, and a programmable lookup table connectable to receive dynamic configuration information determined from an opcode portion of the instruction and capable of generating operator configuration settings defining an aspect of the function or behavior of a configurable operator module, responsive to said dynamic configuration information in the instruction.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: February 24, 2015
    Assignee: Icera, Inc.
    Inventor: Simon Knowles
  • Patent number: 8958854
    Abstract: A user can manage battery consumption of a mobile device using a mobile device battery management program which provides improved battery management functions, such as a dynamic battery use estimator, a battery threshold manager, and a profile based battery manager. Using the dynamic battery use estimator, the user can input different configuration settings of the mobile device and get estimates of the projected remaining battery life for the inputted configuration settings before applying any change to the operational configuration setting. The battery threshold manager allows the user to select a trigger and set its associated condition for turning off at least one application, service, or component of the mobile device when the condition is reached. Using the profile based battery manager, the user can select one of multiple profiles and set the mobile device to operate in an operational configuration setting corresponding to the selected profile.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 17, 2015
    Assignee: Cellco Partnership
    Inventors: Dorothy Beau Morley, Yuk Li, Damodar Bhandarkar, Joel Angiolillo
  • Patent number: 8959371
    Abstract: A technique for performing power management for configurable processor resources of a processor determining whether to increase, decrease, or maintain resource units for each of the configurable processor resources based on utilization of each of the configurable processor resources. A total weighted power number for the processor is substantially maintained while resource units for each of the configurable processor resources whose utilization is above a first level is increased and resource units for each of the configurable processor resources whose utilization is below a second level is decreased. The total weighted power number corresponds to a sum of weighted power numbers for the configurable processor resources.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: February 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thang M. Tran
  • Publication number: 20150039857
    Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 5, 2015
    Inventors: Paul L. Master, Stephen J. Smith, John Watson
  • Patent number: 8935510
    Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20a through 20n from each other.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: January 13, 2015
    Assignee: NEC Corporation
    Inventors: Hiroaki Inoue, Junji Sakai, Tsuyoshi Abe, Masato Edahiro
  • Publication number: 20140351557
    Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 27, 2014
    Inventors: Michael B. Doerr, William H. Hallidy, David A. Gibson, Craig M. Chase
  • Publication number: 20140351556
    Abstract: The invention provides a method of compiling computer program instructions for implementation on a reconfigurable processor comprising a plurality of operational cells, each operational cell being connectable to and disconnectable from one or more of the other operational cells via a programmable interconnect, the method comprising: a routing step in which one or more signal processing paths are determined for performing one or more signal processing operations defined by the computer program instructions, each signal processing path comprising two or more of the operational cells connected via the programmable interconnect, the said signal processing paths being capable of implementation on the said operational cells and the said interconnect of the reconfigurable processor to perform the said one or more signal processing operations; and a post-routing step performed subsequent to the routing step in which an extended signal processing path is determined by extending one of the said signal processing paths
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Inventors: Khodor Ahmad FAWAZ, Tughrul Sati ARSLAN
  • Patent number: 8880849
    Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Altera Corporation
    Inventors: Paul L. Master, Stephen J. Smith, John Watson
  • Publication number: 20140317378
    Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.
    Type: Application
    Filed: May 1, 2014
    Publication date: October 23, 2014
    Applicants: Synopsys, Inc., Fujitsu Semiconductor Limited
    Inventor: Mark David Lippett
  • Patent number: 8868894
    Abstract: A method of manufacture of a computing system includes: executing a first application, active and implemented as hardware within a hardware component having of one or more of reconfigurable hardware devices; detecting a trigger event in a first microkernel; generating a first hardware descriptor based on the trigger event, the first hardware descriptor to configure a portion of the hardware component for the first application or a second application; and configuring the portion of the hardware component with the first hardware descriptor while the first application executes concurrently.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: October 21, 2014
    Assignee: Xcelemor, Inc.
    Inventor: Peter J Zievers
  • Publication number: 20140258678
    Abstract: A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Hari Rao, Sami Khawam, Ioannis Nousias, Raghavan Thirumala
  • Patent number: 8832413
    Abstract: A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: September 9, 2014
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael B. Doerr, William H. Hallidy, David A. Gibson, Craig M. Chase
  • Patent number: 8819320
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 8812820
    Abstract: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: August 19, 2014
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Alexander Thomas
  • Patent number: 8798386
    Abstract: Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: August 5, 2014
    Assignee: Broadcom Corporation
    Inventors: Adrian Lees, David Plowman
  • Patent number: 8799623
    Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics S.A.
    Inventor: Joël Cambonie