Stack Based Computer Patents (Class 712/202)
  • Patent number: 10572261
    Abstract: A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in parallel. In response to a task identifier being received that is indicative of a task requiring an improved level of determinism, the dual-issue capability of at least one of the first thread or the second thread is temporarily disabled.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 25, 2020
    Assignee: NXP USA, Inc.
    Inventors: Alistair Paul Robertson, James Andrew Collier Scobie
  • Patent number: 10528448
    Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: January 7, 2020
    Assignees: The Board of Trustees of the Leland Stanford Junior University, New York University
    Inventors: Subhasish Mitra, Clark Barrett, David Lin, Eshan Singh
  • Patent number: 10438154
    Abstract: A system, method, and computer-readable medium are disclosed for performing a work item queuing operation. The work item queuing operation includes sending a work item from a producer to a processor; adding the work item to a generational queue upon sending the work item from the producer to the processor via a push operation; and, resending the work item from the producer to the processor via a pop operation when the work item is not processed by the processor, the work item queuing operation centralizing detection and reprocessing of items that were not processed due to work item loss.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 8, 2019
    Assignee: Dell Products L.P.
    Inventor: Luis E. Bocaletti
  • Patent number: 10433035
    Abstract: An apparatus includes telemetry registers, a memory, and a virtualized telemetry controller. The memory may store a set of telemetry profiles, including a first telemetry profile specifying a collection trigger, a set of telemetry registers, and a telemetry data destination. The virtualized telemetry controller may be to: detect a condition satisfying the collection trigger specified in the first telemetry profile; in response to a detection of the condition, read telemetry values from the set of telemetry registers specified in the first telemetry profile; generate a telemetry container including the telemetry values; and send the telemetry container to the telemetry data destination specified in the first telemetry profile.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Ronen Chayat, Andrey Chilikin, John J. Browne, Chris MacNamara, Tomasz Kantecki
  • Patent number: 10430580
    Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak K. Gupta
  • Patent number: 10416994
    Abstract: A control method includes building at least two stacks for an app, and managing the Activity components based on the at least two stacks.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: September 17, 2019
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventors: Rong Zeng, Can Wang, Rongfeng Feng, Qixin Xing
  • Patent number: 10387296
    Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel corporation
    Inventors: Youfeng Wu, Justin Gottschlich, Gilles Pokam, Shiliang Hu, Ali-Reza Adl-Tabatabai, Cristiano Pereira
  • Patent number: 10379865
    Abstract: A circuit includes an instruction scheduling circuit and an instruction buffer including entries. The entries each include an instruction, a validity indication, and an attribute. The instruction scheduling circuit partitions the entries into first sets, determines second sets by reordering the entries of each first set according to their attributes, determines a set ordering for the first sets according to a function of their attributes, and selects, based on the set ordering, instructions from the second sets. A process for selecting instructions to issue receives entries, each entry including an instruction, a validity indications, and an attribute. The process partitions the entries into first sets, determines second sets by reordering the entries of each first set according to their attributes, determines a set ordering for first sets according to a function of the attributes of their entries, and selects, based on the set ordering, instructions from the second sets.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 13, 2019
    Assignee: Marvell International Ltd.
    Inventors: Warren Menezes, Joshua Smith
  • Patent number: 10360374
    Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Abhishek Basak, Ravi L. Sahita, Vedvyas Shanbhogue
  • Patent number: 10346625
    Abstract: Systems, methods, and computer program products to perform an operation comprising monitoring a set of file access requests to a file from an application to obtain permission and identity information related to the monitored requests, wherein the monitoring includes obtaining a runtime stack from the application, determining, based on environment information in the runtime stack, whether a first set of privileges available to the application are greater than a second set of privileges available to a the user of the application, storing the permission and identity information and an indication of whether the first set of privileges is greater than the second set of privileges in a data file, and adjusting the privileges for the user based on the determination.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Anderson, Carol S. Budnik, Anna P. Dietenberger, Scott Forstie, Brian J. Hasselbeck, Allen K. Mei, Ellen B. Streifel, Jeffrey M. Uehling
  • Patent number: 10324852
    Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Theodros Yigzaw, Ashok Raj, Robert C. Swanson, Mohan J. Kumar
  • Patent number: 10296341
    Abstract: A processor and system for latest producer tracking In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that includes a producer tracking map, and a results buffer allocater circuit that includes a results buffer free list. Control logic modifies in-register status values stored in the register rename map based on producer tracking status values stored in the producer tracking map. The producer tracking status values stored in the producer tracking map are modified based on buffer identification values output by the results buffer allocater circuit.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 21, 2019
    Assignee: ARM Finance Overseas Limited
    Inventors: Kjeld Svendsen, Xing Yu Jiang
  • Patent number: 10210349
    Abstract: A data processing apparatus has processing circuitry which has a secure domain and a less secure domain of operation. When operating in the secure domain the processing circuitry has access to data that is not accessible in the less secure domain. In response to a control flow altering instruction, processing switches to a program instruction at a target address. Domain selection is performed to determine a selected domain in which the processing circuitry is to operate for the instruction at the target address. Domain checking can be performed to check which domains are allowed to be the selected domain determining the domain selection. A domain check error is triggered if the selected domain in the domain selection is not an allowed selected domain.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 19, 2019
    Assignee: ARM Limited
    Inventors: Thomas Christopher Grocutt, Richard Roy Grisenthwaite
  • Patent number: 10181030
    Abstract: Disclosed herein are methods, systems, and computer-readable media for blocking attempts at runtime redirection and attempts to change memory permissions during runtime. The present disclosure describes features that enable runtime detection of an attempt to redirect routines or change memory permissions, and determining whether to allow or deny the attempt. Such features may include changing memory write permissions on memory segments, such as those segments used by dynamic loaders after call associations have been saved or otherwise created. Other features may include swapping the addresses of system routines (e.g., open, read, write, close, etc.) to new routines that perform the same function as well as additional functionality configured to detect attempts to redirect or change memory permissions. Once detected by the new routine during runtime, a determination may be made to deny or allow the call based on a policy.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 15, 2019
    Assignee: Citrix Systems, Inc.
    Inventor: David Linde
  • Patent number: 9898290
    Abstract: A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Dan F. Greiner, Lisa C. Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 9898289
    Abstract: A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 9652240
    Abstract: Methods and apparatus for predicting the value of a stack pointer which store data when an instruction is seen which grows the stack. The information which is stored includes a size parameter which indicates by how much the stack is grown and one or both of: the register ID currently holding the stack pointer value or the current stack pointer value. When a subsequent instruction shrinking the stack is seen, the stored data is searched for one or more entries which has a corresponding size parameter. If such an entry is identified, the other information stored in that entry is used to predict the value of the stack pointer instead of using the instruction to calculate the new stack pointer value. Where register renaming is used, the information in the entry is used to remap the stack pointer to a different physical register.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: May 16, 2017
    Assignee: Imagination Technologies Limited
    Inventor: Hugh Jackson
  • Patent number: 9588881
    Abstract: A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Franck Fillere
  • Patent number: 9501637
    Abstract: Technologies for shadow stack support for legacy guests include a computing device having a processor with shadow stack support. During execution of a call instruction, the processor determines whether a legacy stack pointer is within bounds and generates a virtual machine exit if the legacy stack pointer is out-of-bounds. If not out-of-bounds, the processor pushes a return address onto the legacy stack and onto a shadow stack protected by a hypervisor. During execution of a return instruction, the processor determines whether top return addresses of the legacy stack and the shadow stack match, and generates a virtual machine exit if the return addresses do not match. If the return addresses match, the processor pops the return addresses off of the legacy stack and off of the shadow stack. The stack out-of-bounds and the stack mismatch virtual machine exits may be handled by the hypervisor. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Michael LeMay, Barry E. Huntley
  • Patent number: 9424036
    Abstract: Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael K Gschwind, Valentina Salapura
  • Patent number: 9191198
    Abstract: In carrying out a task that consumes data from a one-time pad, task inputs comprising at least first data and second data from the pad, are combined together to form an output from which the data used from the pad cannot be recovered without knowledge of at least one of the first and second data. The task concerned can be, for example, the encrypting of a message or the creating of an attribute verifier.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: November 17, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Keith Alexander Harrison, Timothy Paul Spiller, William John Munro, Christopher Tofts
  • Patent number: 9189363
    Abstract: A system, method, and computer program product are provided for monitoring an execution flow of a function. In use, data associated with a function is identified within a call stack. Additionally, a call stack frame is determined from freed memory in the call stack. Further, an execution flow of the function is monitored, utilizing the call stack frame from the freed memory.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 17, 2015
    Inventor: Gregory William Dalcher
  • Patent number: 9063724
    Abstract: A method of executing an instruction set to select a set of registers, includes reading a first instruction of the instruction set; interpreting a first operand of the first instruction to represent a first register S to be selected; interpreting a second operand of the first instruction to represent a number N of registers to be selected; and selecting N consecutive registers starting at the first register S to form the set of registers.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 23, 2015
    Assignee: Cambridge Silicon Radio Limited
    Inventors: Peter Smith, David Richard Hargreaves
  • Publication number: 20150150024
    Abstract: A method of detecting stack overflows includes the following steps: storing in at least one dedicated register at least one data item chosen from: a data item (SPHaut) indicating a maximum permitted value for a stack pointer, and a data item (SPBas) indicating a minimum permitted value for said stack pointer; effecting a comparison between a current value (SP) or past value (SPMin, SPMax) of said stack pointer and said data item or each of said data items; and generating a stack overflow exception if said comparison indicates that said current or past value of said stack pointer is greater than said maximum permitted value or less than said minimum permitted value. A processor for implementing such a method is also provided.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Philippe GROSSI, Dominique DAVID, Francois BRUN
  • Patent number: 9015622
    Abstract: Some embodiments of a system and a method to tune a computing system based on a profile have been presented. A profile as used herein broadly refers to a file containing various parameters of a computing system, such as kernel parameters (e.g., buffer size, network setup, etc.), usable to configure the computing system. For instance, a set of profiles are stored in a computer-readable storage device in a computing system, such as a server, a personal computer, a laptop computer, etc. A processing device miming on the computing system may receive a user selection of one of the set of profiles. In response to the user selection, the processing device may load the selected profile onto the computing system in order to tune the computing system according to the selected profile.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: April 21, 2015
    Assignee: Red Hat, Inc.
    Inventors: Thomas K. Wörner, Christopher Haughey Snook
  • Patent number: 8966461
    Abstract: A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent invocation of a function. The compiler creates a width-specific executable version of the program code by determining a vector width of a target computer system and omitting the function from the width-specific executable if the vector width meets one or more criteria. For example, the compiler may omit the function call if the vector width is greater than a minimum size.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: February 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benedict R. Gaster, Lee W. Howes, Mark D. Hummel
  • Patent number: 8930677
    Abstract: A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object created by a method frame to a stack. The allocation is performed in response to: calling a first and second instruction in the method frame; the first instruction causes an escape of the object, and the second instruction cancels the escape of the object; the object does not escape to a thread other than a thread to which the object has escaped, at the point in time when the escape is cancelled; the first instruction has been called before the second instruction is called; and the object does not escape in accordance with an instruction other than the first instruction in the method frame, regardless of whether the object escapes in accordance with the first instruction.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Horii, Kiyokuni Kawachiya, Tamiya Onodera
  • Patent number: 8918622
    Abstract: A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object created by a method frame to a stack. The allocation is performed in response to: calling a first and second instruction in the method frame; the first instruction causes an escape of the object, and the second instruction cancels the escape of the object; the object does not escape to a thread other than a thread to which the object has escaped, at the point in time when the escape is cancelled; the first instruction has been called before the second instruction is called; and the object does not escape in accordance with an instruction other than the first instruction in the method frame, regardless of whether the object escapes in accordance with the first instruction.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Horii, Kiyokuni Kawachiya, Tamiya Onodera
  • Patent number: 8788796
    Abstract: A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing a plurality of floating-point registers, a decoding section for decoding operation instructions, and a floating-point operation section. The RISC processor may also include a control register for controlling status of floating-point registers, and for controlling the decoding section and the floating-point operation section, to thereby emulate a floating-point register stack using the floating-point register file. The decoding section may include a pointer register for maintaining a stack operation pointer, and for storing a value of the stack operation pointer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: July 22, 2014
    Assignee: Loongson Technology Corporation Limited
    Inventors: Wei Duan, Xiaoyu Li
  • Patent number: 8638805
    Abstract: Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules packets for transmission. The network processor generates tasks corresponding to each received packet associated with a data flow. A traffic manager receives tasks provided by one of the processing modules and determines a queue of the scheduling hierarchy corresponding to the task. The queue has a parent scheduler at each of one or more next levels of the scheduling hierarchy up to a root scheduler, forming a branch of the hierarchy. The traffic manager determines if the queue and one or more of the parent schedulers of the branch should be restructured. If so, the traffic manager drops subsequently received tasks for the branch, drains all tasks of the branch, and removes the corresponding nodes of the branch from the scheduling hierarchy.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 28, 2014
    Assignee: LSI Corporation
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Shailendra Aulakh, Allen Vestal
  • Patent number: 8627267
    Abstract: An apparatus and method for initializing system global variables by using a multiple load/store instruction is disclosed. The apparatus includes: a first storing unit for storing a system global variable initialization function and initialization functions using multiple load/store instruction; a second storing unit for storing a return address; a control unit for storing a first return address to the second storing unit when the system global variable initialization function is called for initializing the system global variable, initializing the system global variables by calling the initialization functions using multiple load/store instruction while performing the system global variable function and performing a rest of system global variable initialization function by finding and executing an execution sequence based on the first return address stored in the second storing unit; and a third storing unit for storing the system global variables initialized according to the control unit.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: January 7, 2014
    Assignee: Pantech Co., Ltd.
    Inventors: Jin-Woo Yang, Seung-Jun Yoon
  • Publication number: 20130145122
    Abstract: The present invention provides an instruction processing method of a network processor and a network processor. The method includes: when executes a pre-added combined function call instruction, adding an address of its next instruction to a stack top of a first stack; judging, according to the combined function call instruction, whether an enable flag of each additional feature is enabled, and if enabled, adding a function entry address corresponding to an additional feature to the stack top of the first stack; and after finishing judging all enable flags, popping a function entry address in the first stack, and executing a function corresponding to a popped function entry address until the address of the next instruction is popped. In the present invention, only one judgment jump instruction needs to be added to a main line procedure to implement function call of enabled additional features, which saves an instruction execution cycle.
    Type: Application
    Filed: February 11, 2013
    Publication date: June 6, 2013
    Applicant: Huawei Technologies Co., Ltd.
    Inventor: Huawei Technologies Co., Ltd.
  • Patent number: 8458441
    Abstract: The subject disclosure is directed towards technology by which an expression in a database engine is executed against stacks of data. Each instruction of the expression is evaluated against the data stacks until completed against each data stack, such as by iterating to execute an instruction through the data stacks before executing the next instruction. The data may be arranged in the data stacks (in memory) in various ways, such as to have each data stack contain the data of one database row, (e.g., with the data stack elements comprising column data. Data may be grouped, such as to put the data from different rows into the same data stack.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: June 4, 2013
    Assignee: Microsoft Corporation
    Inventors: Erik Ismert, Frank Huber
  • Patent number: 8429634
    Abstract: A semiconductor device has an arithmetic processing circuit provided with an arithmetic circuit and a control circuit and a memory circuit provided with a ROM and a RAM, where the arithmetic processing circuit and the memory circuit are connected to each other through an address bus and a data bus, a machine language program executed using the arithmetic processing circuit is stored in the ROM, the RAM has a plurality of banks, processing data obtained by executing the machine language program is divided into a plurality of stacks to be written to the plurality of banks, and the arithmetic processing circuit is operated in accordance with the machine language program so that, in the plurality of stacks stored in the plurality of banks, a stack of which data is not used until the machine language program is terminated is omitted and contiguous stacks are written to the same bank.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Dembo, Yoshiyuki Kurokawa, Masami Endo
  • Publication number: 20130061000
    Abstract: A computer-implemented method for creating a threaded package of computer executable instructions from software compiler generated code includes allocating, through a computer processor, the computer executable instructions into a plurality of stacks, differentiating between different types of computer executable instructions for each computer executable instruction allocated to each stack of the plurality of stacks, creating switch points for each stack of the plurality of stacks based upon the differentiating, and inserting the switch points within each stack of the plurality of stacks.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raul E. Silvera, Guansong Zhang, Yue Zhao
  • Publication number: 20120324206
    Abstract: A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object created by a method frame to a stack. The allocation is performed in response to: calling a first and second instruction in the method frame; the first instruction causes an escape of the object, and the second instruction cancels the escape of the object; the object does not escape to a thread other than a thread to which the object has escaped, at the point in time when the escape is cancelled; the first instruction has been called before the second instruction is called; and the object does not escape in accordance with an instruction other than the first instruction in the method frame, regardless of whether the object escapes in accordance with the first instruction.
    Type: Application
    Filed: August 24, 2012
    Publication date: December 20, 2012
    Applicant: International Business Machines Corporation
    Inventors: Hiroshi Horii, Kiyokuni Kawachiya, Tamiya Onodera
  • Publication number: 20120297167
    Abstract: A processor, method, and medium for implementing a call return stack within a pipelined processor. A stack head register is used to store a copy of the top entry of the call return stack, and the stack head register is accessed by the instruction fetch unit on each fetch cycle. If a fetched instruction is decoded as a return instruction, the speculatively read address from the static register is utilized as a target address to fetch subsequent instructions and the address at the second entry from the top of the call return stack is written to the stack head register.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Inventors: Manish K. Shah, Zeid H. Samoail
  • Patent number: 8234476
    Abstract: A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Rika Ono, Hitoshi Suzuki, Junichi Sato
  • Patent number: 8234516
    Abstract: The invention provides a topology collection method and dual control board device applicable to a stacking system comprising dual control board devices. A master control board of a dual control board device advertises through a stack port the topology information of the member device in which the master control board resides, including information about the master control board and, if a slave control board is present, information about the slave control board; and stores the topology information or updates the existing topology information upon receiving the topology information of the stacking system through the stack port, and backs up the stored topology information of the stacking system to the slave control board after the slave control board is inserted. This invention is applicable for collecting the topology information of a stacking system comprising distributed dual control board devices.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: July 31, 2012
    Assignee: Hangzhou H3C Technologies, Co., Ltd.
    Inventors: Yong Wang, Xiaolong Hu, Yiquan Yang
  • Publication number: 20120166766
    Abstract: Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In one embodiment, the stacks are invisible to software. In an embodiment, a microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit are generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation. Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: December 24, 2010
    Publication date: June 28, 2012
    Inventors: Jonathan D. Combs, Kameswar Subramaniam
  • Patent number: 8195885
    Abstract: In an electronic unit having a stack in memory and adapted to run a plurality of tasks in accordance with a multitask operating system and to save context data in the stack, a scheduling unit schedules the plurality of tasks for wakeup so as to execute the plurality of tasks. Each of the plurality of tasks stays in at least one of a suspended state, a ready state, and a running state. A measurement unit measures an amount of space to be used in the stack during the at least one of the tasks staying in neither the running state nor the ready state.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: June 5, 2012
    Assignee: Denso Corporation
    Inventors: Takahiko Mori, Daisuke Tokumochi
  • Patent number: 8179540
    Abstract: An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming apparatus. A log corresponding to the usage of the service is set in job log information with a synchronization flag set off. The log in the job log information, for which the synchronization flag is set off, is set on. The counter information and the job log information are output after the synchronization flag for the log having the synchronization flag set off has been set on.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 15, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Junichi Hiruma, Nobuyuki Tonegawa
  • Publication number: 20110314259
    Abstract: A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kattamuri Ekanadham, Brian R. Konigsburg, David S. Levitan, Jose E. Moreira, David Mui, IL Park
  • Publication number: 20110289298
    Abstract: A semiconductor circuit includes a memory which stores data; a processing device which executes a program, writes argument data of a function of the program into the memory referring to an address stored in a stack pointer, when a value of a program counter, which indicates an address of the program under execution, reaches a hardware accelerator starting address, and outputs the address stored in the stack pointer; and a hardware accelerator which receives the address of the stack pointer from the processing device, when a value of the program counter of the processing device reaches the hardware accelerator starting address, reads the argument data of the function from the memory referring to the address stored in the stack pointer, and executes the function implemented in hardware using the argument data.
    Type: Application
    Filed: February 16, 2011
    Publication date: November 24, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masayuki TSUJI
  • Publication number: 20110271080
    Abstract: A target computing system 10 is adapted to support a register window architecture, particularly for use when converting non-native subject code 17 instead into target code 21 executed by a target processor 13. A subject register stack data structure (an “SR stack”) 400 in memory has a plurality of frames 410 each containing a set of entries 401 corresponding to a subset of subject registers 502 of one register window 510 in a subject processor 3. The SR stack 400 is accessed by the target code 21 executing on the target processor 13. The SR stack 400 stores a large plurality of such frames 410 and thereby avoids overhead such as modelling automatic spill and fill operations from the windowed register file of the subject architecture. In one embodiment, a target computing system 10 having sixteen general purpose working registers is adapted to support a register window architecture reliant upon a register file containing tens or hundreds of subject registers 502.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Alexander B. Brown
  • Publication number: 20110271081
    Abstract: A multimedia platform is discussed, which includes a first stacking unit including a first substrate and a multimedia processor, wherein the first substrate and the multimedia processor are stacked on the first stacking unit, a pattern and a via hole are formed on the first substrate, and the multimedia processor is mounted on top of the first substrate; a second stacking unit including a second substrate and a plurality of storage devices, wherein the second substrate and the plurality of storage devices are stacked on the second stacking unit, a pattern and a via hole being formed on the second substrate, and the plurality of storage devices are mounted on top of the second substrate; and at least one solder ball arranged on the first stacking unit, the at least one solder ball allowing the first substrate to be coupled to the second substrate.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 3, 2011
    Inventors: You-Hoan Jung, Jong-Sik Jeong
  • Publication number: 20110246748
    Abstract: Illustrated is a system and method that includes a processor and service processor co-located on a common socket, the service processor to aggregate data from a distributed network of additional service processors and processors both of which are co-located on an additional common socket. The system and method also includes a first sensor to record the data from the processor. The system and method also includes a second sensor to record the data from a software stack. The system and method further includes a registry to store the data.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Inventors: Vanish Talwar, Jeffrey R. Hilland, Vidhya Kannan, Sandeep KS, Prashanth V
  • Patent number: 7979685
    Abstract: A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instruction execution modes having an instruction set comprising multiple instruction implementations. At least one of the multiple instruction implementations is configured to change the processor from a first instruction execution mode to a second instruction execution mode. The processor comprises an instruction fetcher configured to fetch an instruction from one of the multiple instruction streams based at least in part upon a current instruction execution mode.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 12, 2011
    Assignee: Oracle America, Inc.
    Inventors: Eduard K. de Jong, Jurjen N.E. Bos
  • Patent number: 7975127
    Abstract: A computer system comprising a data file having entries each of which is designed to hold data, an advanced and a completed mapping file each having entries each of which is designed to hold a data-file-entry address, an operation window that is a buffer to hold substances of operations waiting execution, and a state-modification queue that is designed to be able to hold a substance of a modification on the advanced mapping file for each clock cycle; wherein making a modification on the advanced mapping file, entering the substance of this modification into the state-modification queue, and entering substances of operations into the operation window are each to be done in one clock cycle, and operations held in the operation window are to be executed out of order. The system can attain high performance easily and utilize programs described in any machine language for traditional register-based/stack-based processors.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: July 5, 2011
    Inventor: Hajime Seki
  • Publication number: 20110119508
    Abstract: A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 19, 2011
    Applicant: International Business Machines Corporation
    Inventor: Thomas J. Heller, JR.