Abstract: A target computing system 10 is adapted to support a register window architecture, particularly for use when converting non-native subject code 17 instead into target code 21 executed by a target processor 13. A subject register stack data structure (an “SR stack”) 400 in memory has a plurality of frames 410 each containing a set of entries 401 corresponding to a subset of subject registers 502 of one register window 510 in a subject processor 3. The SR stack 400 is accessed by the target code 21 executing on the target processor 13. The SR stack 400 stores a large plurality of such frames 410 and thereby avoids overhead such as modelling automatic spill and fill operations from the windowed register file of the subject architecture. In one embodiment, a target computing system 10 having sixteen general purpose working registers is adapted to support a register window architecture reliant upon a register file containing tens or hundreds of subject registers 502.

Abstract: A multimedia platform is discussed, which includes a first stacking unit including a first substrate and a multimedia processor, wherein the first substrate and the multimedia processor are stacked on the first stacking unit, a pattern and a via hole are formed on the first substrate, and the multimedia processor is mounted on top of the first substrate; a second stacking unit including a second substrate and a plurality of storage devices, wherein the second substrate and the plurality of storage devices are stacked on the second stacking unit, a pattern and a via hole being formed on the second substrate, and the plurality of storage devices are mounted on top of the second substrate; and at least one solder ball arranged on the first stacking unit, the at least one solder ball allowing the first substrate to be coupled to the second substrate.

Abstract: Illustrated is a system and method that includes a processor and service processor co-located on a common socket, the service processor to aggregate data from a distributed network of additional service processors and processors both of which are co-located on an additional common socket. The system and method also includes a first sensor to record the data from the processor. The system and method also includes a second sensor to record the data from a software stack. The system and method further includes a registry to store the data.

Abstract: A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instruction execution modes having an instruction set comprising multiple instruction implementations. At least one of the multiple instruction implementations is configured to change the processor from a first instruction execution mode to a second instruction execution mode. The processor comprises an instruction fetcher configured to fetch an instruction from one of the multiple instruction streams based at least in part upon a current instruction execution mode.

Abstract: A computer system comprising a data file having entries each of which is designed to hold data, an advanced and a completed mapping file each having entries each of which is designed to hold a data-file-entry address, an operation window that is a buffer to hold substances of operations waiting execution, and a state-modification queue that is designed to be able to hold a substance of a modification on the advanced mapping file for each clock cycle; wherein making a modification on the advanced mapping file, entering the substance of this modification into the state-modification queue, and entering substances of operations into the operation window are each to be done in one clock cycle, and operations held in the operation window are to be executed out of order. The system can attain high performance easily and utilize programs described in any machine language for traditional register-based/stack-based processors.

Abstract: A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack.

Abstract: A post-silicon validation technique is able to craft randomized executable code, with known final outcomes, as a verification test that is executable on a hardware, such as a prototype microprocessor. A verification device is able to generate the test, in the form of programs, in such a way that at the end of the execution, the initial state of the test hardware is restored. Therefore, the final state of such a reversible program is known a priori. The technique may use a program generation algorithm, agnostic to any particular instruction set on the test hardware. In some examples, that algorithm is executed on the test hardware to generate the verification test, which is then executed on that test hardware. In other examples, the verification test is generated on another processor coupled to the test hardware. In either case, the verification test may contain initial and inverse operations determined from the test hardware.

Abstract: Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving high performance. In another aspect, new synchronization primitives FetchAndIncrementBounded (Counter, Bound) and FetchAndDecrementBounded (Counter, Bound) are implemented. These primitives can be implemented in hardware and thus promise a very fast throughput for queues, stacks and double-ended queues.

Abstract: A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.

Abstract: A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.

Abstract: Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Abstract: Systems and methods for storing stack data for multi-threaded processing in a specialized cache reduce on-chip memory requirements while maintaining low access latency. An on-chip stack cache is used store a predetermined number of stack entries for a thread. When additional entries are needed for the thread, entries stored in the stack cache are spilled, i.e., moved, to remote memory. As entries are popped off the on-chip stack cache, spilled entries are restored from the remote memory. The spilling and restoring processes may be performed while the on-chip stack cache is accessed. Therefore, a large stack size is supported using a smaller amount of die area than that needed to store the entire large stack on-chip. The large stack may be accessed without incurring the latency of reading and writing to remote memory since the stack cache is preemptively spilled and restored.

Abstract: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

Abstract: A microprocessor includes an instruction set architecture, comprising a call instruction type, a return instruction type, and other instruction types. Execution units correctly execute program instructions of the other instruction types. A call/return stack has a plurality of entries arranged in a last-in-first-out manner. The call/return stack is architectural state of the microprocessor not modifiable by program instructions of the other instruction types. The call/return stack is architectural state of the microprocessor indirectly modifiable by program instructions of the call and return instruction types. The microprocessor also includes a fetch unit that fetches program instructions and sends the program instructions of the other instruction types to the execution units to be correctly executed.

Abstract: A method and apparatus are provided for operating a processor. The method comprising the steps of providing a single call stack for execution of a plurality of tasks that operate on the processor, parallelly operating the plurality of tasks and allowing a context switch from a first task to a second task of the plurality of tasks, but only when operation of the first task is blocked.

Abstract: A stack pointer is copied to a stack pointer base to debug stack underflow. A move instruction, used to initialize the stack pointer, is modified to additionally copy the stack pointer to a stack pointer base register. During a course of execution in a single context, the stack pointer base sticks to the initial base value while the stack pointer is altered by a succession of PUSH and POP instructions. By monitoring for equivalence in the stack pointer and the stack pointer base values, a balanced number of PUSH and POP instructions is detected. If an equal number of PUSH and POP instructions is detected and an additional POP instruction is programmed, a stack underflow condition exists, an exception condition signaled, and exception flag produced. The exception condition allows the stack to be protected from an excessive POP instruction retrieving data out of context and subsequent loss of stack data.

Abstract: A runtime execution environment may manage resources executing cooperative threading on a single physical thread. One example can scan eligible activation records linked to threads on a method process and can execute one of the activation records. This example can create a new activation record for a new method invoked for the executed activation record and link the new activation record to the executed activation record. Further, this example can loop back to re-start the method.

Abstract: Approaches that allow the context of an SMI task to be saved between SMIs. Upon entering an SMI handler for a task, a new task context stack is created. Thereafter, the SMI handler uses the task context, leaving the original stack unchanged. When the time limit for a single SMI is almost reached, the CPU is directed back to the original stack, and the task context stack persists in memory and retains the context of the task in hand. The soft SMI exits with an indication to signify that a new SMI should be invoked to continue processing. The entity that caused the first soft SMI then invokes another, passing in an indication to signify that this is a continuation of the prior task. On entering the SMI handler, the handler notes the request for continuation, switches to the saved task context stack and continues processing where it left off.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

Abstract: A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack dependent operation is determined. A stack pointer delta is then modified based upon the number of bytes associated with the stack dependent operation. A current location in the stack is determined based on the stack pointer and the stack pointer delta.

Abstract: The invention provides a method and apparatus for eliminating the stack overflow and underflow in a dual stack computer 100 while remaining fully operational in case of single event upset caused by radiation and a method and apparatus for eliminating stack overflow and underflow by replacing a conventional stack with a circular stack array 125B coupled to a plurality of multiplexers 205a-h to function in a circular repeating pattern. The method of the invention provides for the stack to remain operational in the event of single event upset by using one hot logic multiplexers 205a-h. Thus in case of single event upset, where the logic state of the control signals can be corrupted such that at a given time both the push or pop control signals are active, the multiplexers will not shift the data either upward or downward in the data stack 145 and the return stack 120 and prevents the processor system 100 from entering into an unknown state.

Abstract: A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.

Abstract: Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

Abstract: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline.

Abstract: A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.

Abstract: Systems and methods are described for managing applications in a computer system. An operating system kernel such as Linux can be started and executed at different addresses other than the address typically used for such kernels. An operating system kernel can accommodate end of memory and size of memory that do not comply with normal system specifications. Mechanisms are described that change methods for exception vector handling using a software fix. Dual and/or multi-core systems can run applications in both SMP and ASMP modes without needing any hardware changes. Separate instances or similar copies of an OS such as Linux can be executed on multiple cores in ASMP mode. In SMP mode, Linux or another OS can run as a single instance of the OS.

Abstract: An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algorithm allows uninterrupted concurrent access to both ends of the deque, while returning appropriate exceptions in the boundary cases when the deque is empty or full. An interesting characteristic of the concurrent deque implementation is that a processor can detect these boundary cases, e.g., determine whether the array is empty or full, without checking the relative locations of the two end pointers in an atomic operation.

Abstract: There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and 3) at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.

Abstract: A barrier with local spinning. The barrier is described as a barrier object having a bit vector embedded as a pointer. If the vector bit is zero, the object functions as a counter; if the vector bit is one, the object operates as a pointer to a stack. The object includes the total number of threads required to rendezvous at the barrier to trigger release of the threads. The object points to a stack block list that describes each thread that has arrived at the barrier. Arriving at the barrier involves reading the top stack block, pushing onto the list a stack block for the thread that just arrived, decrementing the thread count, and spinning on corresponding local memory locations or timing out and blocking. When the last thread arrives at the barrier, the barrier is reset and all threads at the barrier are awakened for the start of the next process.

Abstract: A method and system for managing global queues is provided. In one example, a method for implementing a global queue is provided. The queue has a head pointer, a tail pointer, and zero or more elements. The method comprises one or more functions for managing the queue, such as an “add to end” function, an “add to front” function, an “empty queue” function, a “remove from front” function, a “remove specific” function and/or a “lock queue” function. In some examples, the method enables an element to be added to the queue even when the queue is in a locked state.

Abstract: The information processing apparatus includes: a process unit having one or more registers that retain data used for calculation; a compression unit that compresses and saves the content in the register to a stack memory; and a decompression unit that decompresses and restores the data saved in the stack memory, to the corresponding registers. If a first decoding unit included in the process unit has decoded a call instruction which is assigned a compression control bit, the compression unit, in executing the call instruction, performs compression before saving the content of the registers to the stack memory. If a second decoding unit included in the process unit has decoded a return instruction which is assigned a decompression control bit, the decompression unit, in executing the return instruction, performs decompression before restoring the content saved in the stack memory to the registers.

Abstract: Executing an instruction on an operand stack, including performing a stack-state aware translation of the instruction to threaded code to determine an operand stack state for the instruction, dispatching the instruction according to the operand stack state for the instruction, and executing the instruction.

Abstract: A virtual machine in a processing system manages type information for operands. In one embodiment, the virtual machine accomplishes the following results through execution of a single instruction: adding an operand tag to a tag stack, and updating a stack pointer for the tag stack to recognize the addition of the operand tag to the tag stack. The single instruction may be a shift instruction, for example. The tag stack may reside in a tag stack register, and each operand tag may indicate whether a corresponding operand on an operand stack is to be treated as a reference operand or a non-reference operand. Other embodiments are described and claimed.

Abstract: An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or FCALL, a stack memory is filled, while the stack is emptied in the case of the presence of a re-jump instruction. At every re-jump, a predetermined amount of re-jump information is taken from stack and supplied to a means for decoding, which is formed to access the stack again in the case where the predetermined amount of re-jump information indicates a change of the physical memory window, to finally supply the correct address for the next instruction in the instruction sequence to the means for reading in.

Abstract: Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each element in the pre-fix expression is then parsed. For each first operand for a Boolean operation, the value of the operand is determined. This may include evaluating a GUID. When an operator and a second operand are encountered, a decision is made as to whether the second operand should be evaluated. The determination as to whether the second operand should be evaluated is made based upon the value of the first operand and the type of operator. If the second operand need not be evaluated, no evaluation is performed thereby saving time and memory space. The evaluation of the Boolean expression continues in this manner until the entire expression has been evaluated. If the Boolean expression is evaluated as true, the program module associated with the Boolean expression may be loaded.

Abstract: A technique for detecting corruption associated with a stack in a storage device is disclosed. In one embodiment, the technique is realized by having a processing device insert a quantity of information adjacent to the stack in the storage device, wherein the quantity of information has an initial state. The processing device then inspects the quantity of information so as to identify any deviation from the initial state and thereby detect corruption associated with the stack in the storage device.

Abstract: The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managing a pointer that points to a current top-of-stack register. As data is pushed or popped from the stack, the top-of-stack point is incremented or decremented accordingly.

Abstract: The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which contains, the remainder of the stack. Some embodiments utilize a variable buffer that is configured to buffer transfers between the processor registers and the memory. The actual amount of data stored in the variable buffer is configured to be flexible, so that transfers between the variable buffer and processor registers are managed to keep the processor registers filled with active stack data (assuming that stack data exists). However, transfers between the variable buffer and memory may be configured to occur only when the variable buffer exceeds certain fill capacities.

Abstract: A technique to dynamically enable or disable a number of stacks within a processor based on demand. At least one embodiment includes logic to detect whether a stack is needed and to enable the stack in response thereto and to disable the stack if it no longer needed.

Abstract: A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor architecture, wherein the translated first block of instructions operate with a stack of data entry positions. During the translation, an expected Top of Stack (TOS) position in the stack for the first block of code is generated.

Abstract: An operand stack (10) permits optimization of memory space and a continuous check of operand type by creating a type memory (20) which stores type information for each operand, said information comprising information about the length of the operand. This length information available for each single operand permits the operands to be stored extremely densely, while the prior art uses uniform length stack elements for each operand, their length depending on the longest operand.

Abstract: Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers, setting a program counter to an address corresponding to code of the particular one of the schedulers, and the processor executing code at an address corresponding to the program counter. Also included may be setting a stack pointer to an address corresponding to stack space for the particular one of the schedulers and the processor using the stack space at the stack pointer after executing code at the address corresponding to the program counter. The system described herein provides a small kernel that can run on a variety of hardware platforms, such as a PowerPC based Symmetrix adapter board used in a Symmetrix data storage device provided by EMC Corporation of Hopkinton, Ma. The core kernel code may be written for the general target platform, such as the PowerPC architecture.

Abstract: One embodiment of the present invention provides a system that facilitates code verification and garbage collection in a platform-independent virtual machine. The system operates by first receiving a code module written in a platform-independent language. Next, the system examines the code module to locate calls to program methods within the code module. The system then transforms the code module so that all operands remaining on the evaluation stack only relate to the called method when the method is called, thereby simplifying verification and garbage collection of the code module.

Abstract: A given software process is composed on one or more threads of execution. Each thread possesses its own stack, a region of memory set aside by the operating system for that thread to store data. Popular programming languages rely heavily on stack-based data (frequently referred to as “local” or “automatic” data). It is a characteristic of deterministic machines like computers that, given the same problem to process with the same data, the same results, both intermediate and final, will result. This even extends to the sequence the software running on the computer will take to process the problem or data. This in turn means that for each thread making up the program, the data layout in the thread's stack will be relatively consistent each time the program gets to a similar point in the processing of the problem and/or data. This represents a potential “point of repeatability” that a hacker can take advantage of.

Abstract: The present invention provides a microprocessor which enables task switching with a small time overhead. Upon reception of input of an interrupt control signal during execution of a task-1, a first program counter is switched to a second program counter and a first register file is switched to a second register file to start execution of a task-2. During the execution of the task-2, a task switch controller controls switches to select the first program counter, first memory devices of a processing pipeline circuit, and the first register file to save data stored in them in a save memory. After the data saving, data on a task-3 saved in the save memory is restored in the first program counter, the first memory devices of the processing pipeline circuit, and the first register file.

Abstract: A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data stored into the cache. When a pop instruction is encountered, the apparatus uses the row and way values at the top of the stack to access the cache. In one embodiment, an offset of the most recent push data within the current cache line specified by the top row and way values is maintained. The offset is updated on each push or pop. If a pop overflows the offset, the top entry of the stack is popped. If a push underflows the offset, the row and way values are pushed onto the stack. The row, way, and offset values are subsequently compared with the actual pop address to determine whether incorrect data was provided.

Abstract: In a data processing apparatus 2 having a first mode of operation in which JAVA® bytecodes 46, 48 specify the processing operations and a second mode of operation in which other instructions specify the processing operations. In order to speed operation, the JAVA® Local Variable 0, or another such variable, is stored within a register of a register bank 14 to be available for rapid access. This storage is in a write-through manner such that reads of the value will be directly serviced from the register R4 and writes to the data value will be made in both the register R4 and back in the original memory location for that data value as determined by the JAVA® Virtual Machine.

Abstract: A programmable unit includes a command execution unit for carrying out commands, a memory device for storing data required for command execution and data emitted from the command execution unit, and a buffer-storage device for buffer storing the data emitted from the command execution unit. The command execution unit writes to the buffer-storage device data to be transferred to the memory device. The data written to the buffer storage device is transferred to the memory device at a later time. The programmable unit is distinguished by forming the buffer-storage device as a stack, and/or by providing a control apparatus that, when required, causes data stored in the buffer-storage device to be moved temporarily to another memory device. Such a programmable unit can carry out any buffer storage of events that may possibly be required quickly and easily in all circumstances.

Abstract: A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Abstract: According to one aspect of the invention, there is provided a method for renaming memory references to stack locations in a computer processing system. The method includes the steps of detecting stack references that use architecturally defined stack access methods, and replacing the stack references with references to processor-internal registers. The architecturally defined stack access methods include memory accesses that use one of a stack pointer, a frame pointer, and an argument pointer. Moreover, the architecturally defined stack access methods include push, pop, and other stack manipulation operations.