Architecture Based Instruction Processing Patents (Class 712/200)
  • Patent number: 10915709
    Abstract: A method for controlling a system using natural language comprises a step of providing a plurality of string programme code components within the system. A string programme code component each comprises a definition string comprising an expression in natural language, and a programme code segment unambiguously assigned to the definition string which implements a functionality assigned to the expression in natural language. At least one of the string programme code components from the plurality of string programme code components further comprises a process for parameter input, wherein this string programme code component is configured to support a parameter input by means of which the functionality provided by the programme code segment of this string programme code component may be specified.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: February 9, 2021
    Inventor: Masoud Amri
  • Patent number: 10917677
    Abstract: A distributed computing system is configured to compute operational data for a video advertisement delivery system. Cloud-based resource are used to calculate operational parameters such as geographical data, unique advertisement delivery instances and segments of consumers that received the video advertisements.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: February 9, 2021
    Assignee: Verizon Media Inc.
    Inventors: Giao Huu Phan, Daniel Wei-Tze Hsiung, Ian Graeme Melven, Brian Hardie, Joseph Gutierrez, Marshall Allen Beddoe, Pankaj Gupta, Bernardo de Seabra, Dru Nelson, Kam Ho Kenneth Cheung, Jason Endo, Max Sadrieh, Rahul Ravindran, Vikas Unnava, Sharon Paisner, Dia Kharrat
  • Patent number: 10915305
    Abstract: A method for controlling a compile a software application. The method includes at least one computer processor generating, from source code corresponding to a software application, a plurality of pre-optimization intermediate representations (IRs) of functions associated with the software application. The method further includes generating a plurality of post-optimization IRs of the functions associated with the software application by executing one or more optimization routines on the plurality of pre-optimization IRs of functions. The method further includes determining a set of IRs of functions, from the plurality of generated pre-optimization IRs of the functions associated with the software application and the generated plurality of post-optimization IRs of the functions associated with the software application. The method further includes converting a determined set of IRs of functions to an executable version of the software application.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yuheng Zhang, Jiu Fu Guo, Kang Zhang, Si Yuan Zhang
  • Patent number: 10901735
    Abstract: An apparatus includes a memory, a memory controller, arithmetic processors, and access circuits corresponding to the arithmetic processors. The memory controller controls a load instruction that reads, from the memory, data to be obtained by the arithmetic processors. The access circuit generates divided instructions by dividing a multicast load instruction, and selects, for each divided instruction, a first access circuit that issues, to the memory controller, a read request for causing the target access circuits to perform responses to the target access arithmetic processors. The first access circuit determines first identification information common to all the target access circuits, and issues, to the memory controller, a single read request to which the first identification information is added, and obtains, from the memory controller, responses to which the first identification information is added, and outputs first data based on the obtained responses to the target arithmetic processors.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 26, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Tomohiro Nagano
  • Patent number: 10896131
    Abstract: Systems and methods for predicting the next host source of a command directed to a storage device, and configuring the storage device with the host memory configuration parameters of that predicted host, are disclosed. A predictive model may be used to identify which of a plurality of different actual or virtual hosts will be sending a next command based on a pattern of prior host origins of commands. The storage device may include a plurality of different memory configuration parameters associated with each different host source and may update the current memory configuration based on the predicted next host origin prior to actual receipt of a next command.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alex Bazarsky, Ariel Navon, Shay Benisty
  • Patent number: 10871967
    Abstract: Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 22, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Patent number: 10872030
    Abstract: A method includes invoking a first instruction that, when executed by a first processor, causes the first processor to perform a first operation, and that, when executed by the first processor, causes a second processor to perform a second operation. The method further includes a second instruction that, when executed by the first processor, causes the first processor to perform the first operation while causing the second processor to perform a third operation or while leaving the second processor unaffected. A control system includes a first processor and a second processor, wherein the first processor is configured to execute a first instruction to perform a first operation, wherein the second processor is configured to perform a second operation when the first processor executes the first instruction.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies AG
    Inventor: Albrecht Mayer
  • Patent number: 10866842
    Abstract: Exploiting FPGAs for acceleration may be performed by transforming concurrent programs. One example mode of operation may provide one or more of creating synchronous hardware accelerators from concurrent asynchronous programs at software level, by obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels, mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter, producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices, performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming, and creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 15, 2020
    Assignee: RECONFIGURE.io LIMITED
    Inventors: Mahdi Jelodari Mamaghani, Robert James Taylor
  • Patent number: 10832191
    Abstract: A system, method, and computer program product are provided for metadata driven interface orchestration and mapping. In operation, a system defines a plurality of job items in a master enterprise catalogue by mapping all possible business requests to one or more pre-defined job items. The system defines job specifications in the master enterprise catalogue by mapping the plurality of job items to one or more pre-defined job specifications. Further, the system defines a job list in the master enterprise catalogue by building a sequence of outgoing requests based on possible use cases and the job specifications. The system defines an order context associated with one or more orders. Additionally, the system automatically generates a job plan including a plurality of activities utilizing the job list from the master enterprise catalogue and the order context. Moreover, the system automatically generates interfaces with a plurality of external systems based on the job plan including the plurality of activities.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: November 10, 2020
    Assignee: AMDOCS DEVELOPMENT LIMITED
    Inventors: Rani Tzur, Daniel Tal, Abhishek Anant Patankar, Jayant K. Sahu, Prashantkumar Kashinath Sonawane
  • Patent number: 10802844
    Abstract: An architectural software model in which browser-executable code and non-browser executable code of an application are distributed. The browser-executable code (such as markup language and script) is executed by a browser on perhaps a client machine, whilst the non-browser executable code (such as C# code as an example) is executed on a server or by a service. Such code typically is included within a single desktop application with an interoperability component operating between. The browser-executable code is able to communicate with the non-browser executable code using a request-response protocol. In order to facilitate communication with the non-browser-executable code, the non-browser executable code is provided in an environment that includes a request translator and a response translator. The environment includes an interface which honors the request/response protocol followed by the browser-executable code.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 13, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Andrew Michael Pennell, Irina Koulinitch, Olivier Colle, Mariyan D. Fransazov
  • Patent number: 10802829
    Abstract: Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, tracking a specific dependency on each of a threshold number of instructions most recently added to the issue queue prior to the instruction, tracking as a single group a dependency of the instruction on any instructions in the issue queue that are not in the threshold number of instructions, and tracking for each source register used by the instruction an indicator of whether its content is dependent on results from an instruction in the single group that has not finished execution. Based at least in part on detecting removal from the issue queue of an instruction in the single group that has issued and not finished execution, the method includes indicating that the instruction is ready for issuance or waiting for a notification that the removed instruction has finished execution.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel A. Silberman, Balaram Sinharoy
  • Patent number: 10795888
    Abstract: A database engine receives a database query from a client. The database engine parses the database query to build a query operator tree that includes a plurality of query operators. The database engine performs one or more optimization passes on the query operator tree, including a deduplication optimization pass, to form an optimized execution plan. The deduplication optimization pass includes: creating a list of query operators via a first traversal of the query operator tree, determining a first query operator that is equivalent to a second query operator, based on a hash map, via a second traversal of the query operator tree, and substituting, via a third traversal of the query operator tree, the second query operator with a tree node that links to the first query operator. The database engine executes the optimized execution plan to retrieve a result set from the database, and returns the result set.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Tableau Software, Inc.
    Inventors: Adrian Vogelsgesang, Michael Haubenschild, Richard L. Cole, Jan Finis, Manuel Then, Tobias Muehlbauer, Thomas Neumann
  • Patent number: 10733199
    Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus M. Helms, Christian Jacobi, Aditya N. Puranik, Parminder Singh
  • Patent number: 10713088
    Abstract: Methods, systems, and computer-readable media for event-driven scheduling using directed acyclic graphs are disclosed. A directed acyclic graph is generated that comprises a plurality of nodes and a plurality of edges. The nodes represent jobs, and the edges represent dependency relationships between individual jobs. Based (at least in part) on one or more events, a job scheduler determines that one of the nodes represents a runnable job. One or more of the dependency relationships for the runnable job are satisfied by the one or more events. An execution schedule is determined for the runnable job. Based (at least in part) on the execution schedule, execution of the runnable job is initiated using one or more computing resources.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Chetan Hosmani, Dougal Stuart Ballantyne
  • Patent number: 10691534
    Abstract: A data encoding method, a data decoding method, and a storage controller are provided. The encoding method includes: obtaining a verification data corresponding to a raw data according to a write command; adding the verification data to the raw data, and obtaining a scrambled data accordingly; and performing an encoding operation on the scrambled data to obtain a codeword data. The decoding method includes: performing a decoding operation on a codeword data to obtain a decoded codeword data, and obtaining a pre-scrambling data accordingly; identifying a verification data and a raw data in the pre-scrambling data; identifying one or more first system data corresponding to the raw data according to a read command; and determining whether the raw data is correct by comparing the one or more first system data and the verification data.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 23, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Hsiu-Hsien Chu, Heng-Lin Yen
  • Patent number: 10642617
    Abstract: A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 5, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks, Douglas R. Reed
  • Patent number: 10642615
    Abstract: A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction outcome, a branch classification unit associated with the processor pipeline and the branch prediction unit. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: a simple branch or a hard-to-predict (HTP) branch, wherein a threshold used for the classification is dynamically adjusted based on a workload of the processor.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Puneeth A. H. Bhat, Satish Kumar Sadasivam, Shruti Saxena
  • Patent number: 10635472
    Abstract: In one approach, an import mechanism allows new hardware intrinsics to be utilized by writing or updating a library of source code, rather than specifically modifying the virtual machine for each new intrinsic. Thus, once the architecture is in place to allow the import mechanism to function, the virtual machine itself (e.g. the code which implements the virtual machine) no longer needs to be modified in order to allow new intrinsics to be utilized by end user programmers. Since source code is typically more convenient to write than the language used to implement the virtual machine and the risk of miscoding the virtual machine is minimized when introducing new intrinsics, the import mechanism described herein increases the efficiency at which new hardware intrinsics can be introduced.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 28, 2020
    Assignee: Oracle International Corporation
    Inventors: John R. Rose, Vladimir Ivanov
  • Patent number: 10591983
    Abstract: A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access processor is designed to allow lower energy memory accesses than can be obtained by the main processor in providing data to the hardware accelerator while providing the hardware accelerator with a sufficiently high bandwidth memory channel. In some embodiments, the main processor may enter a sleep state during accelerator calculations to substantially lower energy consumption.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 17, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Chen-Han Ho, Karthikeyan Sankaralingam, Sung Kim
  • Patent number: 10574521
    Abstract: Methods and systems for configuring a local switch and a remote switch configured as peers. The method includes: receiving a configuration for configuring the local switch and the remote switch; checking if resources are available for the configuration on the local switch; when resources are available on the local switch, reserving those resources; checking if resources are available for the configuration of the remote switch; when resources are available on the remote switch, reserving those resources; and applying the configuration to the local switch and the remote switch when resources are available on the local switch and the remote switch.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 25, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Pankaj Kumar Rai, Shrawan Chittoor Surender, Srinivas Pitta, Siddartha Gundeti, Narayanaswami Ganapathy
  • Patent number: 10572376
    Abstract: An integrated circuit includes a memory interface, coupled to a memory to store data corresponding to instructions, and an operations queue to buffer memory operations corresponding to the instructions. The integrated circuit may include acceleration hardware to execute a sub-program corresponding to the instructions. A set of input queues may include an address queue to receive, from the acceleration hardware, an address of the memory associated with a second memory operation of the memory operations, and a dependency queue to receive, from the acceleration hardware, a dependency token associated with the address. The dependency token indicates a dependency on data generated by a first memory operation of the memory operations. A scheduler circuit may schedule issuance of the second memory operation to the memory in response to the dependency queue receiving the dependency token and the address queue receiving the address.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Kermin Elliott Fleming, Jr., Simon C. Steely, Jr., Kent D. Glossop
  • Patent number: 10552121
    Abstract: An exemplary process management server disclosed herein comprises a machine-learning model that may be trained to expose processes from a message stream in response to a training table. In one embodiment, one or more performance metrics of the exposed processes may be monitored to identify a process anomaly or other change in process performance, and to dynamically modify one or more process components in response thereto. Such an arrangement improves system performance, efficiency and resource utilization. For example, system performance may be improved by re-ordering process steps to minimize resource overlap. Efficiency and resource utilization may be improved by re-ordering process steps to maximize parallel processing and reduce lag times and bottlenecks.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 4, 2020
    Assignee: Capital One Services, LLC
    Inventors: Jayaraman Ganeshmani, Kissoon John Ramotar
  • Patent number: 10534615
    Abstract: A data processing system includes a processor operable to execute a program partitioned into a number of discrete instructions, the processor having multiple processing elements each capable of executing more than one instruction per cycle, and an interface configured to read a first program and, on detecting a branch operation by that program creating m number of branches each having a different sequence of instructions, combine an instruction from one of the branches with an instruction from at least one of the other branches so as to cause a processing element to execute the combined instructions during a single cycle.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: January 14, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Jung-Wook Park
  • Patent number: 10509683
    Abstract: Simulation of a computational job using various sets of resources, and potentially also the automated or semi-automated allocation of an appropriate set of resources for accomplishing a computational job comprising multiple vertices. For each of multiple potential sets of resources, a simulation module simulates processing of the computational job. While the simulation does not actually perform the vertex on each processing node, the simulation does use dependencies between vertices, and historical data regarding the processing of instances of such vertices, in order to determine the efficacy of processing of each vertex, and to put the estimations together into an overall simulation result.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: December 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Furman, Yifung Lin, Deyang Song
  • Patent number: 10503513
    Abstract: A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well as a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: December 10, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: David Conrad Tannenbaum, Srinivasan (Vasu) Iyer, Stuart F. Oberman, Ming Y. Siu, Michael Alan Fetterman, John Matthew Burgess, Shirish Gadre
  • Patent number: 10496823
    Abstract: Technologies for protecting systems and data of an organization from malware include a data integrity server configured to receive a data file for import from an external source. The data integrity server analyzes the received data file with multiple anti-malware engines to determine whether the data file includes hidden malware. The data integrity server discards the data file in response to a determination that the data file includes hidden malware. Additionally, the data integrity server verifies the type of the received data file based on the file extension associated with the received data file. The data integrity server cleans the received data file in response to verification of the file type. The cleaned data file is transmitted to a computing device to be imported. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 3, 2019
    Assignee: Operation and Data Integrity Ltd.
    Inventors: Oren Eytan, David Geva
  • Patent number: 10481908
    Abstract: Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10481909
    Abstract: Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10452542
    Abstract: Provided are a device and method of managing data stored in memory. The device may include a buffer for storing data blocks including a head data block, a tail data block, and intermediate data blocks. Non-used blocks may be further included in the buffer between the head data block and the tail data block. The device may further include a controller for managing the data blocks within the buffer. The managing may include determining a shift direction for the data blocks based on a distribution of the data blocks within the buffer, shifting at least one data block from among the data blocks in the determined direction, and shifting the one or more non-used blocks in an opposite direction from which the at least one data block is shifted. As a result of the shifting, the data blocks may be aggregated within the buffer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 22, 2019
    Assignee: SAP SE
    Inventors: Burak Kurt, Steffen Geissinger, Anil Akay
  • Patent number: 10430565
    Abstract: A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 1, 2019
    Assignee: BlueRISC, Inc.
    Inventors: Csaba Andras Moritz, Saurabh Chheda, Kristopher Carver
  • Patent number: 10430191
    Abstract: Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector of instruction pointers (VIP) processor architecture are disclosed. An example method includes identifying a strand including a fork instruction introducing a first speculative assumption. A basing instruction to initialize a basing value of the strand before execution of a first instruction under the first speculative assumption. A determination of whether a second instruction under a second speculative assumption modifies a first memory address that is also modified by the first instruction under the first speculative assumption is made. The second instruction is not modified when the second instruction does not modify the first memory address. The second instruction is modified based on the basing value when the second instruction modifies the first memory address, the basing value to cause the second instruction to modify a second memory address different from the first memory address.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Yevgeniy M. Astigeyevich, Dmitry M. Maslennikov, Sergey P. Scherbinin, Marat Zakirov, Pavel G. Matveyev, Andrey Rodchenko, Andrey Chudnovets, Boris V. Shurygin
  • Patent number: 10423412
    Abstract: A machine instruction to find a condition location within registers, such as vector registers. The machine instruction has associated therewith a register to be examined and a result location. The register includes a plurality of elements. In execution, the machine instruction counts a number of contiguous elements of the plurality of elements of the register having a particular value in a selected location within the contiguous elements. Other locations within the contiguous elements are ignored for the counting. The counting provides a count placed in the result location.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Markus Kaltenbach, Jentje Leenstra, Brett Olsson
  • Patent number: 10409594
    Abstract: A processing circuit is configured to receive a first binary number composed of a plurality of bits and a second binary number composed of a plurality of bits, and with a digit of the most significant 1-valued bit in the first binary number composed of the plural bits being defined as a first bit digit and with a digit of a bit having a value of 1 first in a higher-order direction than the first bit digit in the second binary number composed of the plural bits being defined as a second bit digit, output a third binary number composed of a plurality of bits out of which a bit corresponding to the second bit digit has a value of 1 and other bits have values of 0, the processing circuit including: a high-order mask processing unit; a low-order mask processing unit; and an output synthesizing unit.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: September 10, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kensuke Shinomiya
  • Patent number: 10387150
    Abstract: A machine instruction to find a condition location within registers, such as vector registers. The machine instruction has associated therewith a register to be examined and a result location. The register includes a plurality of elements. In execution, the machine instruction counts a number of contiguous elements of the plurality of elements of the register having a particular value in a selected location within the contiguous elements. Other locations within the contiguous elements are ignored for the counting. The counting provides a count placed in the result location.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Markus Kaltenbach, Jentje Leenstra, Brett Olsson
  • Patent number: 10298641
    Abstract: A system processes streaming data and includes at least one processor. The system may write streaming data received from a data source as messages in queues at a queuing cluster. The queuing cluster includes a coordinator node to direct the messages to non-coordinator nodes of the queuing cluster. The system may retrieve the data from the queues based on subscription of topics and store the retrieved data in a consumable repository.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Timothy M. Fox, Anyi Li, Scott J. McCallen, Douglas S. Meil, Kaveh Noorbakhsh
  • Patent number: 10268398
    Abstract: A storage system includes a storage device that stores divided data which represents data which is obtained by division of data in a time series; a server device that acquires a first time, searches interval-related information for an interval that overlaps an interval between the first time and a second time following the first time by a specified duration of time, the interval-related information storing information in which identifying information that identifies the divided data and information that relates to intervals which indicate start times and end times of the divided data are associated, and acquires identifying information for the divided data that corresponds to the interval for which the search was performed; and a terminal device that acquires from the storage device the divided data that corresponds to the acquired identifying information and reads out the acquired divided data in chronological order.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 23, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Munenori Maeda, Toshihiro Ozawa
  • Patent number: 10248099
    Abstract: A programmable logic controller executes an SFC program including a plurality of blocks, each including a step indicating an operation output and a transition indicating a transition condition. The programmable logic controller includes an SFC device data collecting unit for collecting device data of a device included in an active step for each scan at the time when the SFC program is executed, an SFC device data storing unit for storing the data collected by the SFC device data collecting unit, and an SFC device data outputting unit for outputting the data stored in the SFC device data storing unit to a memory card as a file for each of the steps or the blocks.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: April 2, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihiro Nagatomo, Yoshifumi Takakura
  • Patent number: 10191742
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen
  • Patent number: 10145961
    Abstract: Efficient transform-based quantization methods and quantization processors implementing such efficient transform-based quantization methods are disclosed. A transform-based quantization method may include: receiving an input signal transformed in a transform domain; producing a low-resolution signal by reducing a resolution of the input signal according to a reduction ratio; inversely transforming the low-resolution signal to produce an inversely transformed low-resolution signal; and quantizing the inversely transformed low-resolution signal to produce a quantized output.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: December 4, 2018
    Assignee: Rockwell Collins, Inc.
    Inventors: Michael H. Stockmaster, Thomas V. Dewulf
  • Patent number: 10127044
    Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: November 13, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas Williams, Sahil Arora, Nikhil Gupta, Wei-Yu Chen, Debjit Das Sarma, Marius Evers
  • Patent number: 10083152
    Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: September 25, 2018
    Assignee: OPEN INVENTION NETWORK LLC
    Inventor: Russell C. McKown
  • Patent number: 10067711
    Abstract: Transferring data from a first data storage cartridge of a first data storage library to a second data storage library. The first library includes a first data storage drive, the second library includes a second data storage drive. A mounting of the first data storage cartridge into the first data storage drive is initiated. A network connection between the first and second data storage drives, with both data storage drives operating in a data transfer mode, is initiated. A mounting of a second data storage cartridge into the second data storage drive is initiated. A copying of the data content of the first data storage cartridge onto the second data storage cartridge via the network connection is initiated. A deletion of the data of the first data storage cartridge is initiated.
    Type: Grant
    Filed: November 1, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bernd Freitag, Brian G. Goodman, Frank Krick, Erik Rueger
  • Patent number: 10025955
    Abstract: The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: July 17, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 9977901
    Abstract: Technologies for protecting systems and data of an organization from malware include a data integrity server configured to receive a data file for import from an external source. The data integrity server analyzes the received data file with multiple anti-malware engines to determine whether the data file includes hidden malware. The data integrity server discards the data file in response to a determination that the data file includes hidden malware. Additionally, the data integrity server verifies the type of the received data file based on the file extension associated with the received data file. The data integrity server cleans the received data file in response to verification of the file type. The cleaned data file is transmitted to a computing device to be imported. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 22, 2018
    Assignee: Operation and Data Integrity Ltd.
    Inventors: Oren Eytan, David Geva
  • Patent number: 9965287
    Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: May 8, 2018
    Assignee: Open Invention Network LLC
    Inventor: Russell C. McKown
  • Patent number: 9946877
    Abstract: Technologies for protecting systems and data of an organization from malware include a data integrity server configured to receive a data file for import from an external source. The data integrity server analyzes the received data file with multiple anti-malware engines to determine whether the data file includes hidden malware. The data integrity server discards the data file in response to a determination that the data file includes hidden malware. Additionally, the data integrity server verifies the type of the received data file based on the file extension associated with the received data file. The data integrity server cleans the received data file in response to verification of the file type. The cleaned data file is transmitted to a computing device to be imported. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 17, 2018
    Assignee: Operation and Data Integrity Ltd.
    Inventors: Oren Eytan, David Geva
  • Patent number: 9940445
    Abstract: A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: April 10, 2018
    Assignee: BlueRISC, Inc.
    Inventors: Csaba Andras Moritz, Saurabh Chheda, Kristopher Carver
  • Patent number: 9934032
    Abstract: A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, Seyed Yahya Sotoudeh, Buford M. Guy
  • Patent number: 9934036
    Abstract: A compiler method that performs parallel processing on a data set using multithreading. The method includes calculating a divisor for dividing the data set. The data set is divided into a number of subsets greater than a number of threads. The method generates a plurality of data subsets and executable code. The code performs processing operations and an instruction executed by a first thread that reaches the code. After completing processing operations related to the subsets that have been assigned to the threads, the next subsets are assigned to the threads. When assigning the next subsets, synchronous processing is performed in order to determine which one of “unprocessed”, “processed”, and “assigned to a different thread” is the state of each of the subsets.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 3, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shunsuke Tanii, Tsuyoshi Hashimoto
  • Patent number: 9928074
    Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: March 27, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yiqun Ge, Wuxian Shi, Qifan Zhang, Tao Huang, Wen Tong