Multiprocessor Instruction Patents (Class 712/203)
  • Patent number: 10409601
    Abstract: An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: William M. Brown, Roland Schulz, Karthik Raman
  • Patent number: 10359953
    Abstract: Systems and methods for offloading data transformation from a host to a hybrid solid state drive (HSSD) are described. In one such method, the HSSD receives initial data from the host and stores the data at a first non-volatile memory (NVM). The HSSD receives a transformation command from the host to offload data transformation. The HSSD copies the data from the first NVM to a second NVM that is configured to provide a finer granularity of data access than that of the first NVM. Then the HSSD transforms the data at the second NVM utilizing the configured processing circuit. The HSSD may store the result in the first NVM and/or second NVM, and send it to the host.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: July 23, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luis Vitorio Cargnini, Viacheslav Anatolyevich Dubeyko
  • Patent number: 10356167
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for profiling and configuring work on a cluster of computer nodes.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 16, 2019
    Assignee: Hortonworks, Inc.
    Inventors: Sheetal Dinkar Dolas, Paul Daniel Codding
  • Patent number: 10333800
    Abstract: Provided are a computer program product, system, and method for allocating physical nodes for processes in an execution plan. An execution plan is generated indicating a plurality of processes. A resource requirement is generated indicating requested physical nodes and an assignment of the processes to execute on the requested physical nodes. A determination is made from the resource requirement of a resource allocation of physical nodes for the requested physical nodes and the processes. The execution plan is updated to generate an updated execution plan indicating the physical nodes on which the processes will execute according to the received resource allocation.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Krishna K. Bonagiri, Eric A. Jacobson, Yong Li, Xiaoyan Pu
  • Patent number: 10325340
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a data entity that causes a processing unit to process a computational graph. In one aspect, method includes the actions of receiving data identifying a computational graph, the computational graph including a plurality of nodes representing operations; obtaining compilation artifacts for processing the computational graph on a processing unit; and generating a data entity from the compilation artifacts, wherein the data entity, when invoked, causes the processing unit to process the computational graph by executing the operations represented by the plurality of nodes.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 18, 2019
    Assignee: Google LLC
    Inventors: Jingyue Wu, Christopher Daniel Leary
  • Patent number: 10291693
    Abstract: Examples of reducing data in a network are disclosed. In one example implementation according to aspects of the present disclosure, method may include receiving, by a network device, data from a mapper system. The method may then include performing, by the network device, a reduction function on the data received from the mapper system to reduce the data. The method may also include transmitting, by the network device, the reduced data to a reducer system.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 14, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Mark Brian Mozolewski
  • Patent number: 10223072
    Abstract: A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. Each iteration includes generating hardware design components for mapping the input range to the target output range using each of a plurality of modulo preserving range reduction methods, synthesizing the generated hardware design components, and selecting one of the generated hardware design components based on the results of the synthesis.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 5, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Samuel Lee
  • Patent number: 10162665
    Abstract: A memory management module receives a request to access a page in a memory, sends the request to a memory controller controlling the memory if the page is available in the memory, and if the page is unavailable, (i) does not send the request to the memory controller, and (ii) generates a first exception. A hypervisor intercepts the first exception and sends a second exception to an operating system. The operating system includes a handler to, in response to the second exception, selectively request the memory controller to obtain the page from a storage device into the memory, and to suspend execution of a first thread issuing the request on a processor until the page becomes available in the memory; and a kernel to schedule execution of a second thread on the processor until the page becomes available, or to idle the processor until the page becomes available.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 25, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Anton Eidelman
  • Patent number: 10157048
    Abstract: An operator split mechanism analyzes code in a streaming application according to specified split criteria to determine when an operator in the streaming application can be split. At compile-time, when an operator satisfies the split criteria, the operator split mechanism splits the operator according to the split criteria. In an integrated development environment (IDE), the operator split mechanism determines when an operator satisfies the split criteria, and splits the operator according to the split criteria. The operator split mechanism can operate in an automatic mode where operators are split without further input from the user, or in a more interactive mode where the operator split mechanism provides recommendations and options to a user, who makes appropriate selections, and the operator split mechanism then functions according to the selections by the user.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, Manuel Orozco, Christopher R. Sabotta, John M. Santosuosso
  • Patent number: 10146519
    Abstract: Disclosed herein provides enhancements for generating large scale processing framework (LSPF) images for deployment in processing environments. In one implementation a method of preparing LSPF service images for large scale data processing environments includes identifying a first LSPF service image, and identifying metadata that defines runtime requirements for deploying the LSPF service in data processing environments. The method further provides generating scripts for deploying the LSPF service based on the metadata, and generating a second LSPF service image for the LSPF service, wherein the second LSPF service image includes the scripts.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: December 4, 2018
    Assignee: Bluedata Software, Inc.
    Inventor: Krishna C. Sagiraju
  • Patent number: 10133496
    Abstract: The disclosed techniques may employ components referred to herein as atoms for computing and maintaining of states. Unlike traditional actors, atoms may be capable of binding to other atoms to form a bound combination of atoms, referred to herein as a molecule. In some examples, while bound to other atoms, an atom may operate in a manner that is different from traditional actors. For example, in some cases, atoms that are bound to one another may be prohibited from concurrently performing different operations on their own separate states. Additionally, bound atoms may be operable to collectively (e.g., synchronously) perform shared operations on their associated states. Furthermore, a shared operation performed on the states of bound atoms may be performed atomically. Also, in some examples, bound atoms may be capable of communicating synchronously with one another and of synchronously accessing each other's states.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: November 20, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Juan Pablo Ferreyra, Brian David Fisher, Adam Julio Villalobos, Yu Ping Hu
  • Patent number: 10089230
    Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M Cimini, Abhishek R. Appu
  • Patent number: 10038448
    Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 31, 2018
    Assignee: Cavium, Inc.
    Inventors: Weihuang Wang, Gerald Schmidt, Srinath Atluri, Weinan Ma, Shrikant Sundaram Lnu
  • Patent number: 9992269
    Abstract: A complex event query specification may be constructed that a complex event processing engine uses to analyze an event stream for an occurrence of a complex event. Event data stored in a distributed file system are mapped to respective instances of the complex event processing engine in respective distributed event streams. The distributed event streams are analyzed by the independently executing complex event processing engines in accordance with the complex event query specification. The occurrence of the complex event in any of the distributed event streams is indicated at the output of the complex event processing engines.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 5, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeffrey M. Odom, Michael P. Fikes, John Swift
  • Patent number: 9934100
    Abstract: A memory swap operation comprises writing information about a process in which a page fault occurred, into a temporary memory using a processor of a host, copying a page in which the page fault occurred, from a memory device recognized as a swap memory into a main memory of the host, and after completing the copying of the page, resuming the process in which the page fault occurred, using the information about the process, written in the temporary memory.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Young Lim, Sung-Yong Seo, Young-Jin Cho, Ju-Yun Jung
  • Patent number: 9904524
    Abstract: The present invention relates to a method and device for visually implementing a software code. To this end, a method for visually implementing a software code according to the present invention comprises the steps of: generating, by a code block generation unit, a code block used for implementing a software code by the unit of block depending on a requirement and a function; and setting, by a code block setting unit, a code block attribute or an internal attribute code included in the code block on the basis of information input from a user, wherein the step of setting the code block attribute or the internal attribute code comprises the step of including function information on the code block, description information on the function information, and the internal attribute code in the code block.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: February 27, 2018
    Inventors: Soo-Jin Hwang, In-Suk Choi
  • Patent number: 9891655
    Abstract: A parallel operation system includes a first node including a first processor configured to execute a first process, a second processor configured to execute a second process, and a first memory, and a second node including a third processor configured to execute a third process, a fourth processor configured to execute a fourth process, and a second memory, and a first signal line that transfers synchronization information between at least one of the first and second processors and at least one of the third and fourth processors, wherein when the first process is to be synchronized with the third process, at least one of the first and the third processors using the first signal line to execute a first synchronization process.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 13, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Ryota Sakurai
  • Patent number: 9892144
    Abstract: Methods and apparatus are provided for serializing data. A computing device can generate a serialization buffer (SB). The SB can specify fields storing data and corresponding offsets, with an offset referring to a location in the SB storing the corresponding field. The SB can access a designated field in the SB by determining a designated offset for the designated field, determining a starting location based on the designated offset, and accessing data at the starting location. A distinct copy of the SB can be stored on a storage device.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 13, 2018
    Assignee: Google LLC
    Inventors: Wouter van Oortmerssen, Martin Froehlich
  • Patent number: 9832081
    Abstract: Provided are a computer program product, system, and method for allocating physical nodes for processes in an execution plan. An execution plan is generated indicating a plurality of processes. A resource requirement is generated indicating requested physical nodes and an assignment of the processes to execute on the requested physical nodes. A determination is made from the resource requirement of a resource allocation of physical nodes for the requested physical nodes and the processes. The execution plan is updated to generate an updated execution plan indicating the physical nodes on which the processes will execute according to the received resource allocation.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Krishna K. Bonagiri, Eric A. Jacobson, Yong Li, Xiaoyan Pu
  • Patent number: 9811845
    Abstract: A system generates a plurality of price master data lookup procedures that are capable of being executed in parallel. The plurality of price master data lookup procedures is stored in a repository in an in-memory system. The in-memory system includes a parallel processor. The system accesses the repository of price master data lookup procedures, and retrieves price master data in parallel using the price master data lookup procedures. The system then calculates a price using the price master data retrieved from the price master database in the in-system memory.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 7, 2017
    Assignee: SAP SE
    Inventors: Prajesh K, Baris Yalcin
  • Patent number: 9798544
    Abstract: Systems and methods for scheduling instructions for execution on a multi-core processor reorder the execution of different threads to ensure that instructions specified as having localized memory access behavior are executed over one or more sequential clock cycles to benefit from memory access locality. At compile time, code sequences including memory access instructions that may be localized are delineated into separate batches. A scheduling unit ensures that multiple parallel threads are processed over one or more sequential scheduling cycles to execute the batched instructions. The scheduling unit waits to schedule execution of instructions that are not included in the particular batch until execution of the batched instructions is done so that memory access locality is maintained for the particular batch. In between the separate batches, instructions that are not included in a batch are scheduled so that threads executing non-batched instructions are also processed and not starved.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 24, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Olivier Giroux, Jack Hilaire Choquette, Xiaogang Qiu, Robert J. Stoll
  • Patent number: 9798831
    Abstract: A computer-implemented method for processing input data in a mapreduce framework includes: receiving, in the mapreduce framework, a data processing request for input data; initiating, based on the data processing request, a map operation on the input data by multiple mappers in the mapreduce framework, each of the mappers using an aggregator to partially aggregate the input data into one or more intermediate key/value pairs; initiating a reduce operation on the intermediate key/value pairs by multiple reducers in the mapreduce framework, wherein, without sorting the intermediate key/value pairs, those of the intermediate key/value pairs with a common key are handled by a same one of the reducers, each of the reducers using the aggregator to aggregate the intermediate key/value pairs into one or more output values; and providing the output values in response to the data processing request.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 24, 2017
    Assignee: Google Inc.
    Inventors: Biswapesh Chattopadhyay, Liang Lin, Weiran Liu, Marián Dvorský
  • Patent number: 9785568
    Abstract: Techniques described herein are generally related to retrieval of data in computer systems having multi-level caches. The multi-level cache may include at least a first cache and a second cache. The first cache may be configured to receive a request for a cache line. The request may be associated with an instruction executing on a tile of the computer system. A suppression status of the instruction may be determined by a first cache controller to determine whether look-up of the first cache is suppressed based upon the determined suppression status. The request for the cache line may be forwarded to the second cache by the first cache controller after the look-up of the first cache is suppressed.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: October 10, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Sriram Vajapeyam
  • Patent number: 9787761
    Abstract: Provided are a computer program product, system, and method for allocating physical nodes for processes in an execution plan. An execution plan is generated indicating a plurality of processes. A resource requirement is generated indicating requested physical nodes and an assignment of the processes to execute on the requested physical nodes. A determination is made from the resource requirement of a resource allocation of physical nodes for the requested physical nodes and the processes. The execution plan is updated to generate an updated execution plan indicating the physical nodes on which the processes will execute according to the received resource allocation.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Krishna K. Bonagiri, Eric A. Jacobson, Yong Li, Xiaoyan Pu
  • Patent number: 9632832
    Abstract: Technologies are generally described for methods and systems to assign threads in a multi-core processor. In an example, a method to assign threads in a multi-core processor may include determining data relating to memory controllers fetching data in response to cache misses experienced by a first core and a second core. Threads may be assigned to cores based on the number of cache misses processed by respective memory controllers. Methods may further include determining that a thread is latency-bound or bandwidth-bound. Threads may be assigned to cores based on the determination of the thread as latency-bound or bandwidth-bound. In response to the assignment of the threads to the cores, data for the thread may be stored in the assigned cores.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: April 25, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9619215
    Abstract: A method for reducing a compile time of a source program includes receiving, by a compiler hosted on a computer, the source program. The compiler may have a compile time that depends non-linearly on a size of a function in the source program. The method involves identifying a source function in the source program and splitting the source function in to two or more target functions having sizes smaller than a size of the source function. The method further includes compiling the source program with the two or more target functions having sizes smaller than a size of the source function replacing the source function in the source program.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 11, 2017
    Assignee: SAP SE
    Inventors: Markus Eble, Soeren Pottberg
  • Patent number: 9558049
    Abstract: Shuffle optimization in map-reduce processing. The method includes: obtaining intermediate results from a plurality of mappers for an application on a computing device; combining the intermediate results from the plurality of mappers; and partitioning the combined intermediate results into intermediate results for respective reducers for the application based on respective keys of the combined intermediate results.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Liang Liu, Junmei Qu, Chao Qiang Zhu, Wei Zhuang
  • Patent number: 9521324
    Abstract: An electronic apparatus and a method of controlling the same are described. A method of controlling an electronic apparatus having a main processor and an image processor includes: booting the main processor and the image processor according to a power input signal of the photographing apparatus; when the image processor is completely booted, performing a photographing preparation operation; photographing an object, performed by the image processor, in response to a shutter release signal; and generating photographing data of the object, performed by the image processor.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-young Jang, Sung-bin Hong
  • Patent number: 9507569
    Abstract: A digital data processing system that is designed to facilitate use of UML activity diagrams.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: November 29, 2016
    Assignee: u-Blox AG
    Inventors: Erkut Uygun, Jan Guffens, Paul Tindall
  • Patent number: 9471291
    Abstract: A method for processing computer program code to enable different parts of the computer program code to be executed by different processing elements of a plurality of communicating processing elements. The method comprises identifying at least one first part of the computer program code, which is to be executed by a particular one of said processing elements. The method further comprises identifying at least one further part of the computer code which is related to the at least one first part of the computer code. The at least one first part of the computer program code and the at least one further part of the computer program code are caused to be executed by the particular one of said processing elements.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 18, 2016
    Assignee: Codeplay Software Limited
    Inventors: Jens-Uwe Dolinsky, Andrew Richards, Colin Riley
  • Patent number: 9424112
    Abstract: Embodiments for a method of interfacing with a remote application programming interface (API) by defining an execution plan using an interface definition language and a dependency configuration file to generate a constrained directed graph of hierarchically dependent functions of the API, and executing the execution plan using an executing engine that traverses the graph to call the API functions in a defined order and convert data output by a parent function call to input required by a child function call until a terminal vertex is reached that results in directing the resulting in an action such as data to persist and/or affecting the state of a system.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: August 23, 2016
    Assignee: EMC Corporation
    Inventors: Mark David Malamut, Erik Hansen, Scott Auchmoody, Jeffrey Norton, Christopher J Hackett
  • Patent number: 9424160
    Abstract: Data flow disruptions over a series of data processing operators can be detected by a computer system that generates a profile for data flow at an operator. The profile can include data input, processing, and output wait times. Using the profile, the system can detect potential flow disruptions. If the potential disruption satisfies a rule, it is considered a data flow disruption and a recommendation associated with the satisfied rule is identified. The recommendation and the operator identity is displayed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian K. Caufield, Lawrence A. Greene, Eric A. Jacobson, Yong Li, Shyam R. Mudambi, Xiaoyan Pu, Dong J. Wei
  • Patent number: 9424074
    Abstract: Aspects of the disclosure relate to learning the most useful backup tasks when processing a job in a distributed computing application. For example, training data may be generated by running a job and running backup tasks for some of the tasks for that job. List of features may be generated for each backup task at different times. A representative list of features may be labeled according to the backup tasks usefulness to the job. The lists and usefulness labels may be used to generate a model of usefulness. The model may then be used to evaluate the usefulness of the tasks for the next job. This information may then be used to schedule backup tasks for execution. In addition, lists of features for these backup tasks may be generated and then used to update the model in a continuous learning loop.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 23, 2016
    Assignee: Google Inc.
    Inventors: Jelena Pjesivac-Grbovic, Kenneth Jerome Goldman, Matthew Faulkner, Wesley Kendall
  • Patent number: 9411633
    Abstract: A computing system for handling barrier commands includes a memory, an interface, and a processor. The memory is configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command. The interface is coupled to the memory and is configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier spreading range and receive a barrier completion notification messages from the target computing system. The pre-barrier computing probe is configured to instruct the target computing system to monitor a status of a transaction that needs to be executed for the barrier command to be completed. The processor is coupled to the interface and is configured to determine a status of the barrier command based on the received barrier completion notification messages.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: August 9, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Iulin Lih, Chenghong He, Hongbo Shi, Naxin Zhang
  • Patent number: 9378053
    Abstract: A method and system for operating a data center. The method includes, in response to a map task distributed by a job tracker, a map task tracker executes the map task to generate a map output including version information. The map task tracker stores the generated map outputs. The map task tracker informs the job tracker of related information of the map output. In response to a reduce task distributed by the job tracker, the reduce task tracker acquires the map outputs for key names including given version information from the map task trackers, wherein the acquired map outputs include the map outputs with the given version information and historical map outputs with the version information prior to the given version information. The reduce task tracker executes the reduce task on the acquired map outputs.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bin Cai, Zhe Xiang, Wei Xue, Bo Yang, Qi Yu
  • Patent number: 9378012
    Abstract: Data is received that includes at least a portion of a program. Thereafter, entry point locations and execution-relevant metadata of the program are identified and retrieved. Regions of code within the program are then identified using static disassembly and based on the identified entry point locations and metadata. In addition, entry points are determined for each of a plurality of functions. Thereafter, a set of possible call sequences are generated for each function based on the identified regions of code and the determined entry points for each of the plurality of functions. Related apparatus, systems, techniques and articles are also described.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: June 28, 2016
    Assignee: Cylance Inc.
    Inventors: Derek A. Soeder, Matt Wolff
  • Patent number: 9323775
    Abstract: A map-reduce compatible distributed file system that consists of successive component layers that each provide the basis on which the next layer is built provides transactional read-write-update semantics with file chunk replication and huge file-create rates. A primitive storage layer (storage pools) knits together raw block stores and provides a storage mechanism for containers and transaction logs. Storage pools are manipulated by individual file servers. Containers provide the fundamental basis for data replication, relocation, and transactional updates. A container location database allows containers to be found among all file servers, as well as defining precedence among replicas of containers to organize transactional updates of container contents. Volumes facilitate control of data placement, creation of snapshots and mirrors, and retention of a variety of control and policy information.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: April 26, 2016
    Assignee: MapR Technologies, Inc.
    Inventors: Mandayam C. Srivas, Pindikura Ravindra, Uppaluri Vijaya Saradhi, Arvind Arun Pande, Chandra Guru Kiran Babu Sanapala, Lohit Vijaya Renu, Vivekanand Vellanki, Sathya Kavacheri, Amit Ashoke Hadke
  • Patent number: 9256408
    Abstract: Aspects of this disclosure relate to a method of compiling high-level software instructions to generate low-level software instructions. In an example, the method includes identifying, with a computing device, a set of high-level (HL) control flow (CF) instructions having one or more associated texture load instructions, wherein the set of HL CF instructions comprises one or more branches. The method also includes converting, with the computing device, the identified set of HL CF instructions to low-level (LL) instructions having a predicate structure. The method also includes outputting the converted (LL) instructions having the predicate structure.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 9, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Weifeng Zhang, Chihong Zhang
  • Patent number: 9195521
    Abstract: A non-transitory computer-readable storage medium may comprise a set of instructions for creating a subsystem process independent from a main system process for data computation. The set of instructions may direct at least one processor to perform acts of: in a main system process, receiving a user input; in the main system process, sending the user input to a subsystem process, the subsystem process is independent from and in parallel with the main system process; in the main system process, generating a first computation result according to the user input; in the subsystem process, generating a second computation result in parallel with the main system process according to the user input; in the main system process, receiving the second computation result from the subsystem process; and in the main system process, combining the first computation result and the second computation result.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 24, 2015
    Assignee: Tencent Technology (Shenzhen) Co., Ltd.
    Inventors: Yuanxue Zhao, Ansong Yao, Chao Zhong, Zhiming Nie, Kai Xu, Lanqi Song, Lei Jiang
  • Patent number: 9170864
    Abstract: Data processing in a hybrid computing environment that includes a host computer, a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module, the host computer having local memory shared remotely with the accelerators, the accelerators having local memory for the plurality of accelerators shared remotely with the host computer, where data processing according to embodiments of the present invention includes performing, by the plurality of accelerators, a local reduction operation with the local shared memory for the accelerators; writing remotely, by one of the plurality of accelerators to the shared memory local to the host computer, a result of the local reduction operation; and reading, by the host computer from shared memory local to the host computer, the result of the local reduction operation.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: October 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, James E. Carey, Matthew W. Markland, Philip J. Sanders, Timothy J. Schimke
  • Patent number: 9146830
    Abstract: The technology provides a hybrid local/remote hosted MapReduce framework and infrastructure comprising systems and methods for improving setup, configuration, controllability, debuggability, and integration of a compute job and systems and methods for increasing programmer productivity. The system applies an interpreted programming language for the programmer's custom Map and Reduce algorithms, such that those algorithms can execute identically on both the hosted service as well as locally (e.g., on the programmer's local computing system or device) for development and debugging purposes. Furthermore, the system delivers this service—a hosted MapReduce infrastructure—in a simple and transparent web service.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: September 29, 2015
    Assignee: JSMapreduce Corporation
    Inventor: Ervin Peretz
  • Patent number: 9104399
    Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fadi Busaba, Brian Curran, Lee Eisen, Christian Jacobi, David A. Schroter, Eric Schwarz
  • Patent number: 9081901
    Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 14, 2015
    Assignee: RAYTHEON COMPANY
    Inventors: Lloyd J. Lewins, William D. Farwell, Kenneth E. Prager, Michael D. Vahey
  • Patent number: 9046593
    Abstract: A method and apparatus for detecting signals. According to an embodiment, energy waves are received at a first receiver system and a second receiver system. The first receiver system generates first information using the energy waves received at the first receiver system. The first receiver system receives second information generated using the energy waves received at the second receiver system from the second receiver system. The first receiver system identifies desired information about a repetitive portion of a signal carried in the energy waves received at the first receiver system using the first information and the second information.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 2, 2015
    Assignee: THE BOEING COMPANY
    Inventors: Gary Alan Ray, James Bryan Baker, Daniel Stewart Summers
  • Patent number: 9047141
    Abstract: A large-scale data processing system and method including a plurality of processes, wherein a master process assigns input data blocks to respective map processes and partitions of intermediate data are assigned to respective reduce processes. In each of the plurality of map processes an application-independent map program retrieves a sequence of input data blocks assigned thereto by the master process and applies an application-specific map function to each input data block in the sequence to produce the intermediate data and stores the intermediate data in high speed memory of the interconnected processors. Each of the plurality of reduce processes receives a respective partition of the intermediate data from the high speed memory of the interconnected processors while the map processes continue to process input data blocks an application-specific reduce function is applied to the respective partition of the intermediate data to produce output values.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: June 2, 2015
    Assignee: GOOGLE INC.
    Inventors: Grzegorz Malewicz, Marian Dvorsky, Christopher B. Colohan, Derek P. Thomson, Joshua Louis Levenberg
  • Patent number: 9013717
    Abstract: A handheld imaging device includes an image sensor for sensing an image; a multi-core processor for processing the sensed image; and a program memory provided external to the multi-core processor, and communicating therewith via a communication bus. The multi-core processor includes a bus interface for interfacing with the communication bus, and further includes an image sensor interface for interfacing with the image sensor separately from the communication bus and the bus interface. The multi-core processor includes a plurality of parallel processing units connected by a crossbar switch to form the multi-core.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: April 21, 2015
    Assignee: Google Inc.
    Inventor: Kia Silverbrook
  • Patent number: 9015622
    Abstract: Some embodiments of a system and a method to tune a computing system based on a profile have been presented. A profile as used herein broadly refers to a file containing various parameters of a computing system, such as kernel parameters (e.g., buffer size, network setup, etc.), usable to configure the computing system. For instance, a set of profiles are stored in a computer-readable storage device in a computing system, such as a server, a personal computer, a laptop computer, etc. A processing device miming on the computing system may receive a user selection of one of the set of profiles. In response to the user selection, the processing device may load the selected profile onto the computing system in order to tune the computing system according to the selected profile.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: April 21, 2015
    Assignee: Red Hat, Inc.
    Inventors: Thomas K. Wörner, Christopher Haughey Snook
  • Patent number: 8996278
    Abstract: In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the internal combustion engine, the control unit includes a selecting unit, that selects at least one core used in the computation from among the plurality of cores, a computing unit that distributes the tasks to the at least one core selected by the selecting unit to perform computation, and an acquisition unit that acquires an engine, rotational speed of the internal combustion engine, and, when the engine rotational speed acquired by the acquisition unit is higher than or equal to a predetermined threshold, the selecting unit increases the number of the cores selected as compared with when the acquired engine rotational speed is lower than the predetermined threshold.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 31, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hayato Nakada, Akira Ohata, Keisuke Osakabe
  • Patent number: 8990767
    Abstract: A method, system, and article of manufacture for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a computer with a plurality of processors. The method includes: generating segments of block with or without duplication for each block with an internal state and for each block without any output by traversing the graphical model from each block with an internal state to each block without any output; merging the segment to reduce duplication; compiling and converting each segment from the merged results in an executable code; and individually allocating the executable code for each segment to a plurality of processors for parallel execution.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kumiko Maeda, Shuichi Shimizu, Takeo Yoshizawa
  • Patent number: 8966491
    Abstract: NUMA-aware reader-writer locks may leverage lock cohorting techniques to band together writer requests from a single NUMA node. The locks may relax the order in which the lock schedules the execution of critical sections of code by reader threads and writer threads, allowing lock ownership to remain resident on a single NUMA node for long periods, while also taking advantage of parallelism between reader threads. Threads may contend on node-level structures to get permission to acquire a globally shared reader-writer lock. Writer threads may follow a lock cohorting strategy of passing ownership of the lock in write mode from one thread to a cohort writer thread without releasing the shared lock, while reader threads from multiple NUMA nodes may simultaneously acquire the shared lock in read mode. The reader-writer lock may follow a writer-preference policy, a reader-preference policy or a hybrid policy.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: February 24, 2015
    Assignee: Oracle International Corporation
    Inventors: Irina Calciu, David Dice, Victor M. Luchangco, Virendra J. Marathe, Nir N. Shavit, Yosef Lev