Abstract: An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Z36 and AK36 of the Socket-370 central processing unit to determine which type the Socket-370 central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-370 central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-370 central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.

Abstract: A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller includes a message reception controller for receiving a message from another node and judging illustratively the status of message reception and the need to return an acknowledge message; an acknowledge generating unit for generating an acknowledge message transmission request based on predetermined information in the message and the reception status when the return of an acknowledge message is judged to be necessary; and a message transmission controller for receiving an acknowledge the message transmission request and generating and returning an acknowledge message correspondingly. At the receiving node, the network interface controller can return an acknowledge message without processor intervention.

Abstract: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.

Abstract: A vector computer system includes a plurality of memory banks 40, a vector processor 11, and a plurality of additional processing units 30 each of which is connected to one of the memory banks 40. Each of the additional processing units 30 reads data from the corresponding memory bank 40 by referring to an address designated by the processor 11, and performs a designated operation about the data. Then the additional processing unit 30 stores the result of the operation into the designated address.

Abstract: A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first identifies a bin associated with blocks (“lockers”) of memory large enough to satisfy a memory allocation request. When the identified bin has a free locker, the memory allocation system searches a circular list of headers associated with the identified bin for a collection of lockers (“warehouse”) that contains a locker that is available to be allocated. The memory allocation system allocates the found available locker to satisfy the request. If, however, the allocated bin has no free lockers, the memory allocation system allocates a warehouse with lockers large enough to satisfy the memory allocation request.

Abstract: One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g.

Abstract: A system provides an environment for parallel programming by providing a plurality of modular parallelizable operators stored in a computer readable memory. Each operator defines operation programming for performing an operation, one or more communication ports, each of which is either an input port for providing the operation programming a data stream of records, or an output port for receiving a data stream of records from the operation programming and an indication for each of the operator's input ports, if any, of a partitioning method to be applied to the data stream supplied to the input port.

Abstract: In the data driven computer system (FIG. 4, FIG. 7), data are transferred between data driven computers (1, 11, 12, 21, 22, 24, 25, . . . , and n), with instruction code (code) and identification numbers to identify data for arithmetic operation. Calculation results obtained by arithmetic units (111, 121, 21n, 22n, 24n, 25n, . . . , and nn) are stored in a data field (data). In parallel, an instruction rewriting units (3, 115, 125, 134, 211, 221, 241, 251, . . . , and nl) calculates an instruction code to be used in a following process and then rewrite a current instruction code with the calculated one without any execution of a microprocessor (14) or other controller. The result of the arithmetic operation is transferred to a peripheral device (16) or the microprocessor (14) through the data driven computer (13, 23).

Abstract: A network browsing system includes a host computer coupled to a client computer by a network. A network browser process implemented on the client computer is capable of establishing a connection with the host computer and of generating a request for desired data from the host computer which is to generate desired images on the display of the client computer. A server process implemented on the host computer services the request for desired data received from the client computer by modifying the desired data into modified data such that no additional connection between the client computer and the host computer is required to receive the entirety of the modified data. The browser process of the client computer can generate the desired images from the modified data to the same extent that it could from the originally requested desired data.

Abstract: A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes and that execute a long type register branch instruction are provided. Thus, a register branch instruction can be executed with three instructions rather than five instructions unlike with a related art reference.

Abstract: A technique for searching in a source sequence for a target sequence using parallel processing.

Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.

Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.

Abstract: An apparatus for receiving and processing digital signals. Techniques and apparatus are disclosed for reducing power consumption in digital receiving and processing circuits without manual intervention and without data rate reduction. The digital signal comprises a leading, slower data rate signal and a trailing, faster data rate signal. When the pre-defined leading signal is received, a slower digital-signal processor processes that signal and then activates a faster digital-signal processor which processes the trailing, faster signal. After processing the trailing signal, the faster digital-signal processor is deactivated.

Abstract: A network browsing system includes a host computer coupled to a client computer by a network. A network browser process implemented on the client computer is capable of establishing a connection with the host computer and of generating a request for desired data from the host computer which is to generate desired images on the display of the client computer. A server process implemented on the host computer services the request for desired data received from the client computer by modifying the desired data into modified data such that no additional connection between the client computer and the host computer is required to receive the entirety of the modified data. The browser process of the client computer can generate the desired images from the modified data to the same extent that it could from the originally requested desired data.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization.

Abstract: A microprocessor capable of performing multimedia and non-multimedia operations provided a plurality of stack based instructions is provided. The microprocessor includes a stack processor coupled to a stack capable of storing values, a register processor coupled to a register file capable of storing values, and a copy-unit having a first port coupled to the stack and a second port coupled to the register file being configured to copy data between the register file and the stack. The microprocessor also includes logic coupled to receive the plurality of stack based instructions from memory, cache, or other storage devices coupled to the microprocessor. The logic is configured to determine which of the plurality of stack based instructions are regular stack instructions and which of the plurality of stack based instructions are extended stack instructions.

Abstract: Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.

Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

Abstract: A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed.

Abstract: A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.

Abstract: A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The processor includes execution logic having a pipeline for executing the nonserializing instruction. The processor also includes logic separate from the execution logic for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic. The serializing instruction is executed without providing the serializing instruction to the pipeline.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.

Abstract: A microprocessor is provided which detects an escape instruction. The escape instruction indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate instruction set is encoded in the escape instruction. The subsequent instructions are routed to an execution unit or a separate processor for execution. Each instruction sequence within a program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. In one embodiment, the microprocessor executes the x86 instruction set and the alternate instruction set is the ADSP 2171 instruction set. The escape instruction is defined using a previously undefined opcode within the x86 instruction set. Complex mathematical functions (which are more efficiently executed within a DSP) may be performed more efficiently than previously achievable using the x86 instruction set alone.

Abstract: A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.