Abstract: A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing.

Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.

Abstract: A processing system has a processor core (104) executing instructions of a first instruction set and an instruction translator (108) for generating translator output signals corresponding to one or more instructions of the first instruction set so as to emulate instructions of a second instruction set. The instruction translator (108) provides translator output signals specifying operations that are arranged so that the input variables to an instruction of the second instruction set are not changed until the final operation emulating that instruction is executed. An interrupt handler services an interrupt after execution of an operation of the instructions of the first instruction set.

Abstract: A data processing apparatus (102) includes a processor core (104) having a bank of registers (106). The bank of registers (106) include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator (108) into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core (104). The instruction translator (108) has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1:i+1˜i+4; F2:i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation.

Abstract: A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are not using the MAC circuitry. During the idle times, the DSP processor gives control of the MAC to the fixed function circuit. The fixed functions provided by the fixed function circuit can include digital filters, including a Finite Impulse Response filters (FIR), an Infinite Impulse Response (IIR) filter, or an oversampling filter associated with a sigma-delta converter. The DSP may, under program control, set up specific parameters for the fixed function, provide parameters to the fixed function parameter memory, or obtain results from the fixed function. Parameters for the fixed function circuit include the type of filter, the number of taps and the filter coefficients. For a decimation filter, the fixed function parameters can also include the decimation factor.

Abstract: A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.

Abstract: A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Abstract: A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application.

Abstract: A method is shown for selecting active, or hot, code traces in an executing program for storage in a code cache. A trace is a sequence of dynamic instructions characterized by a start address and a branch history which allows the trace to be dynamically disassembled. Each trace is terminated by execution of a trace terminating condition which is a backward taken branch, an indirect branch, or a branch whose execution causes the branch history for the trace to reach a predetermined limit. As each trace is generated by the executing program, it is loaded into a buffer for processing. When the buffer is full, a counter corresponding to the start address of each trace is incremented. When the count for a start address exceeds a threshold, then the start address is marked as being hot. Each hot trace is then checked to see if the next trace in the buffer shares the same start address, in which case the hot trace is cyclic.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: A computer system employing a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). The host processor core executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor core communicates with the emulation coprocessor core to cause the emulation coprocessor core to execute the foreign application program. Accordingly, application programs coded according to the foreign instruction set architecture can be executed directly in hardware. The computer system may be characterized as a heterogeneous multiprocessing system.

Abstract: A space-efficient and flexible mechanism for implementing a virtual machine in a resource-constrained environment such as a smartcard is proposed. The virtual machine is designed for interpreting or carrying out instructions which are identified by an instruction code, also called opcode. Both, the addresses, respectively identifiers, of the functions implementing the instruction codes, respectively opcodes, which the virtual machine interprets, as well as parameters to those functions are kept within lookup tables.

Abstract: A data processing apparatus for executing multiple instruction sets.

Abstract: An internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and one destination-operand bit field for designating a register-to-register operation. Another format is a load-store format that includes an instruction-type bit field, an identifier of a source or destination register for the respective load or store operation, and bit fields for specifying the segment, base and index parameters of an address.

Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.

Abstract: A method for growing a secondary trace out of a cache of translations for a program during the program's execution in a dynamic translator, comprising the steps of: maintaining execution counts for translation heads that are executed from a code cache; when an execution count for one of said translation heads exceeds a threshold, designated as a hot translation head, beginning a mode of operation in which, as following code translations are executed from the code cache after the execution of the hot translation head, storing in a history buffer information identifying each of the following code translations in sequence; terminating the storing of information in the history buffer in relation to the hot translation head when a termination condition is met; and linking together the translation head and the sequence of following code translations identified in the history buffer to form a larger code translation.

Abstract: Code and instruction encoding extensions to a microcontroller architecture provide backward compatibility with an existing microcontroller while allowing significant performance enhancements as a result to the new architecture. An extension to provide additional instruction codes has been implemented while retaining backwards compatibility so that the instructions for the prior processor retain their functionality by utilizing one unused opcode in the prior processor's opcode map. In this connection, two modes of operation are provided, namely binary and source modes. The entire instruction set is available in both modes, but the encoding is different. In the binary mode, all of the instructions of the prior processor keep their encoding. The additional instructions have an ASH prefix, ASH being the single unused opcode. In source mode, some of the instructions from the prior processor known as register instructions have the AS prefix, thereby freeing up 160 opcodes for more important instructions.

Abstract: An improved computer architecture and system advantageously combine the beneficial characteristics of a high level object oriented programming language with an optimized processor for efficient application to real time embedded computing problems. Additionally, an improved method for resolving symbolic references in code generated by compiling source code written in an object oriented programming language to the corresponding logical memory addresses stores look-up information with the object itself after the first encounter of a given symbolic reference, whereby the logical memory address information is available for subsequent encounters of the symbolic reference, and whereby no modification of the program instructions containing the symbolic reference is necessary. In a preferred embodiment, the Java™ programming language is used.

Abstract: A computer system includes a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured to execute instructions defined by a different instruction set architecture from the host instruction set architecture (“the foreign instruction set architecture”). According to one embodiment, the host processor executes operating system code as well as application programs which are coded in the host instruction set architecture. Upon initiation of a foreign application program, the host processor communicates with the emulation coprocessor to cause the emulation coprocessor to execute the foreign application program. The computer system also includes a bus bridge coupled to the host processor and the emulation coprocessor.

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The keyed program operation permits secure transfer of program data through open channels such as the Internet. A programmable instruction decoder programmable decodes encrypted instruction op codes, without decrypting them into standard op codes. Logic is used to accomplish network handshaking. The network handshaking further used to provide additional key information for continued operation the CPU.

Abstract: A preprocessor is functionally inserted between a memory and a processor core. The preprocessor fetches virtual machine instructions, like Java instructions, from the memory and from them it generates native instructions which are supplied to the processor core. In response to a special virtual instruction the preprocessor supplies a native jump to subroutine to the processor core, monitors when the processor core returns from that subroutine and then resumes supplying generated native instructions. The invention also provides for a processor which has a special instruction which calls a subroutine and causes the processor to convert a call context for virtual machine instructions to a call context for a high level language subroutine before making the call.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each instruction contains at least a single bit indicating said instruction sizes. An instruction buffer coupled with an instruction size evaluation unit for determining the instruction size upon said at least single bit of said instruction is provided.

Abstract: A source program is executed on microcontroller core 114 of a processing unit 100. The core 114 is capable of native instructions from a predetermined set of micro-controller specific instructions. In a pre-processing step, for the program statements of the source program a program-specific virtual machine is defined with a corresponding set of virtual machine instructions, such that the expression of the program statements in the sequence of instructions requires less storage space compared to using only native instructions. For the program-specific virtual machine an associated conversion means 132 is defined for converting the program-specific virtual machine instructions into the native instructions of the core 114. The source program statements are expressed in a sequence of instructions comprising instructions of the defined virtual machine. The sequence of instructions is stored in an instruction memory 120. The conversion means 114 is represented in the processing unit 100.

Abstract: A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Abstract: The instruction translator includes a translator for reading out a corresponding instruction from the instruction memory in response to the received address to be executed by the processor and translating the instruction in a second instruction architecture into an instruction in a first instruction architecture, an instruction cache for temporarily holding the instruction in the first instruction architecture after the translation by the translator in association with the address in the instruction memory, and a selector for searching the instruction cache in response to the received address of an instruction to be executed by the processor, and based on a determination result of whether or not an instruction corresponding to the instruction of the address is held in the instruction cache, selectively outputting an instruction output by the translator, and the corresponding instruction in the first instruction architecture which has been held in the instruction cache.

Abstract: To provide a method of implementing cache logic technique in which total data processing time can be reduced, input data divided into block is sequentially processed in units of block in plural circuits using a programmable logic device provided with a circuit information input controller, a programmable logic circuit sector and a data cache. The plural circuits are sequentially reconfigured in the programmable logic device and execute processing per plural blocks which can be stored in the data cache. Intermediate data in units of plural blocks is stored in the data cache to be input data to a reconfigured circuit and intermediate data as the result of the processing by the reconfigured circuit is overwritten to the data cache. When the processing of the plural circuits is finished, the result of the processing is output to an external device without being stored in the data cache.

Abstract: A program controller for use in a processor operating on pipe-line principles includes: a first memory section for outputting an instruction contained in a first program including a plurality of instructions; a second memory section for outputting an instruction contained in a second program including a plurality of instructions, the first program being different from the second program; a selection section for selecting either the instruction which is output from the first memory section or the instruction which is output from the second memory section; a determination section for determining whether or not the instruction selected by the selection section is an instruction for controlling the execution order of instructions; and a control section for, if the instruction selected by the selection section is determined as an instruction for controlling the execution order of instructions, controlling the selection section so as to switch from the selected instruction to the unselected instruction of either th

Abstract: A method for executing instructions on an application-specific microprocessor having a machine language is described. Microcontroller-like instructions are provided in a virtual language for execution on the processor. High-level DSP-like functions are compiled into DSP-like instructions in the machine language for execution on the processor. The microcontroller-like instructions are combined with the DSP-like instructions to produce a program, the program having a virtual language portion and a machine language portion respectively. When the program is executed, the virtual language portion of the program is translated into machine language instructions, and the machine language portion of the program is directly executed, such that the application-specific microprocessor executes both the DSP-like instructions and the microcontroller-like instructions.

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.

Abstract: A virtual memory for a computer system is provided that is portable between different central processing unit (CPU) types. The system includes a high level virtual memory (HLVM) having high level program codes that are independent of a specific CPU type, a low memory vector table (LMVT) coupled to the HLVM that dispatches a call in response to a high level program code received from the HLVM, and a low level virtual memory (LLVM) coupled to the LMVT having low level program codes that depend on a specific CPU type. The method of operating the virtual memory system includes the steps of generating a high level virtual memory (HLVM) instruction from high level program codes that are independent of specific CPU characteristics and receiving the HLVM instruction in a low memory vector table (LMVT).

Abstract: A plurality of processing stages interposed between an input and an output of a system including a pipeline machine interconnect for conveyance of tokens along the pipeline. Control and or data tokens in the form of universal adaptation units interface with all of the stages in the pipeline and alternatively interact with selected stages in the pipeline so that the processing stages in the pipeline are afforded enhanced flexibility in configuration and processing. In one embodiment of the system, the stages accept a data stream having portions encoded according to respectively different video formats. At least one of the stages includes circuitry for generating signals to indicate an end-of-picture data decoding. The stage includes state machine logic that is responsive to the generated signals for effecting an end of picture data decoding by clearing the pipeline.

Abstract: In the data driven computer system (FIG. 4, FIG. 7), data are transferred between data driven computers (1, 11, 12, 21, 22, 24, 25, . . . , and n), with instruction code (code) and identification numbers to identify data for arithmetic operation. Calculation results obtained by arithmetic units (111, 121, 21n, 22n, 24n, 25n, . . . , and nn) are stored in a data field (data). In parallel, an instruction rewriting units (3, 115, 125, 134, 211, 221, 241, 251, . . . , and nl) calculates an instruction code to be used in a following process and then rewrite a current instruction code with the calculated one without any execution of a microprocessor (14) or other controller. The result of the arithmetic operation is transferred to a peripheral device (16) or the microprocessor (14) through the data driven computer (13, 23).

Abstract: An instruction fetch unit 10 issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline 14. The instruction fetch unit 10 also issues a normal ALU operating instruction to a second pipeline 16. Occasionally, a wide ALU operating instruction using both a first integer unit 20 and a second integer unit 24 to the first pipeline 14 while a normal ALU operating instruction using the second integer unit 24 to the second pipeline 16. In this case, if the normal ALU operating instruction is earlier, then the normal ALU operating instruction is executed preferentially. If the wide ALU operating instruction is earlier, then the wide ALU operating instruction is executed preferentially.

Abstract: An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the variety of processes, and a second processor capable of executing a portion of or the entire instruction set, the second processor being capable of executing a part of the instruction set corresponding to the specific process more efficiently than the first processor, wherein the second processor executes the specific process whereas the first processor executes the other processes. Accordingly, the information-processing device can execute a variety of instructions efficiently.

Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.

Abstract: Accordingly, a prefetch instruction mechanism is desired for implementing a prefetch instruction which is non-faulting, non-blocking, and non-modifying of architectural register state. Advantageously, a prefetch mechanism described herein is provided largely without the addition of substantial complexity to a load execution unit. In one embodiment, the non-faulting attribute of the prefetch mechanism is provided though use of the vector decode supplied Op sequence that activates an alternate exception handler. The non-modifying of architectural register state attribute is provided (in an exemplary embodiment) by first decoding a PREFETCH instruction to an Op sequence targeting a scratch register wherein the scratch register has scope limited to the Op sequence corresponding to the PREFETCH instruction.

Abstract: A computer program product, method and apparatus for utilizing common prefix codes in computing instructions so as to reduce the number instructions required to perform identical operations for varying operand sizes. In one form, the common prefix code is appended as the higher order portion of the instruction word to form a second series of instructions. These computing instructions may be utilized in conjunction with a flag register, which, in one application, designates which series of instructions to use; either the original instructions or the modified instructions containing the common prefix. In another application, the flag register designates which register or memory should be used to store the operands and the associated results. Through the use of common prefix codes and the flag register, operands of various sizes can be efficiently manipulated through a simplified scheme of instructions.

Abstract: An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions of the stack based computing system are separated into different instruction types. Certain combinations of instruction types can be combined into instruction groups for concurrent execution. The execution unit includes an instruction folding unit that is configured to determine the instruction type of instructions and combine the instructions into instruction groups, and an instruction pipeline that is configured to process both instructions and instruction groups. In one embodiment, the instruction folding unit includes: an instruction type estimator which estimates the instruction types of various instructions; an instruction selector, which selects the instruction types from the estimated instruction types; and a folding logic circuit which combines the instructions into instruction groups.

Abstract: A compression scheme for program executables that run in a reduced instruction set computer (RISC) architecture such as the PowerPC is disclosed. The method and system utilize scope-based compression for increasing the effectiveness of conventional compression with respect to register and literal encoding. First, discernible patterns are determined by exploiting instruction semantics and conventions that compilers adopt in register and literal usage. Additional conventions may also be set for register usage to facilitate compression. Using this information, separate scopes are created such that in each scope there is a more prevalent usage of a limited set of registers or literal value ranges, or there is an easily discernible pattern of register or literal usage. Each scope then is compressed separately by a conventional compressor.

Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.

Abstract: The number of opcode functions exceeds the number of opcodes available by virtue of a technique employing dual function opcodes wherein the second function is executed when a particular resolving flag is put into a set state and otherwise the first function is executed. Furthermore, a generic push opcode and a generic pop opcode are employed without any register pointer designations so that a series of push operations can be performed using a single opcode and a series of pop operations can be performed using a single opcode. The utility of the processor is further enhanced by incorporating a series of handler opcodes that permits simulating on the instruction set of the processor a program designed for a different instruction set. A special simulator opcode called a jump vector opcode is employed to control the operation of reading in the target opcode, applying an algorithm that provides the host processor address for corresponding handler opcodes and jumping to those addresses.

Abstract: A slave device, connected directly to a system bus, which system bus requests the execution of a complex communication protocol, is controlled by another device, connected to the system bus, which identifies the slave device as the target of a transaction on the system bus, executes the communication protocol and sends to the slave device through an auxiliary interface a first identification signal, a second signal for instructing execution of the transaction, and receives from the slave device, through the auxiliary interface, a transaction executed signal. In this way the interface logic of the slave device is reduced to the minimum since the slave device is not required to execute the communication protocol.

Abstract: A superscalar complex instruction set computer (“CISC”) processor having a reduced instruction set computer (“RISC”) superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes “pre-decode” information, a byte queue which is a queue of aligned instruction and pre-decode information of the “predicted executed” state, and an instruction decoder which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue and determines the number of possible x86 instruction dispatch for shifting the byte que. The instruction decoder includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs.

Abstract: A method and apparatus for reducing the number of opcodes required in a computer architecture using an operation class code and an operation selector code. A processor contains a fetch unit which fetches instructions to be executed by the processor. An instruction may conform to an instruction format which includes a number of fields that specify an operation class code, an operation selector code, and one or more operands. The processor also contains a decoder which uses the operation class code to generate a single execution flow that is capable of executing a class of similar operations. The single execution flow, in the form of execution control information, is sent to an execution unit along with the associated operands. The operation selector code is also passed to the execution unit. The execution unit performs the specific operation identified by the operation selector code and execution control information.