Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: A system, method and medium performing data operations according to a merged multi-threading and out-of-order scheme. According to the method, at least one instruction is decoded, a thread of an instruction is read based on the decoding result, and a predetermined operation is performed on each of a plurality of threads, including the read thread, in each of a plurality of pipeline stages in an out-of-order manner, based on the decoding result. Accordingly, it is possible to guarantee high throughput while maintaining a small number of threads.

Abstract: A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.

Abstract: Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a present instruction, and at least one subset instruction decoder configured to determine whether the present instruction potentially needs a register. A memory element is also included and is configured to hold data from a previous instruction. A selector is included and configured to output either the previous instruction or the decoded present instruction, based on the subset instruction decoder.

Abstract: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue.

Abstract: In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

Abstract: An VLIW instruction mechanism is described which accesses multiple slot instructions for execution to achieve high levels of selectable parallelism and to make improvements to code density. To this end, the VLIW instruction mechanism includes a short instruction word (SIW) register for holding an SIW. The SIW includes an indication of a slot instruction to execute and a dynamic slot instruction operand which is used by the slot instruction to execute. Further, the VLIW instruction mechanism includes a register for holding slot instructions which are retrieved from VLIW memory. The retrieved slot instructions include a stored operand which is used when executing the retrieved slot instruction. The VLIW instruction mechanism further includes a controller and an execution unit. The controller selects which of the operands are utilized with the retrieved slot instructions. The execution unit executes the retrieved slot instruction with the selected operand.

Abstract: An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the output from the instruction buffer; an instruction decompression section for decompressing the output from the first selector into an original instruction; a second selector for outputting the output from the instruction buffer when no compressed instruction is stored in the instruction buffer and outputting the output from the instruction decompression section otherwise; an instruction decoding section for outputting a signal indicating presence/absence of instruction branching based on a result of decoding the output from the selector; and a control section for instructing the first selector to select a predetermined one of the received signals when the signal from the instruction decoding section indicates that there is instruction branching.

Abstract: The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word length select for indicating a present instruction's word length, and a first selector for routing the instruction into the 16-bit decoder when the present instruction is 16-bits long. The first selector is also configured to route a previous instruction into the 16-bit decoder, maintaining the 16-bit decoder's present state. A second selector is configured to route the instruction into the 32-bit decoder when the present instruction is 32-bits long. The second selector is also configured to route a past instruction into the 32-bit decoder to maintain the 32-bit decoder's present state.

Abstract: In one embodiment, the invention provides a method for examining information about branch instructions. A method, comprising: examining information about branch instructions that reach a write-back stage of processing within a processor, defining a plurality of streams based on the examining, wherein each stream comprises a sequence of basic blocks in which only a last block in the sequence ends in a branch instruction, the execution of which causes program flow to branch, the remaining basic blocks in the stream each ending in a branch instruction, the execution of which does not cause program flow to branch.

Abstract: Conditional branch bytecodes are processed by a Virtual Machine Interpreter (VMI) hardware accelerator that utilizes a branch prediction scheme to determine whether to speculatively process bytecodes while waiting for the CPU to return a condition control variable. The VMI assumes the branch condition will be fulfilled if a conditional branch bytecode calls for a backward jump and that the branch condition will not be fulfilled if a conditional branch bytecode calls for a forward jump. Alternatively, the VMI makes an assumption only if a conditional branch bytecode calls for a backward jump or the VMI assumes that the branch condition will be fulfilled whenever it processes a conditional branch bytecode. The VMI only speculatively processes bytecodes that are easily reversible, and suspends speculative processing of bytecodes upon encountering a bytecode that is not easily reversible. If a VMI assumption is invalidated, any speculatively processed bytecodes are reversed.

Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.

Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilising a 12-bit offset field but with a fixed addressing mode and a second form utilising a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.

Abstract: A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of the intermediate results must avoid plausible wrong results. A programmable feature allows the instruction decoder to provide plural answers, including plausible wrong answers. Instruction output selection logic selects a predetermined buffer, and this permits further microprocessor operation with the correct intermediate result.

Abstract: A method and apparatus for utilizing multiple microcode flow synonyms or hardware flow synonyms for an instruction is disclosed. In one embodiment, a microcode synonym is created for execution on two or more execution units of differing types. One microcode synonym may be chosen for execution depending upon the availability status of the execution units. In another embodiment, several microcode synonyms may be chosen for execution. The results of the first microcode synonym to complete execution may be retired. If the results of execution of two microcode synonyms do not match, a fault exception may be raised.

Abstract: A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes second decoder logic capable of decoding a plurality of encoded instructions comprising a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic. Finally, the processor includes decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic. In operation, the decoder control logic operates such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode. Likewise, when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode.

Abstract: An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.

Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.

Abstract: A VoiceXML interpreting system and method including a VoiceXML Interpreter. The VoiceXML interpreter includes a Fetcher operative to retrieve documents, a compiler operative to compile documents retrieved by the Fetcher and a cache which stores compiled documents compiled by the compiler.

Abstract: Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus, and translates each of the macro instructions into associated native instructions for execution. If a first form of a first macro instruction is retrieved, the instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register. The bypass logic is coupled to the instruction translation logic.

Abstract: Unhandled operation of a program instruction of a first instruction set, such as a Java bytecode, is detected. Instead of invoking a mechanism for directly dealing with that unhandled operation, one or more instructions from a second instruction set, such as ARM instructions, are instead used to emulate the instruction that was subject to the unhandled operation. If these instructions of the second instruction set are also subject to unhandled operation, then the mechanisms for dealing with unhandled operation within that second instruction set may be invoked to repair that operation. This approach is well suited to dealing with unhandled operation of variable length instructions being interpreted with a processor core having a native fixed length instruction set. In particular, prefetch aborts and unhandled floating point operations may be conveniently dealt with in this way.

Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.

Abstract: A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1: i+1˜i+4; F2: i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats F1, F2), and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1˜i+3), the opcodes of the first operation (101) in the two external formats are identical.

Abstract: The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.

Abstract: A system and method for handling complex instructions includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the Jump instruction if it was.

Abstract: The present invention provides an apparatus and method for storing instruction set information. The apparatus comprises a processing circuit for executing processing instructions from any of a plurality of instruction sets of processing instructions, each processing instruction being specified by an instruction address identifying that processing instruction's location in memory. A different number of instruction address bits need to be specified in the instruction address for processing instructions in different instruction sets. The apparatus further comprises encoding logic for encoding an instruction address with an indication of the instruction set corresponding to that instruction to generate an n-bit encoded instruction address.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set.

Abstract: Program instructions in the form of Java bytecodes may be subject to fixed mappings to processing operations or programmable mappings to processing operations. A system is provided with a fixed mapping hardware interpreter, a programmable mapping hardware interpreter and a software interpreter. The fixed mapping hardware interpreter is able to provide high speed interpretation of the common and simple bytecodes. The programmable mapping hardware interpreter is able to provide high speed interpretation of the simple and performance critical programmable bytecodes with the remaining bytecodes and more complicated bytecodes being handled by the software interpreter.

Abstract: A hardware Java™ accelerator is provided to implement portions of the Java™ virtual machine in hardware in order to accelerate the operation of the system on Java™ bytecodes. The Java™ hardware accelerator preferably includes Java™ bytecode translation into native CPU instructions. The combination of the Java™ hardware accelerator and a CPU provides a embedded solution which results in an inexpensive system to run Java™ programs for use in commercial appliances.

Abstract: The present invention provides a non-copy shared stack and register set device and a dual language processor structure using the same, which achieve non-copy data sharing by controlling a selector and the stack pointer of a data stack. The selector is connected to each item of the data stack and a register of the register set, such that, when the register set requires to exchange data with the data stack, the selector is controlled and the stack pointer is updated thereby the selector is switched to make the stack item pointed by the stack pointer communicate with the register.

Abstract: A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer.

Abstract: A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set.

Abstract: There is disclosed a data processor containing an instruction issue unit that efficiently transfers instruction bundles from a cache to an instruction pipeline. The data processor comprises 1) an instruction pipeline comprising N processing stages; and 2) an instruction issue unit for fetching into the instruction pipeline instructions fetched from the instruction cache, each of the fetched instructions comprising from one to S syllables.

Abstract: A data processing apparatus includes a processor core having a bank of registers. The bank of registers include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core. The instruction translator has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: An apparatus comprising a processor and a translator circuit. The processor may (i) comprise a number of internal registers and (ii) be configured to manipulate contents of the internal registers in response to instruction codes of a first instruction set. The translator circuit may be configured to implement a stack using one or more of the internal registers of the processor.

Abstract: In one embodiment, a processor receives coded instructions and converts the instructions to a second code prior to execution. The processor may be a digital signal processor. A decoder in the processor determines the destination of the instructions and performs decoding functions based on the destination.

Abstract: A data processing system supports execution of both native instructions and Java bytecodes using a hardware executer for the Java bytecodes where possible and a software instruction interpreter for the Java bytecodes where these are not supported by the hardware. The sequences of native instructions 26 within the software instruction interpreter that perform the processing for the Java bytecodes being interpreted terminate within a sequence terminating instruction BXJ that acts differently depending upon whether or not an enabled hardware executer 6 is detected to be present. If an enabled hardware executer is detected as present, then the execution of the next Java bytecode is attempted with this. If an active hardware executer is not present, then the next Java bytecode is passed directly to the software instruction interpreter.

Abstract: Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.

Abstract: To improve the execution performance of a program which makes indirect array reference by performing data prefetching also on an indirect reference array while reducing an instruction overhead, locality in data reference which cannot be detected by a conventional compiler is enabled to be detected by a user instruction or analysis by a compiler on the basis of a tendency that values of indices in an indirect reference array monotonously increase or decrease. By using the information, issuing of redundant prefetch instructions is suppressed, and data prefetching is enabled to be performed also on an indirect reference array.

Abstract: A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The data processor is a VLIW (Very Long Instruction Word) system that can execute a plurality of operations in parallel, and specify the execution sequence of the operations. It can assign a plurality of operations to the same operation code, and the operations that are executed in a second or subsequent sequence are limited to only predetermined operations among the plurality of operations.

Abstract: An interpreter invocation mechanism for switching between execution of native instruction words to interpreted instruction words uses a subroutine call instruction to start execution of the interpreter. The return address of the subroutine call instruction is used as an address pointer to the start of the interpreted code. The interpreted code may terminate with an Exit instruction whereupon normal native code execution resumes using the instruction at the immediately following memory address or alternatively with a Return instruction that recovers a return address previously stored to stack memory.

Abstract: A data processing system is provided with a first mechanism for executing instructions of a first instruction set and a second mechanism for executing instructions of a second instruction set. The second mechanism requires configuration data 310, 312, 314, 316 which may or may not be valid. Programs that use the second execution mechanism are responsible for the writing of its own configuration data with this being indicated as being necessary by a configuration valid indicator CV set to indicate that the configuration is invalid by the operating system 300 upon detecting an appropriate process switch.

Abstract: A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the current execution mode. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath shared by both execution modes (base and migrant). The two execution modes have separate control logic. Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet. Code processed by the migrant and base decode pipelines produces machine words that are selected by a multiplexer. The multiplexer is controlled by the operating mode bound to the fetch packet that produced the machine word.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.