Abstract: A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily stores an instruction that includes at least one of: an operational code, destination information, and source information. The instruction decoder is operably coupled to interpret the instruction to identify the arithmetic logic unit and/or the finite field arithmetic unit to perform the operational code of the corresponding instruction. The instruction decoder then identifies at least one destination location within the digital storage device based on the destination information contained within the corresponding instruction. The instruction decoder then identifies at least one source location within the digital storage device based on the source information of the corresponding instruction.

Abstract: An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.

Abstract: A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.

Abstract: A numerical arithmetic circuit 50 executes an arithmetic instruction according to an instruction read out of a program memory 10 and then stores the arithmetic result into a register group 40 via an input switcher 70. A mode register 20 is associated with the register group 40. A flag designating whether or not a predetermined logic operation is executed to the arithmetic result is set to the mode register 20. When the register group 40 stores the arithmetic result, the mode register 20 corresponding to the register being the register group 40 designated on the program is referred as a register which stores the arithmetic result. Thus, a predetermined arithmetic and logic operation to the arithmetic result is controlled.

Abstract: A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.

Abstract: Method, apparatus, and program means for rearranging data between multiple registers. The method of one embodiment comprises shuffling first set of packed data from a first source based on a first set of masks to produce a first set of shuffled data. The first set of masks is to include a first plurality of control entries to set designated data element positions in the first set of shuffled data to zero. A second packed data from a second source is shuffled based on a second set of masks to produce a second set of shuffled data. The second set of masks includes a second plurality of control entries to set to zero data element positions in the second set of shuffled data opposite to said designated data element positions in the first set of shuffled data. The first set of shuffled data and said second set of shuffled data are merged together to form a packed data resultant.

Abstract: Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table having a set of L data elements. A determination of whether the table fits into a single register is made. A data lookup into the table is performed with a packed data shuffle operation if the determination indicates that the table does fit into a single register. The table is divided into a plurality of sections if the table does not fit into a single register. Each of the sections is sized to fit into a single register. A plurality of packed data shuffle operations are executed on the plurality of sections to look up data in the table.

Abstract: A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including special relocations that have a type field for identifying the nature of a function to be implemented by the special relocation. The function is selected from a plurality of arithmetic and logical functions. A method of preparing the executed program includes reading the special relocations, determining from the type field the nature of the function to be implemented, carrying out the selected arithmetic or logical function to generate a result value and using the result value in a subsequent special relocation operation. The method may be executed by a linker having a relocation module for reading the special locations and carrying out the relocation operations.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.

Abstract: A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.

Abstract: In a wide instruction architecture processor device, an instruction execution unit provides integer and floating point capability within its constituent arithmetic logic channels. Results are written out to a register file where integer results are given higher priority over floating point results, which are buffered, in order to increase integer operation throughput. By buffering floating point results and giving priority to integer results, fewer register file write ports are needed. A bypass mechanism allows access to floating point results during their pendency in the buffer. Dual serially-configured integer units are configured to enable two-operand and combined (three-operand) instructions to be delivered to an arithmetic and logic channel at every clock cycle. Similarly, dual parallel pipelined floating point units are configured to permit two-operand and combined (three-operand) floating point instructions to be delivered to an arithmetic and logic channel on each clock cycle.

Abstract: Embodiments of the present invention provide a method and structure for performing data element manipulation and preprocessing on a microprocessor architecture that supports Single Instruction Multiple Data (SIMD) operations. According to the principles of the present invention, a microprocessor data manipulation matrix module provides inherent data manipulation functionality to SIMD instructions. The data manipulation matrix module permits SIMD instructions themselves to direct and manage any necessary operand data element preprocessing, such as data element alignment. By the present invention, separate SIMD data element manipulation of the prior art is superfluous.

Abstract: A data processing system and method that provides two processes, checkpointing and compute point propagation, and permits a continuous flow of data processing by allowing each process to (1) return to normal operation after checkpointing or (2) respond to receipt of a compute point indicator, independently of the time required by other processes for similar responsive actions. Checkpointing makes use of a command message from a checkpoint processor that sequentially propagates through a process stage from data sources through processes to data sinks, triggering each process to checkpoint its state and then pass on a checkpointing message to connected “downstream” processes. A compute point indicator marks blocks of records that should be processed as a group within each process. A compute point indicator is triggered and sequentially propagates through a process stage from data sources through processes to data sinks without external control.

Abstract: A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation of the dyadic DSP instruction with data paths of each selectively configured to execute the main operation and the sub operation of the dyadic DSP instruction. A voice and data communication system has a first gateway and a second gateway coupled to a packetized network, each gateway having a network interface including the dyadic DSP instruction processor. An application specific signal processor with a signal processor having a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation with multiplexers coupled to the first DSP functional block and the second DSP functional block to selectively configure data paths thereto.

Abstract: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

Abstract: The present invention relates to a method and system for providing a combined addition/subtraction instruction with a flexible and dynamic source selection mechanism. Specifically, a method can select a plurality of source operands from a plurality of operands, and set a polarity of each of the plurality of source operands to negative, if a value associated with the source operand is set to require negation of the source operand. The method also can add selected pairs of the plurality of source operands in predetermined orders to obtain a plurality of addition results and subtract the selected pairs of the plurality of source operands in the predetermined orders to obtain a plurality of subtraction results. The method further can output the plurality of addition results and the plurality of subtraction results.

Abstract: The present invention relates to a method and system for providing sine and cosine value pairs in a processor. The method includes decoding a sine and cosine instruction having a predetermined source angle and generating an index value for a sine cosine table (SCT) using a sine cosine control register (SCCR). The method also includes generating a plurality of quadrant bits using the SCCR, reading a sine and a cosine value pair from the SCT using the index value, and adjusting a sign of each value of the sine and the cosine value pair using the plurality of quadrant bits, if necessary. The method further includes incrementing the SCCR, if the SCCR is to be incremented, executing the sine and cosine instruction using the sine and cosine value pair, and outputting at least one result.

Abstract: The present invention relates to a method and system for on-the-fly precision adjustment of packed data. Specifically, on-the-fly precision adjustment of packed data includes operating on data that may be either packed or unpacked data. The method and system also may store at least one packed or unpacked result from the operated on data. In accordance with an embodiment of the present invention, the method includes decoding an instruction, determining the instruction is to be executed using on-the-fly precision adjustment of packed data, executing the instruction using on-the-fly precision adjustment of packed data, and outputting at least one result from the executed instruction.

Abstract: A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field programmable array. The circuit receives an external instruction stream which provides a first set of instruction values, and has a memory which contains a second set of instruction values. Two or more outputs provide instruction streams to the processing device. The circuit has a control input in the form of a mask which causes a selection means to allocate bits from the first and second sets of instruction values to different instruction streams to the processing device.

Abstract: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

Abstract: A functional unit is described for selectively performing a number of types of bit rearrangement operations, including a generalized bit reverse operation and a generalized shuffle/unshuffle operation, and in addition left and right unsigned shift operations and an arithmetic shift right operation. The functional unit includes a shifter array and a control signal generator. The shifter array includes a plurality of selector circuits arrayed in a number of stages for shifting bits of an input data word in accordance with control signals, the output of the last stage corresponding to a rearranged output data word. The control signal generator generates control signals in response to rearrangement operation type and pattern information.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in parallel by a SIMD arithmetic unit. A selector for adding an operation for interchanging multiple outputs of a SIMD arithmetic unit is added to a data path. A register file is divided in accordance with the output bit fields of the SIMD arithmetic unit. A means of specifying multiple registers as a SIMD instruction's output operand is added. Therefore, part of the output results of arithmetic operations performed in parallel by the SIMD arithmetic unit can be stored in a register providing the input for another arithmetic operation. Software pipelining is rendered achievable in this manner.

Abstract: The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU.

Abstract: The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) and attaches a dual-MAC coprocessor (MAC3), (MAC4) onto it in a unique way to achieve a significant increase in processing capability.

Abstract: A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.

Abstract: A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central processing unit having a converter unit and a set of conversion registers. The load/store instructions having data requiring conversion include an index field for identifying one of the conversion registers. Each one of the conversion registers includes information on the type of conversion required and any scaling factors to be applied. Upon receiving one of these instructions, the converter uses the identified conversion register to perform the conversion and stores the converted data into the corresponding register or memory location.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to he saturation signal.

Abstract: A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

Abstract: The objective of the invention is to detect a characteristic in a technical system with reference to model checking. A comparison is made, involving the coordination of several comparative processes, whereby the comparison leads to a result. The comparison is terminated as soon as a comparative process proves that the characteristic is present or not in the appropriate system.

Abstract: A method, apparatus, and article of manufacture for the inclusion of extended relocation types and operations performed thereon in a relocation directory within an object module or load module. The relocation directory includes a field to describe the referenced item relocated into the address constant location within the text, which may be a numerical value, symbol, address, set of data or instructions or symbol. The relocation directory further includes a field to describe the operation performed on the referenced item and the present contents of the address constant, which includes operations such as subtraction, addition, division, multiplication, logical AND, logical OR, shifting, logical XOR, and moving. The result of the operation performed on the referenced item and the content of the address constant is relocated into the address constant location.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.

Abstract: A data processing device comprises an instruction decoding unit for decoding a code of either a division instruction or a remainder instruction applied thereto, the instruction code having a size field for storing data size information. When a control unit receives a decoded result from the instruction decoding unit, the decoded result indicating the data size information stored in the size field of the instruction code, it presets a number of times that one loop iteration comprised of steps required for executing either the division instruction or the remainder instruction is to be carried out, based on the data size information. An ALU disposed within an arithmetic unit performs the loop iteration for either the division instruction or the remainder instruction only the number of times preset by the control unit.

Abstract: A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of operands of the instruction set architecture. The data typer and aligner is selectively configued to align and select one of more sets of data bits from one or more data buses as operands for functional blocks of the signal processor in response to fields of an instruction.

Abstract: The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse Response (FIR) filtering with a downsampling (or upsampling) option, row/column Discrete Cosine Transform (DCT)/Inverse Discrete Cosine Transform (IDCT), and generic algebraic functions. The architecture is called IPP, which stands for image processing peripheral, and consists of 8 hardware multiply-accumulate units connected in parallel and routed and multiplexed together. The architecture can be dependent upon a Direct Memory Access (DMA) controller to retrieve and write back data from/to DSP memory without intervention from the DSP core. The DSP can set up the DMA transfer and IPP/DMA synchronization in advance, then go on its own processing task. Alternatively, the DSP can perform the data transfers and synchronization itself by synchronizing with the IPP architecture on these transfers.

Abstract: A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.

Abstract: An instruction set for control of an audio signal processor that allows for a high degree of flexibility in generating desired sound effects. The instruction set serves as a multi-functional instruction base upon which other specialized sound effects can be constructed.

Abstract: A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length which identifies a test register holding a plurality of test bits greater than the predetermined bit length. The test register holds a test code defining a test condition. The test condition is checked against at least one condition code and the operation is selectively carried out in dependence on whether the condition code satisfies the test condition. In one embodiment, the condition codes are set on a lane-by-lane basis for packed operands.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: A high speed programmable ER computational engine that is based on a micro-programmed control unit and a register intensive pipelined datapath that removes the need for having an instruction set interpreter includes a data path unit operably coupled to directly receive datapath control words from a control unit. The control unit includes memory and an address unit, where the memory stores the data path control words, which relate to a computational algorithm. The address unit receives input (e.g., begin an ER calculation) from an external source, where the input causes at least some of the data path control words to be retrieved from the memory. The data path unit includes a pair of register files, a plurality of floating point units, and data flow coupling. The pair of register files operate in a double buffering manner such that one of the register files is receiving parameters (e.g., data rate information of a connection) for subsequent computation while the other is used for a current computation.

Abstract: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

Abstract: An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

Abstract: A processor (12) uses an architecture having a plurality of redundant state machines (86, 90) and a new instruction format (30) to increase efficiency of the utilization of operational circuitry, such as a multiply accumulate unit MAC (52). Thus the processor (12) can switch contexts or channels without incurring any dead or wasted cycles for the MAC unit (52).

Abstract: An adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of the first numerical value is described.