Abstract: Methods and systems for performance measurements of a program are provided. An execution trace of the program may be captured and stored. The stored execution trace may be replayed in an offline mode. Performance measurements for the program may be determined based on the replaying of the execution trace in the offline mode.

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.

Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

Abstract: An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is 5 responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. Processing circuitry is then used to perform a vector memory access operation in order to access in memory a plurality of data values at addresses determined from an address vector operand 10 comprising a plurality of address elements. The address vector operand is provided in a specified vector register of the vector register set, such that the plurality of elements of the vector stored in that specified vector register form the plurality of address elements.

Abstract: Performing a rooted-v collective operation by an operational group of compute nodes in a parallel computer includes: upon encountering a rooted-v collection operation during execution, identifying, by a root node of an operational group of compute nodes, a count to use for the selection of a collective algorithm for effecting the rooted-v collective operation; broadcasting, by the root node to the other computer nodes in the operational group, an active message, wherein the active message includes the identified count to use for the selection of the collective algorithm; and selecting, by all the compute nodes of the operational group based on the identified count, a same collective algorithm to effect the rooted-v collective operation; and executing the rooted-v collective operation by all compute nodes of the operational group using the selected algorithm.

Abstract: A electronic system includes: a cluster manager configured to: divide a user program into a group of parallel execution tasks, and generate shuffling metadata to map intermediate data and processed data from the parallel execution tasks; a shuffling cluster node, coupled to the cluster manager, configured to: store the shuffling metadata by an in-storage computer (ISC), and incrementally shuffle each of the sub-packets of the intermediate data and the processed data, by the ISC, based on the shuffling metadata when the parallel execution task is in process; and a local storage, coupled to the shuffling cluster node and mapped through the shuffling metadata, for receiving the sub-packets of the processed data from the shuffling cluster node.

Abstract: A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software includes software prefetch instructions, using a hardware data prefetcher, and, accessing the software prefetch instructions if the software includes software prefetch instructions. Using the hardware data prefetcher, weak stream software data and instruction prefetching operations are executed based on the software prefetch instructions, free of training operations.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: An exemplary method for detecting one or more anomalies in a system includes building a temporal causality graph describing functional relationship among local components in normal period; applying the causality graph as a propagation template to predict a system status by iteratively applying current system event signatures; and detecting the one or more anomalies of the system by examining related patterns on the template causality graph that specifies normal system behaviors. The system can align event patterns on the causality graph to determine an anomaly score.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: Corruption of call stacks is detected by using guard words placed in the call stacks. A determination is made that a caller routine is to facilitate detection of corruption of stacks. Based on the determination, a store of a guard word in a stack frame of the caller routine is provided in the caller routine. The stored guard word is then used to detect corruption of the stack frame.

Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data to an execution unit, where the first data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.

Abstract: A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.

Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Abstract: The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse map table (RMT) and a separate guest accessed pages table (GAPT) for each virtual machine. The RMT has a plurality of entries, each entry including information for identifying a virtual machine that is permitted to access an associated page of data in a memory. Each GAPT has a record of pages being accessed by a corresponding virtual machine. During operation, a table walker receives a request from a given virtual machine to translate a guest physical address to a system physical address. The table walker checks at least one of the RMT and a corresponding GAPT to determine whether the given virtual machine has access to a corresponding page. If not, the table walker terminates the translating. Otherwise, the table walker completes the translating.

Abstract: A method includes determining that an operation should be performed to restore 80 bits stored in memory for an 80 bit register of a guest architecture on a host having 64-bit registers. The method further includes storing 64 bits from the 80 bits in a host register. The method further includes storing the remaining 16 bits from 80 bits in supplemental memory storage. The method further includes identifying a floating point operation that should be performed to operate on the 80-bit register for the guest architecture. As a result, the method further includes using the 64 bits in the host register and the remaining 16 bits stored in memory in a supplemental memory storage to translate a floating point number represented by the 80 bits to a 64-bit floating point number and store the 64-bit floating point number in the host register.

Abstract: A method of exchanging data in a real-time operating system, between a primary core and a secondary core in a multi-core processor, includes executing a primary path via the primary core and executing a secondary path via the secondary core. The primary path is configured to be a relatively faster processing task and the secondary path is configured to be a relatively slower processing task. The method includes devising a freeze in process flag to have a respective flag status set and cleared by the primary path. The method includes devising a data frozen flag to have a respective flag status set and cleared by both the primary and the secondary paths. A component that is operatively connected to the multi-core processor may be controlled based at least partially on a difference between primary and secondary sets of calculations executed by the primary and secondary cores, respectively.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: A technique suppresses the occurrence of stalling caused by data dependency other than register dependency in an out-of-order processor. A stall reducing program includes a handler for detecting a stall occurring during execution of execution code using a performance monitoring unit, and identifying, based on dependencies, a second instruction on which a first instruction is data dependent, the stall based on this dependency; a profiler registering the second instruction as profile information; and an optimization module for inserting a thread yield instruction in the appropriate position inside the execution code or original code file based on the profile information, and outputting the optimized execution code.

Abstract: Techniques are disclosed for implementing a unified partitioning scheme within distributed database systems to allow a table to be horizontally partitioned and those partitions stored on and serviced by a storage group. A storage group is a subset of storage manager (SM) nodes, and each SM node is configured to persist database data in durable storage. The distributed database system assigns each storage group to a subset of SM nodes. The distributed database system can address each storage group using a symbolic mapping that allows transactions to identify a particular storage group, and to direct read and write operations to a subset of SM nodes servicing that storage group. An administrator can update this mapping on-the-fly to cause the distributed database system to dynamically adjust an implemented partitioning scheme without necessarily interrupting on-going database operations.

Abstract: A lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed, as well as a barrier request that requests ordering of memory access requests prior to and after the barrier request. The barrier request precedes a copy-type request and a paste-type request of the memory move in program order. Prior to completion of processing of the barrier request, the lower level cache allocates first and second state machines to service the copy-type and paste-type requests. The first state machine speculatively reads a data granule identified by a source real address of the copy-type request into a non-architected buffer. After processing of the barrier request is complete, the second state machine writes the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.

Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.

Abstract: A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.

Abstract: External references are resolved in a software compiling and linking environment by identifying a group of related external references and by processing the group of external references until a stopping condition is satisfied. The external references are processed by selecting a next external reference from the group of external references as a current external reference and by resolving the current external reference with a matching definition if a matching definition for the current external reference exists. The stopping condition is designated as being satisfied if either the selected external reference is resolved, or if each external reference in the group of external references has been selected.

Abstract: An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

Abstract: External references are resolved in a software compiling and linking environment by identifying a group of related external references and by processing the group of external references until a stopping condition is satisfied. The external references are processed by selecting a next external reference from the group of external references as a current external reference and by resolving the current external reference with a matching definition if a matching definition for the current external reference exists. The stopping condition is designated as being satisfied if either the selected external reference is resolved, or if each external reference in the group of external references has been selected.

Abstract: A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor.

Abstract: Methods and apparatus for efficient loading of data from memory to registers and storing of data from registers to memory are described. In an embodiment, a processor comprises a data structure to which addresses which are used for load operations are pushed. Instead of independently generating addresses for a store operation, addresses are popped from the data structure and either used directly or an optional offset may first be applied to the popped address. In this way, a store operation and a load operation may be performed in parallel because they do not both require use of the logic which independently generates addresses for load/store operations. In various examples, the data structure is a FIFO structure.

Abstract: A batching module that prepares a plurality of blocked expressions for batch evaluation. The plurality of blocked expressions comprises a current expression in a particular stack in a blocked state. The batching module divides the plurality of blocked expressions into one or more partitions. For each particular partition of the one or more partitions, a single batch processing call is dispatched to an application server to perform a batch evaluation.

Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory.

Abstract: An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

Abstract: A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.

Abstract: A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A transaction is detected. The transaction has a begin-transaction indication and an end-transaction indication. If it is determined that the begin-transaction indication is not a no-speculation indication, then the transaction is processed.

Abstract: A transaction is detected. The transaction has a begin-transaction indication and an end-transaction indication. If it is determined that the begin-transaction indication is not a no-speculation indication, then the transaction is processed.

Abstract: Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.

Abstract: Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Abstract: In one embodiment the invention provides a method. The method includes invoking, via an application, a call of a command line utility; providing, via the application, an identifier in the call of the command line utility, wherein the identifier comprises an operating system controlled memory location; storing output from the command line utility in operating system shared memory at the operating system controlled memory location identified by the identifier; and retrieving, by the application, the command line utility output from the operating system shared memory at the operating system controlled memory location identified by the identifier.

Abstract: A task scheduling method is disclosed, where each processor core is programmed with a short list of priorities, each associated with a minimum response time. The minimum response times for adjacent priorities are different by at least one order of magnitude. Each process is assigned a priority based on how its expected response time compares with the minimum response times of the priorities. Lower priorities may be assigned a timeslice period that is a fraction of the minimum response time. Also disclosed is a task division method of dividing a complex task into multiple tasks is; one of the tasks is an input gathering authority task having a higher priority, and it provides inputs to the other tasks which have a lower priority. A method that permits orderly shutdown or scaling back of task activities in case of resource emergencies is also described.

Abstract: Administering VMs in a distributed computing environment that includes hosts that execute a VMM, with each VMM supporting execution of one or more VMs, includes: assigning the VMMs to a logical tree topology with one as a root; and executing, by the VMMs of the tree topology, a reduce operation, including: sending, by the root VMM to each of other VMMs of the tree topology, a request for an instance of a particular VM; pausing, by each of the other VMMs, the requested instance of the particular VM; providing, by each of the other VMMs to the root VMM in response to the root VMM's request, the requested instance of the particular VM; and identifying, by the root VMM, differences among the requested instances of the particular VM including, performing a bitwise XOR operation amongst the instances of the particular VM.

Abstract: Administering VMs in a distributed computing environment that includes hosts that execute a VMM, with each VMM supporting execution of one or more VMs, includes: assigning the VMMs to a logical tree topology with one as a root; and executing, by the VMMs of the tree topology, a reduce operation, including: sending, by the root VMM to each of other VMMs of the tree topology, a request for an instance of a particular VM; pausing, by each of the other VMMs, the requested instance of the particular VM; providing, by each of the other VMMs to the root VMM in response to the root VMM's request, the requested instance of the particular VM; and identifying, by the root VMM, differences among the requested instances of the particular VM including, performing a bitwise XOR operation amongst the instances of the particular VM.

Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.

Abstract: In a distributed computing environment that includes which each execute a VMM, where each VMM supports execution of one or more VMs, administering the VMs may include: assigning, by a VMM manager, the VMMs of the distributed computing environment to a logical tree topology, including assigning one of the VMMs as a root VMM of the tree topology; and executing, amongst the VMMs of the tree topology, a gather operation, including: sending, by the root VMM, to other VMMs in the tree topology, a request to retrieve one or more VMs supported by the other VMMs; pausing, by the other VMMs, each VM requested to be retrieved; and providing, by the other VMMs to the root VMM, the VMs requested to be retrieved.

Abstract: In a distributed computing environment that includes which each execute a VMM, where each VMM supports execution of one or more VMs, administering the VMs may include: assigning, by a VMM manager, the VMMs of the distributed computing environment to a logical tree topology, including assigning one of the VMMs as a root VMM of the tree topology; and executing, amongst the VMMs of the tree topology, a gather operation, including: sending, by the root VMM, to other VMMs in the tree topology, a request to retrieve one or more VMs supported by the other VMMs; pausing, by the other VMMs, each VM requested to be retrieved; and providing, by the other VMMs to the root VMM, the VMs requested to be retrieved.

Abstract: An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.