Instruction Modification Based On Condition Patents (Class 712/226)
  • Patent number: 10922131
    Abstract: The embodiments of the present disclosure provide an application function control method and a related product. The method includes: generating in response to detecting a starting instruction for a first application, a first instruction containing an application identifier of the first application; generating in response to finding out according to the first instruction that the disabled function set includes at least one first function of the first application, a second instruction containing a function identifier of the at least one first function and running according to the second instruction one or more functions, except the at least one first function, in multiple functions of the first application.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 16, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Jian Bai
  • Patent number: 10908908
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • Patent number: 10901739
    Abstract: Systems and methods for controlling machine operations are provided. A number of data entries are organized into a stack. Each data entry includes a type, a flag, a length, and a value or pointer entry. For each data entry in the stack, the type of data is determined from the type entry, the presence of an address or value is determined by the respective flag entry, and a length of the address or value is determined from the respective length entry. The data to be utilized or an address for the same at the electronic storage area is provided at the respective value or pointer entry.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: January 26, 2021
    Assignee: Rankin Labs, LLC
    Inventor: John Rankin
  • Patent number: 10839802
    Abstract: A method and data processing device for receiving, at a data processor, data that includes at least one personalized phrase. The method includes extracting a personalized phrase from received data. The method includes tracking, via an assigned phrase counter, each occurrence of the personalized phrase in the received data and subsequently received data. The method includes periodically comparing a value of the assigned phrase counter to pre-established count thresholds to determine when a count of the personalized phrase reaches at least one of the pre-established count thresholds. The method includes storing the personalized phrase to a phrase database and linking the personalized phrase to the one or more general phrases in the phrase database. The method includes selectively triggering a contextual response to the data and executing, by the data processor, the corresponding operation. The method includes outputting the contextual response to an output device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 17, 2020
    Assignee: Motorola Mobility LLC
    Inventors: Zhengping Ji, Rachid Alameh
  • Patent number: 10831507
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 10, 2020
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David Brian Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Patent number: 10810104
    Abstract: A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which the application code includes a prefixed instruction to be modified by a prefix, a trap is provided. The trap is configured to report a presence of the prefix, but to otherwise perform the trap functions absent the prefix; i.e., the prefix is otherwise ignored in the processing of the trap.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventor: Michael K. Gschwind
  • Patent number: 10795680
    Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Robert C. Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert D. Cavin, Bret L. Toll, Santiago Galan Duran, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind Baburao Girkar, Edward Thomas Grochowski, Jonathan Cannon Hall, Dennis R. Bradford, Elmoustapha Ould-Ahmed-Vall, James C. Abel, Mark Charney, Seth Abraham, Suleyman Sair, Andrew Thomas Forsyth, Lisa Wu, Charles Yount
  • Patent number: 10795675
    Abstract: An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 6, 2020
    Assignee: ARM Limited
    Inventors: Richard Roy Grisenthwaite, Nigel John Stephens
  • Patent number: 10761979
    Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Hugh Wilkinson, William R. Wheeler, Debra Bernstein
  • Patent number: 10761849
    Abstract: A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Ching-Tsun Chou, Oleg Margulis, Tyler N. Sondag
  • Patent number: 10719318
    Abstract: The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 21, 2020
    Assignee: Movidius Limited
    Inventor: David Moloney
  • Patent number: 10705972
    Abstract: Systems, apparatuses, and methods for determining preferred memory page management policies by software are disclosed. Software executing on one or more processing units generates a memory request. Software determines the preferred page management policy for the memory request based at least in part on the data access size and data access pattern of the memory request. Software conveys an indication of a preferred page management policy to a memory controller. Then, the memory controller accesses memory for the memory request using the preferred page management policy specified by software.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: July 7, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amin Farmahini-Farahani, Alexander D. Breslow, Nuwan S. Jayasena
  • Patent number: 10642620
    Abstract: In an embodiment, a computation engine may perform dot product computations on input vectors. The dot product operation may have a first operand and a second operand, and the dot product may be performed on a subset of the vector elements in the first operand and each of the vector elements in the second operand. The subset of vector elements may be separated in the first operand by a stride that skips one or more elements between each element to which the dot product operation is applied. More particularly, in an embodiment, the input operands of the dot product operation may be a first vector having second vectors as elements, and the stride may select a specified element of each second vector.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: May 5, 2020
    Assignee: Apple Inc.
    Inventors: Tal Uliel, Eric Bainville, Jeffry E. Gonion, Ali Sazegari
  • Patent number: 10628156
    Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy David Anderson, Duc Quang Bui, Mujibur Rahman, Joseph Raymond Michael Zbiciak, Eric Biscondi, Peter Dent, Jelena Milanovic, Ashish Shrivastava
  • Patent number: 10628161
    Abstract: A processor comprises an execution unit and a detection unit which are functionally connected. The execution unit is configured to execute computer programs, and the detection unit is configured to detect infinite loops during the execution of a computer program in the execution unit during run-time. The computer program has a plurality of go-to instructions, and each go-to instruction is characterized by a corresponding branch address. The detection unit is configured to calculate a detection function of the branch addresses of a branch sequence, the branch sequence including a sequence of executed go-to instructions. The detection function is chosen such that an increased value of the detection function is characteristic of an infinite loop in the branch sequence in which at least one go-to instruction is repeated.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 21, 2020
    Assignee: TECHNISCHE UNIVERSITÄT MÜNCHEN
    Inventors: Andreas Ibing, Julian Kirsch
  • Patent number: 10579389
    Abstract: An apparatus includes a processing pipeline comprising a plurality of stages, the plurality of stages including at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group. However, when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: March 3, 2020
    Assignee: ARM Limited
    Inventors: Ian Michael Caulfield, Chiloda Ashan Senerath Pathirane
  • Patent number: 10572259
    Abstract: An apparatus and method of operating a data processing apparatus are provided. The data processing circuitry is responsive to a hint instruction to then assert at least one performance modifying control signal, when subsequently generating control signals for other data processing instructions. This causes the data processing functional hardware which performs the data processing operations defined by the data processing instructions to operate in a modified manner, although the data processing results produced do not change in dependence on whether the at least one performance modifying control signal is asserted.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: February 25, 2020
    Assignee: ARM LIMITED
    Inventors: Jesse Garrett Beu, Alejandro Rico Carro, Lee Evan Eisen, Michael Filippo
  • Patent number: 10553207
    Abstract: The disclosed method may include (1) determining whether a next operation of a plurality of operations of a computational model is dependent upon a Boolean predication value, (2) based on the next operation not being dependent on the Boolean predication value, performing the next operation, where a state of the computational model is updated as a result of performing the next operation, and (3) based on the next operation being dependent on the Boolean predication value, performing at least one of (a) allowing, based on the Boolean predication value being a first value, the next operation to update the state of the computational model, and (b) preventing, based on the Boolean predication value being a second value different from the first value, the next operation from updating the state of the computational model. Various other methods and systems are also disclosed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 4, 2020
    Assignee: Facebook, Inc.
    Inventors: Nadav Rotem, Abdulkadir Utku Diril, Mikhail Smelyanskiy, Jong Soo Park, James Kenneth Reed
  • Patent number: 10552156
    Abstract: Processing circuitry for performing data processing operations includes issue control circuitry to control issue of the processing operations. Validity marking circuitry marks when input operands are valid and available within an issue queue, and is responsive to a first input operand of the plurality of input operands having a predetermined value to mark a second input operand of the plurality of input operands as meeting its validity condition (i.e. it is possible to determine from the first input operand that the result of the processing operation concerned will be independent of the value of the second input operand and accordingly there is no need to wait for it to actually be available). In order to resolve ordering constraint problems which may be associated with the use of the early valid marking technique separate ordering valid flags may be provided and monitored in respect of at least order-constrained processing operations.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 4, 2020
    Assignee: ARM Limited
    Inventor: Simon John Craske
  • Patent number: 10531516
    Abstract: An indication of an application-related objective is received at a first agent associated with a first device. One or more meta-language based descriptions comprising device data stored in a data store are used to identify a second device from a plurality of devices to help the first device to achieve the application-related objective. At least in part by exchanging with a second agent associated with the second device one or more programmatically determined bids and responses to bids, a mutually compatible set of configurations for the first device and the second device to cooperate with each other are determined to help achieve the application-related objective. The mutually compatible set of configurations comprising parameters are agreed upon by the first device and the second device. The first device and the second device are configured based at least in part on the mutually compatible set of configurations.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 7, 2020
    Inventor: Mark Cummings
  • Patent number: 10509635
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. The processor defines a special store instruction that is different from a regular store instruction. The special store instruction is used in regions of the computer program where memory aliasing may occur. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing may occur.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Patent number: 10489543
    Abstract: An integrated circuit can include programmable circuitry configured to implement an overlay circuit specified by an overlay and a processor coupled to the programmable circuitry. The processor can be configured to control the programmable circuitry through execution of a framework. The framework provides high-productivity language control of implementation of the overlay in the programmable circuitry.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 26, 2019
    Assignee: XILINX, INC.
    Inventors: Patrick Lysaght, Graham F. Schelle, Parimal Patel
  • Patent number: 10467124
    Abstract: The example embodiments are directed to an automated cloud platform certification process. In one example, the method includes receiving a request for adding an application to the cloud platform, executing the application and performing an automated certification process based on the executed application. According to various embodiments, the automated certification process may include verifying an output of the executed application, verifying an impact of the executed application on the cloud platform is below a predetermined threshold, and verifying the executed application satisfies applicable coding guidelines. The application may be stored or launched on the cloud platform following successful certification.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 5, 2019
    Assignee: General Electric Company
    Inventors: Haofeng Tang, Roopa Gidugu
  • Patent number: 10235173
    Abstract: Systems, apparatuses, and methods for implementing an IF2FOR transformation are disclosed. In one embodiment, a first group of instructions include an IF-statement and one or more control dependent instructions. The first group of instructions are transformed into a second group of instructions if the first group of instructions meet one or more criteria. In one embodiment, the criteria includes the (1) IF-statement being part of a loop and (2) the control dependent instructions not having any inter-loop iteration dependency. The second group of instructions are executable to (1) store results of the IF-statement condition for a first number of iterations and (2) execute the control dependent instructions for a second number of iterations when the IF-statement condition evaluates to true.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Anupama Rajesh Rasale
  • Patent number: 10228956
    Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Mark J. Dechene, Zhongying Zhang, Jason Agron, Sebastian Winkel
  • Patent number: 10175984
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 8, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10146547
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: December 4, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10133300
    Abstract: Embodiments are disclosed for a method of executing instructions in a processing core of a microprocessor. In one embodiment, the method comprises, in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain. The method further comprises synchronizing the input from the second clock domain with the first clock domain, if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction, and otherwise performing the instruction.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 20, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Matthew Ray Tubbs, Robert Allen Shearer, Ryan Haraden
  • Patent number: 10078515
    Abstract: Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael K Gschwind, Valentina Salapura
  • Patent number: 10073773
    Abstract: Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Logical elements such as processing elements are provided instructions via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 11, 2018
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10061588
    Abstract: Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael K Gschwind, Valentina Salapura
  • Patent number: 9996326
    Abstract: An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Ronald I. McIntosh
  • Patent number: 9984432
    Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 29, 2018
    Assignee: Mireplica Technology, LLC
    Inventor: William M. Johnson
  • Patent number: 9977677
    Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 22, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kurt A. Feiste, Christopher M. Mueller, Dung Q. Nguyen, Eula F. Tolentino, Tien T. Tran, Jing Zhang
  • Patent number: 9959102
    Abstract: An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.
    Type: Grant
    Filed: November 14, 2015
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Ronald I. McIntosh
  • Patent number: 9946538
    Abstract: A method and apparatus for providing support for self modifying guest code. The apparatus includes a memory, a hardware buffer, and a processor. The processor is configured to convert guest code to native code and store converted native code equivalent of the guest code into a code cache portion of the processor. The processor is further configured to maintain the hardware buffer configured for tracking respective locations of converted code in a code cache. The hardware buffer is updated based a respective access to a respective location in the memory associated with a respective location of converted code in the code cache. The processor is further configured to perform a request to modify a memory location after accessing the hardware buffer.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Karthikeyan Avudaiyappan
  • Patent number: 9946550
    Abstract: A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ram Rangan, William E. Speight, Mark W. Stephenson, Lixin Zhang
  • Patent number: 9916146
    Abstract: Presently described is a decompilation method of operation and system for parsing executable code, identifying and recursively modeling data flows, identifying and recursively modeling control flow, and iteratively refining these models to provide a complete model at the nanocode level. The nanocode decompiler may be used to determine if flaws, security vulnerabilities, or general quality issues exist in the code. The nanocode decompiler outputs in a standardized, human-readable intermediate representation (IR) designed for automated or scripted analysis and reporting. Reports may take the form of a computer annotated and/or partially human annotated nanocode listing in the above-described IR. Annotations may include plain English statements regarding flaws and pointers to badly constructed data structures, unchecked buffers, malicious embedded code or “trap doors,” and the like. Annotations may be generated through a scripted analysis process or by means of an expert-enhanced, quasi-autonomous system.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 13, 2018
    Assignee: Veracode, Inc.
    Inventor: Christien Rioux
  • Patent number: 9910674
    Abstract: In the data processor in which a combination of multiple specific instructions is prohibited, an instruction set is employed that additionally defines that prohibition combination pattern as a separate instruction. With respect to the prohibition combination pattern additionally defined as the separate instruction, for example, in order to make a definition in such a manner that an instruction dispatch mechanism for the instruction set that is present before the additional definition is used as is, the instruction to be additionally defined by the prohibition combination pattern is limited to an instruction type that is the same as the instruction defined only with a latter-half code of the instruction in a case of an instruction set in which the instruction set that is present before the additional definition includes a prefix code.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Fumio Arakawa
  • Patent number: 9904550
    Abstract: A method for combining instructions, performed by a compiler, containing at least the following steps. First instructions are obtained, where each performs one of a calculation operation, a comparison operation, a logic operation, a selection operation, a branching operation, a LD/ST (Load/Store) operation, a SMP (sampling) operation and a complicated mathematics operation. The first instructions are combined as one combined instruction according to data dependencies between the first instructions. The combined instruction is sent to a SP (Stream Processor).
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: February 27, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Huaisheng Zhang, Zhou Hong, Heng Qi
  • Patent number: 9886277
    Abstract: Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Maxim Loktyukhin, Robert Valentine, Julian C. Horn, Mark J. Charney
  • Patent number: 9830153
    Abstract: A pipelined run-to-completion processor executes a conditional skip instruction. If a predicate condition as specified by a predicate code field of the skip instruction is true, then the skip instruction causes execution of a number of instructions following the skip instruction to be “skipped”. The number of instructions to be skipped is specified by a skip count field of the skip instruction. In some examples, the skip instruction includes a “flag don't touch” bit. If this bit is set, then neither the skip instruction nor any of the skipped instructions can change the values of the flags. Both the skip instruction and following instructions to be skipped are decoded one by one in sequence and pass through the processor pipeline, but the execution stage is prevented from carrying out the instruction operation of a following instruction if the predicate condition of the skip instruction was true.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: November 28, 2017
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 9817665
    Abstract: A technique includes receiving a request from a processor to retrieve a first instruction from a memory for a staged execution pipeline. The technique includes selectively retrieving the first instruction from the memory in response to the request based on a determination of whether the processor will execute the first instruction.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 14, 2017
    Assignee: SILICON LABORATORIES INC.
    Inventor: Paul I. Zavalney
  • Patent number: 9804852
    Abstract: In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Jonathan D. Combs, Jason W. Brandt, Robert Valentine, Kevin B. Smith, Zia Ansari, Maxim Loktyukhin
  • Patent number: 9778949
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for thread waiting. One of the methods includes starting, by a first thread on a processing core, a task by starting to execute a plurality of task instructions; initiating, by the first thread, an atomic memory transaction using a transactional memory system, including: specifying, to the transactional memory system, at least a first memory address for the atomic memory transaction and temporarily ceasing the task by not proceeding to execute the task instructions; receiving, by the first thread, a signal as a consequence of a second thread accessing the first memory address specified for the atomic memory transaction; and as a consequence of receiving the signal, resuming the task, by the first thread, and continuing to execute the task instructions.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 3, 2017
    Assignee: Google Inc.
    Inventor: Benjamin C. Serebrin
  • Patent number: 9684510
    Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Igor Ermolaev, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, Jesus Corbal San Adrian, Andrey Naraikin
  • Patent number: 9639360
    Abstract: A data processing system is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction Inst0 and an intermediate value consuming instruction Inst1. In dependence upon one or more input operands to the evaluation, an embedded opcode within the intermediate value passed between the intermediate value generating instruction and the intermediate value consuming instruction may be set to have a value indicating that a substitute instruction should be used in place of the intermediate value consuming instruction. The instructions may be floating point instructions, such as a floating point power instruction evaluating the data processing function ab.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: May 2, 2017
    Assignee: ARM Limited
    Inventor: Jorn Nystad
  • Patent number: 9619235
    Abstract: A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 11, 2017
    Assignees: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Mitsuru Tomono, Hiroya Uehara, Makiko Ito
  • Patent number: 9582279
    Abstract: Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked, and based on the confidence level being a first value, a predicted operation of the instruction, which is based on a predictor, is unconditionally performed. Further, based on the confidence level being a second value, a specified operation of the instruction, which is based on a determined condition, is conditionally performed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9563424
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for selecting native code instructions. One of the methods includes receiving an initial machine language instruction for execution by a processor in a first execution mode; determining that a portion of the initial machine language instruction, when executed by the processor in a second execution mode, satisfies one or more risk criteria; generating one or more alternative machine language instructions to replace the initial machine language instruction for execution by the processor in the first execution mode, wherein the one or more alternative machine language instructions, when executed by the processor in the second execution mode, mitigate the one or more risk criteria; and providing the one or more alternative machine language instructions.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: February 7, 2017
    Assignee: Google Inc.
    Inventors: David C. Sehr, Bennet S. Yee, Jean-Francois Bastien