Abstract: A method of visual media processing includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode; for a sample spatially located at location of the current video block relative to an upper-left position of a coding tree unit including the current video block and having a block vector, computing a corresponding reference in the buffer at a reference location, wherein the reference location is determined using the block vector and the location; and upon determining that the reference location lies outside the buffer, re-computing the reference location based at least in part on a location of the current video block relative to the coding tree unit including the current video block.

Abstract: Embodiments include a hierarchical metadata prediction system that includes a first line-based predictor having a first line for storage of metadata entries, and a second line-based predictor configured to store metadata entries from the first line-based predictor. The second line-based predictor has a second line, the second line including a plurality of containers, the plurality of containers including at least a first set of containers having a first size and a second set of containers having a second size. The system also includes a processing device configured to transfer one or more metadata entries between the first line-based predictor and the second-line based predictor. Embodiments also include a computer-implemented method and a computer program product.

Abstract: A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

Abstract: An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.

Abstract: A semiconductor device (100) includes: first storage means (110) storing, in advance, a plurality of pieces of execution order inspection information (111˜11n) used for inspection of an execution order of a plurality of code blocks in a predetermined program, second storage means (120), which is a cache for the first storage means, and prediction means (130) for predicting a storage area of the execution order inspection information based on prediction auxiliary information in a first code block of the plurality of code blocks and a control flow graph of the program, the storage area being a prefetch target to be prefetched from the first storage means to the second storage means.

Abstract: Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

Abstract: Restoring speculative history used for making speculative predictions for instructions processed in a processor. The processor can be configured to speculatively predict an outcome of a condition or predicate of a conditional control instruction before its condition is fully evaluated in execution. Predictions are made by the processor based on a history that is updated based on outcomes of past predictions. If a conditional control instruction is mispredicted in execution, the processor can perform a misprediction recovery by stalling the instruction pipeline, flushing younger instructions in the instruction pipeline back to the mispredicted conditional control instruction, and then re-fetching instructions in the correct instruction flow path for execution.

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.

Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

Abstract: A storage device includes a non-volatile memory including a plurality of memory blocks. The storage device performs an alignment operation in response to receipt of an align command. The alignment operation converts a received logical address of a logical segment into a physical address and allocates the physical address to a physical block address corresponding to a free block. The storage device is further configured to performs a garbage collection in units of the physical block address that indicates one memory block.

Abstract: An apparatus comprises a branch predictor to predict an outcome of a branch instruction to be processed by processing circuitry, based on branch prediction state information stored in one or more branch prediction structures, and a call path tracking element to store call path tracking information, where in response to a procedure calling instruction processed by the processing circuitry, the call path tracking information is updated depending on at least a portion of an address associated with the procedure calling instruction. The one or more branch prediction structures include at least one call-path-indexed branch prediction structure which is indexed based on an index value which depends on a portion of the call path tracking information stored in the call path tracking element.

Abstract: A microprocessor includes a translation look-aside buffer (TLB) having a plurality of TLB entries addressable by a branch address and having a branch target buffer (BTB), including a plurality of BTB entries addressable by the branch address. Each TLB entry includes a virtual address. Each BTB entry including a branch tag-way data and a target tag-way data. To perform a branch prediction, the BTB and TLB are accessed, where the TLB way associative data representing one of N sets of TLB entries is used to determine BTB hit or BTB miss. If BTB hit, the branch target address of the branch address may be obtained by accessing the TLB using target tag-way data in the BTB, or by using the branch page address when a same page bit in the hit BTB entry is set.

Abstract: A system includes a branch predictor and a processing circuit configured to perform a plurality of operations including storing a skip-over offset value in the branch predictor. The skip-over offset value defines a number of search addresses of the branch predictor to be skipped. The operations further include searching the branch predictor for a branch prediction. Responsive to finding the branch prediction, the searching of the branch predictor is re-indexed based on the skip-over offset value associated with the branch prediction.

Abstract: A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.

Abstract: A non-volatile storage device includes a compact and efficient filter of data samples for a monitored statistic about operation of the storage device. The non-volatile storage device comprises a plurality of non-volatile memory cells and a control circuit connected to the non-volatile memory cells. The control circuit is configured to maintain at the non-volatile storage device a sum of samples of the statistic for a moving window of the samples such that during operation new samples are added to the sum and contributions from old samples are removed from the sum by the control circuit multiplying the sum by a weight when adding the new samples.

Abstract: An arithmetic processing device includes: a pipeline circuit including an instruction fetch circuit, an instruction decoder that performs a first branch misprediction determination for a branch instruction, and issues the instructions in-order, a branch instruction processing circuit which performs a second branch misprediction determination for the branch instruction; and a commit processing circuit that executes a commit processing of the processed instructions in-order.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions fetched from an instruction cache, an instruction prefetcher to speculatively prefetch instructions into the instruction cache, and a branch predictor having at least one branch prediction structure to store branch prediction data for predicting at least one branch property of an instruction fetched for processing by the processing circuitry. On prefetching of a given instruction into the instruction cache by the instruction prefetcher, the branch predictor is configured to perform a prefetch-triggered update of the branch prediction data based on information derived from the given instruction prefetched by the instruction prefetcher. This can help to improve performance, especially for workloads with a high branch density and large branch re-reference interval.

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

Abstract: An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.

Abstract: Techniques for improving branch target buffer (“BTB”) operation. A compressed BTB is included within a branch prediction unit along with an uncompressed BTB. To support prediction of up to two branch instructions per cycle, the uncompressed BTB includes entries that each store data for up to two branch predictions. The compressed BTB includes entries that store data for only a single branch instruction for situations where storing that single branch instruction in the uncompressed BTB would waste space in that buffer. Space would be wasted in the uncompressed BTB due to the fact that, in order to support two branch lookups per cycle, prediction data for two branches must have certain features in common (such as cache line address) in order to be stored together in a single entry.

Abstract: Query processors often receive queries to be processed against a data set, such as by inserting user input into parameterized fields of a query template. Some queries may include a conditional statement, and manipulation of user input (e.g., injection attacks) may introduce a delay through a conditional branch. The time required to fulfill the query may indicate which conditional branch was taken, thus revealing properties of the data set that are intended to be withheld. Instead, a query processor may examine the query to identify, between a pair of conditional branches, a processing delay of the first conditional branch as compared with the second conditional branch. The query processor may identify a query adaptation that reduces the processing delay of the first conditional branch as compared with the second conditional branch, and evaluate the query against the data set according to the query adaptation to present a query result.

Abstract: Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system is disclosed. The prediction system includes a prediction circuit employing reduced operation folding of the history register for indexing a prediction table containing prediction values used to process a consumer instruction when value has not yet been resolved. To avoid the requirement to perform successive logic folding operations to produce a folded context history of a resultant reduced bit width, reduced logic level folding operation of the resultant reduced bit width is employed. Reduced logic level folding operation of the resultant reduced bit width involves using current folded context history from previous contents of a history register as basis for determining a new folded context history. In this manner, logic folding of the history register is faster and operates with reduced power consumption as a result of fewer logic operations.

Abstract: An execution flow protection module (30) for a microcontroller (10) with a memory (24) and a microprocessor (20) is described. The module (30) is configured to monitor the memory (24) access of the microcontroller (10) to identify instructions fetched by the microcontroller (10) from the memory (24) for execution by the microprocessor (20). The module (30) comprises an instruction decoder unit (32) for determining a program counter value associated with the execution flow of the instructions fetched by the microcontroller (10); a program counter predictor unit (34) for predicting the program counter value of the next fetched instruction; and an interrupt module (40) for responding if the next instruction fetched by the microcontroller does not match the predicted program counter value.

Abstract: In an approach for decreasing an execution time of a computer code, one or more processors identify a long-form conditional branch that is included in a first region of a computer code. The one or more processors generate a long-form unconditional branch with a target that is a target of a long-form conditional branch. The one or more processors modify the long-form conditional branch to be a short-form conditional branch. The one or more processors insert the long-form unconditional branch into the computer code within a branch distance of the short-form conditional branch. The one or more processors modify a target of the short-form conditional branch to be a location of the long-form unconditional branch in the computer code.

Abstract: A processor includes: an instruction execution unit that executes an instruction; and a branch prediction unit that stores history information indicating every instruction fetches performed a certain number of times before an instruction fetch of a branch prediction target instruction whether the instruction predicted as branch-taken is included and weight tables including weights corresponding to instructions and predicts the branch prediction target instruction to be taken or not-taken. The branch prediction unit, before the instruction fetch of the branch prediction target instruction, obtains the history information and the weights related to the instruction fetches performed the certain number of times to perform a product-sum operation, and at the time of the instruction fetch of the branch prediction target instruction, performs an operation of a result of the product-sum operation and a weight of the branch prediction target instruction to perform branch prediction.

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

Abstract: The disclosed embodiments provide a system that facilitates prefetching an instruction cache line in a processor. During execution of the processor, the system performs a current instruction cache access which is directed to a current cache line. If the current instruction cache access causes a cache miss or is a first demand fetch for a previously prefetched cache line, the system determines whether the current instruction cache access is discontinuous with a preceding instruction cache access. If so, the system completes the current instruction cache access by performing a cache access to service the cache miss or the first demand fetch, and also prefetching a predicted cache line associated with a discontinuous instruction cache access which is predicted to follow the current instruction cache access.

Abstract: Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media are disclosed. In one embodiment, a branch prediction circuit including a first branch predictor and a second branch predictor is provided. The first branch predictor generates a first branch prediction for a conditional branch instruction, and the first branch prediction is stored in a first branch prediction history. The first branch prediction is also speculatively forwarded to a second branch prediction history. The second branch predictor subsequently generates a second branch prediction based on the second branch prediction history, including the speculatively forwarded first branch prediction. By enabling the second branch predictor to base its branch prediction on the speculatively forwarded first branch prediction, an accuracy of the second branch predictor may be improved.

Abstract: Technologies for supporting large pages in hardware prefetchers are described. A processor includes a processor core comprising a pipeline, cache memory and a hardware prefetcher coupled to the processor core and the cache memory. The hardware prefetcher is a region-based hardware prefetcher to track memory regions of a predefined region size that is defined by software to be executed by the processor. The hardware prefetcher is operative to receive incoming requests and track different memory regions of predefined size with multiple streams in a stream table with stream entries. The hardware prefetcher generates a prefetch request and determines whether the prefetch request goes beyond a page boundary of the one memory region. The hardware prefetcher creates a new stream entry to track a successive memory region when the prefetch request goes beyond the page boundary of the one memory region, allowing subsequent prefetch requests to the successive memory region.

Abstract: Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a system for a semi-exclusive second-level branch target buffer. The system includes a first-level branch target buffer (BTB1), a branch target buffer preload table (BTBP), and a second-level branch target buffer (BTB2) coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes performing a search to locate entries in the BTB2 having a memory region corresponding to a search request. Based on locating entries in the BTB2, a bulk transfer of located entries is performed from the BTB2 to the BTBP. A state associated with the located entries is updated to encourage exclusivity between the BTB1 and the BTB2. Based on transferring a BTBP entry from the BTBP to the BTB1, a BTB1 entry is evicted from the BTB1. The evicted BTB1 entry is transferred from the BTB1 to the BTB2.

Abstract: Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB2 having a memory region corresponding to a search request. Based on locating the entries in the BTB2, a bulk transfer of located entries is performed from the BTB2 to a BTBP. A state associated with the located entries is updated to encourage exclusivity between the BTB1 and the BTB2. Based on transferring a BTBP entry from the BTBP to a BTB1, a BTB1 entry is evicted from the BTB1. The evicted BTB1 entry is transferred from the BTB1 to the BTB2.

Abstract: An AC-to-DC adapter may be provided in order to increase the sensitivity of a touch-sensitive surface. Such an AC-to-DC adapter may include a rectifying circuit to rectify incoming AC signals. The rectifying circuit may take the form of a diode bridge network that includes four diode branches. Stabilization circuits may be provided in parallel with each diode branch in order to decrease the impedance of the diode bridge network during particular periods of operation. The stabilization circuits may be configured such that the impedance of the diode bridge network is substantially constant during all periods of operation. As a result, the impedance of the AC-to-DC adapter may be relatively constant during all periods of operation. In turn, the sensitivity of a touch-sensitive surface of a device being powered by such an AC-to-DC adapter may increase.

Abstract: Techniques for detecting security exploits associated with return-oriented programming are described herein. For example, a computing device may determine that a retrieved count is indicative of malicious activity, such as return oriented programming. The computing device may retrieve the count from a processor performance counter of prediction mismatches, the prediction mismatches resulting from comparisons of a call stack of the computing device and of a shadow call stack maintained by a processor of the computing device. In response to determining that the count indicates malicious activity, the computing device may perform at least one security response action.

Abstract: Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.

Abstract: Disclosed herein is a memory access control circuit including: a determination section adapted to determine whether a target requested by a first wraparound memory access request from a processor is stored in a prefetch buffer; a request generation section adapted to generate a second wraparound memory access request including the target if it is determined that the target is not stored in the prefetch buffer; and an address conversion section adapted to convert the start address of the first wraparound memory access request according to predetermined rules for use as a start address of the second wraparound memory access request.

Abstract: According to one embodiment, a method for a store operation with a conditional push of a tag value to a queue is provided. The method includes configuring a queue that is accessible by an application, setting a value at an address in a memory device including a memory and a controller, receiving a request for an operation using the value at the address and performing the operation. The method also includes the controller writing a result of the operation to the address, thus changing the value at the address, the controller determining if the result of the operation meets a condition and the controller pushing a tag value to the queue based on the condition being met, where the tag value in the queue indicates to the application that the condition is met.

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

Abstract: A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.

Abstract: Embodiments relate to a semi-exclusive second-level branch target buffer. An aspect includes a computer-implemented method for a semi-exclusive second-level branch target buffer. The method includes performing a search to locate entries in a BTB2 having a memory region corresponding to a search request. Based on locating the entries in the BTB2, a bulk transfer of located entries is performed from the BTB2 to a BTBP. A state associated with the located entries is updated to encourage exclusivity between the BTB1 and the BTB2. Based on transferring a BTBP entry from the BTBP to a BTB1, a BTB1 entry is evicted from the BTB1. The evicted BTB1 entry is transferred from the BTB1 to the BTB2.

Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a processing circuit, for an entry corresponding to the search request in a first-level branch target buffer. The method also includes, based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. The method additionally includes, based on locating the entries in the second-level branch target buffer, performing a bulk transfer of the entries from the second-level branch target buffer.

Abstract: A multiple stage branch prediction system including a branch target address cache (BTAC) and a branch predictor circuit is disclosed. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of a branch instruction and to manage the BTAC entry based on the stored state information in response to actual resolution of the branch instruction.

Abstract: Exemplary embodiments include a system and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry corresponds to one or more branch target buffer rows and specifies the ordering from least-recently-used to most-recently-used of the associated branch target buffer columns, selecting a row from the branch target buffer and simultaneously selecting the associated entry from the most-recently-used table and speculating that there is a prediction in the most recently used column of the plurality of columns from the selected row from the branch target buffer while determining whether there is a prediction and which column contains the prediction.

Abstract: A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and a tag may indicate the location of the stored target. The tag may be associated with the CTI rather than associating the complete target address with the CTI. When the CTI reaches an execution stage of the processor, the tag may be used to retrieve the predicted target address. In some embodiments using a tag to retrieve a predicted target, CTI instructions from different processor threads may be interleaved without affecting retrieval of predicted targets.

Abstract: A method includes executing a branch instruction and determining if a branch is taken. The method further includes evaluating a number of instructions associated with the branch instruction. Upon determining that the branch is taken, the method includes selectively writing an entry into a branch target buffer that corresponds to the taken branch responsive to determining that the number of instructions is less than a threshold.

Abstract: A method for a delayed branch implementation by using a front end track table. The method includes receiving an incoming instruction sequence using a global front end, wherein the instruction sequence includes at least one branch, creating a delayed branch in response to receiving the one branch, and using a front end track table to track both the delayed branch the one branch.

Abstract: A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit.

Abstract: A multiple stage branch prediction system includes a branch target address cache (BTAC) and a branch predictor circuit. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of a branch instruction and to manage the BTAC entry based on modified state information prior to resolution of the branch instruction.

Abstract: Embodiments relate to branch prediction table install source tracking. An aspect includes a computer-implemented method for branch prediction table install source tracking. The method includes receiving at a branch target buffer a request to install a branch target buffer entry corresponding to a branch instruction for branch prediction. The method further includes identifying, by a computer, a source of the request as an install source of the branch target buffer entry. The method also includes storing, by the computer, an install source identifier in the branch target buffer based on the install source.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating branches in computer code. A compiler or a post-compilation tool can obfuscate branches by receiving source code, and compiling the source code to yield computer-executable code. The compiler identifies branches in the computer-executable code, and determines a return address and a destination value for each branch. Then, based on the return address and the destination value for each branch, the compiler constructs a binary tree with nodes and leaf nodes, each node storing a balanced value, and each leaf node storing a destination value. The non-leaf nodes are arranged such that searching the binary tree by return address leads to a corresponding destination value. Then the compiler inserts the binary tree in the computer-executable code and replaces each branch with instructions in the computer-executable code for performing a branching operation based on the binary tree.

Abstract: A branch target address table is provided for each branch instruction having a plurality of branch targets. Each branch target address table stores a history of a plurality of branch target addresses determined in the past by executing a corresponding branch instruction. A branch target prediction unit predicts a predicted branch target address with respect to a branch instruction with reference to the history of branch target addresses stored in the branch target address table corresponding to the branch instruction. The predicted branch target address obtained as a result of the prediction is stored, for example, in a predicted branch target address storage unit in association with the branch instruction, and is referenced by an instruction fetch control unit at the time of prefetching a branch target instruction.