Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) Patents (Class 712/233)
  • Patent number: 11630800
    Abstract: In one embodiment of the present invention, a programmable vision accelerator enables applications to collapse multi-dimensional loops into one dimensional loops. In general, configurable components included in the programmable vision accelerator work together to facilitate such loop collapsing. The configurable elements include multi-dimensional address generators, vector units, and load/store units. Each multi-dimensional address generator generates a different address pattern. Each address pattern represents an overall addressing sequence associated with an object accessed within the collapsed loop. The vector units and the load store units provide execution functionality typically associated with multi-dimensional loops based on the address pattern. Advantageously, collapsing multi-dimensional loops in a flexible manner dramatically reduces the overhead associated with implementing a wide range of computer vision algorithms.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 18, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Ching Y. Hung, Jagadeesh Sankaran, Ravi P. Singh, Stanley Tzeng
  • Patent number: 11614944
    Abstract: In one embodiment, a branch prediction control system is configured to move a mispredicted conditional branch from a smaller cache side that uses the lower complexity conditional branch predictor to one of the two large cache sides that uses the higher complexity conditional branch predictors. The move (write) is achieved according to a configurable probability or chance to escape misprediction recurrence and results in a reduced amount of mispredictions for the given branch instruction.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 28, 2023
    Assignee: CENTAUR TECHNOLOGY, INC.
    Inventor: Thomas C. McDonald
  • Patent number: 11334354
    Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 17, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy Anderson, Duc Quang Bui, Joseph Zbiciak
  • Patent number: 11200062
    Abstract: Systems, apparatuses, and methods for implementing a physical register last reference scheme are described. A system includes a processor with a mapper, history file, and freelist. When an entry in the mapper is updated with a new architectural register-to-physical register mapping, the processor creates a new history file entry for the given instruction that caused the update. The processor also searches the mapper to determine if the old physical register that was previously stored in the mapper entry is referenced by any other mapper entries. If there are no other mapper entries that reference this old physical register, then a last reference indicator is stored in the new history file entry. When the given instruction retires, the processor checks the last reference indicator in the history file entry to determine whether the old physical register can be returned to the freelist of available physical registers.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: December 14, 2021
    Assignee: Apple Inc.
    Inventors: Deepankar Duggal, Conrado Blasco, Muawya M. Al-Otoom, Richard F. Russo
  • Patent number: 11157612
    Abstract: To detect tampering in secure computation while maintaining confidentiality with a little communication traffic. A random number generation part (11) generates [{right arrow over (?)}ri], [{right arrow over (?)}si]. A random number multiplication part (12) computes [{right arrow over (?)}ti]:=[{right arrow over (?)}ri{right arrow over (?)}si]. A secret multiplication part (13) computes [{right arrow over (?)}z]:=[{right arrow over (?)}x{right arrow over (?)}y]. A random number verification part (14) discloses a pi,jth element of each of [{right arrow over (?)}ri], [{right arrow over (?)}si], [{right arrow over (?)}ti] and confirms whether the element has integrity as multiplication. A random number substitution part (15) randomly substitutes elements in each of [{right arrow over (?)}ri], [{right arrow over (?)}si], [{right arrow over (?)}ti] except for the pi,j-th element to generate [{right arrow over (?)}r?i], [{right arrow over (?)}s?i], [{right arrow over (?)}t?i].
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: October 26, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventor: Dai Ikarashi
  • Patent number: 11120603
    Abstract: A shader core includes a first processing element (PE), a second processing element, a register file and a warp sequencing unit. The first PE includes a first predetermined number of execution units, and the second PE includes a second predetermined number of execution units in which the second predetermined number of execution units is less than the first predetermined number of execution units. The register file shared by the first PE and the second PE. The warp sequencer unit (WSQ) is coupled to the first PE and to the second PE and schedules an instruction trace to execute on the first PE or the second PE based on information contained in a trace header of the instruction trace. The information contained in the trace header indicates whether the instruction trace is executable on the second PE.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 14, 2021
    Inventors: Tejash M. Shah, Mark Greenberg
  • Patent number: 11074080
    Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: July 27, 2021
    Assignee: ARM Limited
    Inventors: Peter Richard Greenhalgh, Simon John Craske, Ian Michael Caulfield, Max John Batley, Allan John Skillman, Antony John Penton
  • Patent number: 11016861
    Abstract: Embodiments for crash recoverability for graphics processing units (GPUs) by a processor. GPU application data and kernel execution state of one or more GPUs may be checkpointed. The checkpointed GPU application data and the kernel execution state may be recovered. The checkpointed GPU application data and the kernel execution state may be persisted on non-volatile memory.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: I-Hsin Chung, Zaid Qureshi, Jinjun Xiong, Hubertus Franke
  • Patent number: 11016874
    Abstract: An example system includes a processor to receive an application to be instrumented. The processor is to also instrument the application based on a baseline taint tracking scheme to generate an instrumented application including taint tags. The processor is also to execute the instrumented application and generate a profile of runtime behavior of the application. The processor is to modify the baseline tracking scheme based on the profile to generate an updated taint tracking scheme.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Roee Hay, Omer Tripp
  • Patent number: 11003457
    Abstract: A pipelined processor for carrying out pipeline processing of instructions, which undergo a plurality of stages, is provided. The pipelined processor includes: a memory-activation indicator and a memory controller. The memory-activation indicator stores content information that indicates whether to activate a first volatile memory and/or a second volatile memory while performing a current instruction. The memory controller is arranged for controlling activation of the first volatile memory and/or the second volatile memory in a specific stage of the plurality of stages of the current instruction according to the content information stored in the memory-activation indicator.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 11, 2021
    Assignee: MEDIATEK INC.
    Inventors: Hsing-Chuang Liu, Chang-Chia Lee, Yu-Shu Chen
  • Patent number: 10990448
    Abstract: A memory subsystem for use with a single-instruction multiple-data (SIMD) processor comprising a plurality of processing units configured for processing one or more workgroups each comprising a plurality of SIMD tasks, the memory subsystem comprising: a shared memory partitioned into a plurality of memory portions for allocation to tasks that are to be processed by the processor; and a resource allocator configured to, in response to receiving a memory resource request for first memory resources in respect of a first-received task of a workgroup, allocate to the workgroup a block of memory portions sufficient in size for each task of the workgroup to receive memory resources in the block equivalent to the first memory resources.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 27, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower, Jonathan Redshaw
  • Patent number: 10972789
    Abstract: Aspects of the subject disclosure may include, for example, receiving, over a communication network, a plurality of requests for frames of video content to provide to a mobile device. Further embodiments can include determining a first portion of the plurality of requests are for pre-fetch frames of the video content, and providing, over the communication network, the pre-fetch frames to the mobile device over a default bearer path. Additional embodiments can include determining a second portion of the plurality of requests are for emergent frames of the video content, and providing, over the communication network, the emergent frames to the mobile device over a dedicated bearer path. Other embodiments are disclosed.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 6, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Zhehui Zhang, Shu Shi, Rittwik Jana, Varun Gupta
  • Patent number: 10936318
    Abstract: A computer system includes a first predictor circuit configured to generate a first predictor signal, and a second predictor circuit configured to generate a second predictor signal different from the first predictor signal. The computer system further includes a TIP arbiter configured to receive the first predictor signal and the second predictor signal, and to select one of the first predictor signal or the second predictor signal as a final prediction of a target address for a fetched branch instruction. The selection is based at least in part on a comparison between a branch address of the fetched branch instruction and a stored tag value, along with a counter value stored in the arbiter entry.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ehsan Fatehi, Naga Gorti, Nicholas Orzol, Christian Zoellin
  • Patent number: 10937118
    Abstract: A method and system are described herein for an optimization technique on two aspects of thread scheduling and dispatch when the driver is allowed to pick the scheduling attributes. The present techniques rely on an enhanced GPGPU Walker hardware command and one dimensional local identification generation to maximize thread residency.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Jayanth N. Rao, Michal Mrozek
  • Patent number: 10922081
    Abstract: Establishing a conditional branch frame barrier is described. A conditional branch in a function epilogue is used to provide frame-specific control. The conditional branch evaluates a return condition to determine whether to return from a callee function to a calling function, or to execute a slow path instead. The return condition is evaluated based on a thread local value. The thread local value is set such that returns to potentially unsafe frames in a call stack are prohibited. The prohibition to return to a potentially unsafe frame may be referred to as a “frame barrier.” Additionally, the thread local value may be used to establish safepointing and/or thread local handshakes, both after execution of a function body and after execution of a loop body.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 16, 2021
    Assignee: Oracle International Corporation
    Inventor: Erik Österlund
  • Patent number: 10922099
    Abstract: A method of generating a user interface for presentation to a user. The method comprises executing a first application computer program to provide a user interface, executing agent computer program code to interrogate and modify said user interface during execution of said first application computer program, and presenting said modified user interface. The first application computer program may be run on a server, while the modified user interface may be presented to a user at a client connected to said server.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 16, 2021
    Assignee: VERSATA FZ-LLC
    Inventor: Plamen Ivanov Valtchev
  • Patent number: 10884746
    Abstract: A determination is made as to whether an instruction is an affiliation-creating instruction that provides an affiliation between a plurality of registers. Based on determining the instruction is an affiliation-creating instruction, an affiliation is specified. Further, a branch instruction is obtained. The branch instruction is separated from the instruction by one or more instructions. Based on the branch instruction and specifying the affiliation, processing is performed.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10795729
    Abstract: Disclosed is a data accelerated processing system including a processing device, a storage device, an interface device and a control device. The processing device is configured to realize accelerated operation processing of data. The storage device is electrically connected to the processing device for storing the data sent by a server. The interface device is electrically connected to the processing device for data transmission between the processing device and the server. The control device is configured to regulate the status of the processing device. During an operation process, a large number of operating tasks in the server may be transmitted to the processing device for operating through the interface device, and large amounts of buffered data may be stored in the storage device. The data accelerated processing system improves data reading speed and operation efficiency through the cooperation of the processing device, the storage device and the interface device.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 6, 2020
    Assignee: Cambricon Technologies Corporation Limited
    Inventors: Kun Li, Dejing Wang, Shuo Xing
  • Patent number: 10795683
    Abstract: Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting a more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan, Mauricio J. Serrano
  • Patent number: 10782973
    Abstract: A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carlo Bertolli, John Kevin Patrick O'Brien, Alexandre E Eichenberger, Zehra Noman Sura
  • Patent number: 10761855
    Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 10719319
    Abstract: In one embodiment, a processor comprises a decoder to decode a first instruction, the first instruction comprising an opcode and at least one parameter, the opcode to identify the first instruction as an instruction associated with an indirect branch, the at least one parameter indicative of whether the indirect branch is allowed; and circuitry to generate an error message based on the at least one parameter.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Kekai Hu, Ke Sun, Rodrigo Branco
  • Patent number: 10705849
    Abstract: A data processing system includes a multithreaded processor to execute a plurality of selected program threads in parallel. A mode-selectable processor is coupled to the multithreaded processor and executes in either a first mode or a second mode. In the first mode program instructions from a single thread are executed. In the second mode, which is selected when the single program thread is inactive, program instructions forming a plurality of borrowed threads are executed. These borrowed threads are taken from a queue of candidate program threads which is managed by the multithreaded processor.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 7, 2020
    Assignee: The Regents of the University of Michigan
    Inventors: Seyedamirhossein Mirhosseininiri, Thomas Friedrich Wenisch
  • Patent number: 10681076
    Abstract: A method for identifying security vulnerabilities in a third party software component includes generating a test application for the third party software component. The test application is generated such that every externally accessible data path in the third party component is called. The test application and the third party software component are analyzed using a static application security testing (SAST) code analyzer. One or more test results are obtained from the SAST code analyzer. The one or more test results are used to identify security vulnerabilities in the third party component.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jeremy W. Long, Mitch Moon
  • Patent number: 10635655
    Abstract: It is proposed a device and method for finding nilcatenations, and proposes nilcatenation detection techniques, which can be applied to blockchains, and even constitute a proof of useful work, as the periodic removal of nilcatenations keeps a ledger size as small as possible. Banks and blockchains need to keep track of an ever-increasing list of transactions between the accounts owned by their users. However, as time goes by, many of these transactions can be safely “forgotten”, in the sense that purging a set of transactions that compensate each other does not impact the network's semantic meaning i.e. the vector Bt of amounts representing the balances of users at a given point in time t. Nilcatenation refers to a collection of past transaction vectors having no effect on Bt. Removing these transactions yields a smaller, but equivalent set of transactions.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 28, 2020
    Assignee: INGENICO GROUP
    Inventors: David Naccache, Remi Geraud
  • Patent number: 10613842
    Abstract: A computer-implemented method includes receiving an initial control flow graph (CFG) describing a project, where the project includes one or more programs. The initial CFG includes a plurality of graph nodes and a plurality of edges connecting the plurality of graph nodes to one another. Based on first profiling data, a first set of one or more graph nodes of the plurality of graph nodes of the initial CFG is selected as a first set of main nodes. The first profiling data describes a first execution history of the project. The initial CFG is simplified by generating a first final CFG, which includes the first set of main nodes and excludes one or more remaining nodes of the initial CFG that are not in the first set of main nodes.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bao Zhang, Naijie Li, Ming Ran Liu, Yuan Zhai
  • Patent number: 10592244
    Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
  • Patent number: 10564973
    Abstract: A processor fetches instructions from a plurality of threads. Each entry in a branch information storage (BIS) stores a virtual address ID for a branch, information about the branch, and thread ID information. The BIS is accessed using a virtual address of an instruction to be fetched for a thread to determine whether a hit exists, and if so, to obtain the branch information stored in the entry that gave rise to the hit. The virtual address is converted into a physical address, and an address translation regime is specified for each thread. When allocating an entry into the BIS, allocation circuitry determines, for a branch instruction for a current thread, whether the address translation regime is shared by plural threads. If so, the allocation circuitry identifies both the current thread and any other thread for which the address translation regime is shared.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 18, 2020
    Assignee: ARM LIMITED
    Inventors: Alexander Alfred Hornung, Ian Michael Caulfield
  • Patent number: 10564974
    Abstract: A determination is made as to whether an instruction is an affiliation-creating instruction that provides an affiliation between a plurality of registers. Based on determining the instruction is an affiliation-creating instruction, an affiliation is specified. Further, a branch instruction is obtained. The branch instruction is separated from the instruction by one or more instructions. Based on the branch instruction and specifying the affiliation, processing is performed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10528365
    Abstract: A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: January 7, 2020
    Assignee: Imagination Technologies Limited
    Inventors: David William Knox, Michael John Davis, Adrian John Anderson
  • Patent number: 10437597
    Abstract: A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Adam B. Collura, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 10346350
    Abstract: A processor includes an architectural register file loadable with micro-operations by architectural instructions of an architectural instruction set of the processor and an execution unit that executes instructions. The instructions are either architectural instructions or microinstructions into which architectural instructions are translated. The execution unit includes a decoder that decodes the instructions into micro-operations, a mode indicator that indicates one of first and second modes, a pipeline of stages to which are provided micro-operations that control circuits of the stages of the pipeline, and a multiplexer. The multiplexer selects for provision to the pipeline a micro-operation received from the decoder when the mode indicator indicates the first mode and selects for provision to the pipeline a micro-operation received from the architectural register file when the mode indicator indicates the second mode.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 9, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 10318304
    Abstract: Methods and conditional branch predictors for predicting an outcome of a conditional branch instruction in a program executed by a processor using a long conditional branch history include generating a first index from a first portion of the conditional branch history and a second index from a second portion of the conditional branch history. The first index is then used to identify an entry in a first pattern history table including first prediction information; and the second index is used to identify an entry in a second pattern history table including second prediction information. The outcome of the conditional branch is predicted based on the first and second prediction information.
    Type: Grant
    Filed: July 25, 2015
    Date of Patent: June 11, 2019
    Assignee: MIPS Tech, LLC
    Inventor: Manouk Vartan Manoukian
  • Patent number: 10209993
    Abstract: A branch predictor has a block address useable to access a block of instruction bytes of an instruction cache and first/second byte offsets within the block of instruction bytes. Hashing logic hashes a branch pattern and respective first/second address formed from the block address and the respective first/second byte offsets to generate respective first/second indexes. A conditional branch predictor receives the first/second indexes and in response provides respective first/second direction predictions of first/second conditional branch instructions in the block of instruction bytes. In one embodiment, a branch target address cache (BTAC) provides the byte offsets, and the first/second direction predictions are statically associated with first/second target addresses also provided by the BTAC.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoling Wang, Mengchen Yang, Guohua Chen
  • Patent number: 10185570
    Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 10133572
    Abstract: A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active threads, and perform a divergent operation on the selected active thread. The divergent operation may be a serial operation.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Evan Gruber, Lin Chen, Yun Du, Alexei Vladimirovich Bourd
  • Patent number: 10114652
    Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu, Alfred T. Watson, III
  • Patent number: 10069855
    Abstract: A method for identifying security vulnerabilities in a third party software component includes generating a test application for the third party software component. The test application is generated such that every externally accessible data path in the third party component is called. The test application and the third party software component are analyzed using a static application security testing (SAST) code analyzer. One or more test results are obtained from the SAST code analyzer. The one or more test results are used to identify security vulnerabilities in the third party component.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 4, 2018
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jeremy W. Long, Mitch Moon
  • Patent number: 10063569
    Abstract: Embodiments of an invention for custom protection against side channel attacks are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive an instruction to provide for shielding code against side channel attacks, wherein the instruction includes a first operand to specify one of a plurality of levels of protection. The execution hardware is to execute the instruction, wherein execution of the instruction includes configuring the processor to provide a specified level of protection.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventor: Paul Caprioli
  • Patent number: 10025329
    Abstract: A method and apparatus adjust portable electronic device operation based on ambient temperature. A user input of a desired performance mode of a portable electronic device can be received. An ambient temperature in an environment surrounding the portable electronic device can be determined. A device temperature mitigation threshold value can be set based on the ambient temperature and based on the desired performance mode. Portable electronic device operation can be adjusted based on the portable electronic device temperature exceeding the device temperature mitigation threshold value.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 17, 2018
    Assignee: Google Technology Holdings LLC
    Inventors: Jiri Slaby, Morris B. Bowers, Itisha C. Deokar
  • Patent number: 10013243
    Abstract: According to an aspect of some embodiments of the present invention there is provided a computerized method of analyzing code of a software program for dominance relationships between a plurality of functions of the software program, the method comprising: receiving source code of a software program, the source code having a plurality of functions; identifying a plurality of intraprocedural dominator graphs each for another of the plurality of functions; combining the plurality of intraprocedural dominator graphs to create an interprocedural dominance graph with edges that logically connect between nodes of the plurality of functions; identifying a plurality of interprocedural dominance relations between nodes in different functions of the plurality of functions using the interprocedural dominance graph; and analyzing the software program according to the plurality of interprocedural dominance relations.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Jonathan Bnayahu, Yishai Feldman
  • Patent number: 9983878
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9977679
    Abstract: An apparatus and method are provided for processing instructions from a plurality of threads. The apparatus comprises a processing pipeline to process instructions, including fetch circuitry to fetch instructions from a plurality of threads for processing by the processing pipeline, and execution circuitry to execute the fetched instructions. Execution hint instruction handling circuitry is then responsive to the fetch circuitry fetching an execution hint instruction for a first thread, to treat the execution hint instruction, at least in a presence of a suspension condition, as a predicted branch instruction with a predicted behavior, and to cause the fetch circuitry to suspend fetching of instructions for the first thread. The execution circuitry is then arranged to execute the predicted branch instruction with a behavior different to the predicted behavior, in order to trigger a misprediction condition.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 22, 2018
    Assignee: ARM Limited
    Inventors: Ian Michael Caulfield, Antony John Penton, Robert Gwilym Dimond
  • Patent number: 9971614
    Abstract: This invention generates, when the application issues a request, the native code of a function required at the timing and registers the native code in a code cache. This makes it possible to perform processing at high speed as long as the function is requested at a timing earlier than the timing of actually executing the function. This apparatus includes an execution unit configured to execute a native code corresponding to a function requested from the application when the native code is stored in a cache memory and to execute the function requested from the application in an interpreter form when the native code is not stored in the cache memory, and a dynamic compilation unit configured to compile, when a compilation request is received from the application, a requested function and record a generated native code in the cache memory.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 15, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takenori Asami
  • Patent number: 9928046
    Abstract: A method, computer program product, and computer system for tracking tuples by ID as the tuples progress through an operator of a chain of operators within a processing element. Dynamic loading may be utilized to load a processing code for the operator in response to invoking fusion for the operator. Ownership of network I/O may be shifted from the operator to a final operator of the chain of operators within the processing element. A tuple ID may be rolled back to a last ID processed by the operator being added into the processing element.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, David M. Koster, Christopher R. Sabotta, Joseph C. Schmidt
  • Patent number: 9910701
    Abstract: A device, such as a constrained device that includes a processing device and memory, schedules user-defined independently executable functions to execute from a single stack common to all user-defined independently executable functions according to availability and priority of the user-defined independently executable functions relative to other user-defined independently executable functions and preempts currently running user-defined independently executable function by placing the particular user-defined independently executable function on a single stack that has register values for the currently running user-defined independently executable function.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 6, 2018
    Assignee: Tyco Fire & Security GmbH
    Inventors: Vincent J. Lipsio, Jr., Paul Rasband
  • Patent number: 9898299
    Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 9882923
    Abstract: An automatic context-sensitive sanitization technique detects errors due to the mismatch of a sanitizer sequence with a browser parsing context. A pre-deployment analyzer automatically detects violating paths that contain a sanitizer sequence that is inconsistent with a browsing context associated with outputting an untrusted input. The pre-deployment analyzer determines a correct sanitizer sequence which is stored in a sanitization cache. During the runtime execution of the web application, a path detector tracks execution of the web application in relation to the violating paths. The correct sanitizer sequence can be applied when the runtime execution follows a violating path.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 30, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventors: David Molnar, Benjamin Livshits, Patrice Godefroid, Prateek Saxena
  • Patent number: 9870466
    Abstract: There is disclosed in one example, a computing apparatus, including: first one or more logic elements providing a code module, the code module comprising a member having a branching policy designating either a public or private member; second one or more logic elements providing a policy engine, operable to: receive a first branch instruction to the member; determine that the branch instructions does not meet the policy; and take a security action. There is also disclosed a method of providing a policy engine, and a computer-readable medium having stored thereon executable instructions for providing a policy engine.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: January 16, 2018
    Assignee: McAfee, Inc.
    Inventors: Carl D. Woodward, Jennifer Eligius Mankin, Jeremy Bennett
  • Patent number: 9830156
    Abstract: One embodiment of the present invention sets forth a technique for optimizing parallel thread execution in a temporal single-instruction multiple thread (SIMT) architecture. When the threads in a parallel thread group execute temporally on a common processing pipeline rather than spatially on parallel processing pipelines, execution cycles may be reduced when some threads in the parallel thread group are inactive due to divergence. Similarly, an instruction can be dispatched for execution by only one thread in the parallel thread group when the threads in the parallel thread group are executing a scalar instruction. Reducing the number of threads that execute an instruction removes unnecessary or redundant operations for execution by the processing pipelines. Information about scalar operands and operations and divergence of the threads is used in the instruction dispatch logic to eliminate unnecessary or redundant activity in the processing pipelines.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 28, 2017
    Assignee: NVIDIA Corporation
    Inventor: Ronny M. Krashinsky