Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) Patents (Class 712/233)
  • Patent number: 10795729
    Abstract: Disclosed is a data accelerated processing system including a processing device, a storage device, an interface device and a control device. The processing device is configured to realize accelerated operation processing of data. The storage device is electrically connected to the processing device for storing the data sent by a server. The interface device is electrically connected to the processing device for data transmission between the processing device and the server. The control device is configured to regulate the status of the processing device. During an operation process, a large number of operating tasks in the server may be transmitted to the processing device for operating through the interface device, and large amounts of buffered data may be stored in the storage device. The data accelerated processing system improves data reading speed and operation efficiency through the cooperation of the processing device, the storage device and the interface device.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 6, 2020
    Assignee: Cambricon Technologies Corporation Limited
    Inventors: Kun Li, Dejing Wang, Shuo Xing
  • Patent number: 10795683
    Abstract: Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting a more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan, Mauricio J. Serrano
  • Patent number: 10782973
    Abstract: A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carlo Bertolli, John Kevin Patrick O'Brien, Alexandre E Eichenberger, Zehra Noman Sura
  • Patent number: 10761855
    Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 10719319
    Abstract: In one embodiment, a processor comprises a decoder to decode a first instruction, the first instruction comprising an opcode and at least one parameter, the opcode to identify the first instruction as an instruction associated with an indirect branch, the at least one parameter indicative of whether the indirect branch is allowed; and circuitry to generate an error message based on the at least one parameter.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Kekai Hu, Ke Sun, Rodrigo Branco
  • Patent number: 10705849
    Abstract: A data processing system includes a multithreaded processor to execute a plurality of selected program threads in parallel. A mode-selectable processor is coupled to the multithreaded processor and executes in either a first mode or a second mode. In the first mode program instructions from a single thread are executed. In the second mode, which is selected when the single program thread is inactive, program instructions forming a plurality of borrowed threads are executed. These borrowed threads are taken from a queue of candidate program threads which is managed by the multithreaded processor.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 7, 2020
    Assignee: The Regents of the University of Michigan
    Inventors: Seyedamirhossein Mirhosseininiri, Thomas Friedrich Wenisch
  • Patent number: 10681076
    Abstract: A method for identifying security vulnerabilities in a third party software component includes generating a test application for the third party software component. The test application is generated such that every externally accessible data path in the third party component is called. The test application and the third party software component are analyzed using a static application security testing (SAST) code analyzer. One or more test results are obtained from the SAST code analyzer. The one or more test results are used to identify security vulnerabilities in the third party component.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jeremy W. Long, Mitch Moon
  • Patent number: 10635655
    Abstract: It is proposed a device and method for finding nilcatenations, and proposes nilcatenation detection techniques, which can be applied to blockchains, and even constitute a proof of useful work, as the periodic removal of nilcatenations keeps a ledger size as small as possible. Banks and blockchains need to keep track of an ever-increasing list of transactions between the accounts owned by their users. However, as time goes by, many of these transactions can be safely “forgotten”, in the sense that purging a set of transactions that compensate each other does not impact the network's semantic meaning i.e. the vector Bt of amounts representing the balances of users at a given point in time t. Nilcatenation refers to a collection of past transaction vectors having no effect on Bt. Removing these transactions yields a smaller, but equivalent set of transactions.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 28, 2020
    Assignee: INGENICO GROUP
    Inventors: David Naccache, Remi Geraud
  • Patent number: 10613842
    Abstract: A computer-implemented method includes receiving an initial control flow graph (CFG) describing a project, where the project includes one or more programs. The initial CFG includes a plurality of graph nodes and a plurality of edges connecting the plurality of graph nodes to one another. Based on first profiling data, a first set of one or more graph nodes of the plurality of graph nodes of the initial CFG is selected as a first set of main nodes. The first profiling data describes a first execution history of the project. The initial CFG is simplified by generating a first final CFG, which includes the first set of main nodes and excludes one or more remaining nodes of the initial CFG that are not in the first set of main nodes.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bao Zhang, Naijie Li, Ming Ran Liu, Yuan Zhai
  • Patent number: 10592244
    Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
  • Patent number: 10564973
    Abstract: A processor fetches instructions from a plurality of threads. Each entry in a branch information storage (BIS) stores a virtual address ID for a branch, information about the branch, and thread ID information. The BIS is accessed using a virtual address of an instruction to be fetched for a thread to determine whether a hit exists, and if so, to obtain the branch information stored in the entry that gave rise to the hit. The virtual address is converted into a physical address, and an address translation regime is specified for each thread. When allocating an entry into the BIS, allocation circuitry determines, for a branch instruction for a current thread, whether the address translation regime is shared by plural threads. If so, the allocation circuitry identifies both the current thread and any other thread for which the address translation regime is shared.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 18, 2020
    Assignee: ARM LIMITED
    Inventors: Alexander Alfred Hornung, Ian Michael Caulfield
  • Patent number: 10564974
    Abstract: A determination is made as to whether an instruction is an affiliation-creating instruction that provides an affiliation between a plurality of registers. Based on determining the instruction is an affiliation-creating instruction, an affiliation is specified. Further, a branch instruction is obtained. The branch instruction is separated from the instruction by one or more instructions. Based on the branch instruction and specifying the affiliation, processing is performed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10528365
    Abstract: A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: January 7, 2020
    Assignee: Imagination Technologies Limited
    Inventors: David William Knox, Michael John Davis, Adrian John Anderson
  • Patent number: 10437597
    Abstract: A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Adam B. Collura, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 10346350
    Abstract: A processor includes an architectural register file loadable with micro-operations by architectural instructions of an architectural instruction set of the processor and an execution unit that executes instructions. The instructions are either architectural instructions or microinstructions into which architectural instructions are translated. The execution unit includes a decoder that decodes the instructions into micro-operations, a mode indicator that indicates one of first and second modes, a pipeline of stages to which are provided micro-operations that control circuits of the stages of the pipeline, and a multiplexer. The multiplexer selects for provision to the pipeline a micro-operation received from the decoder when the mode indicator indicates the first mode and selects for provision to the pipeline a micro-operation received from the architectural register file when the mode indicator indicates the second mode.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 9, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 10318304
    Abstract: Methods and conditional branch predictors for predicting an outcome of a conditional branch instruction in a program executed by a processor using a long conditional branch history include generating a first index from a first portion of the conditional branch history and a second index from a second portion of the conditional branch history. The first index is then used to identify an entry in a first pattern history table including first prediction information; and the second index is used to identify an entry in a second pattern history table including second prediction information. The outcome of the conditional branch is predicted based on the first and second prediction information.
    Type: Grant
    Filed: July 25, 2015
    Date of Patent: June 11, 2019
    Assignee: MIPS Tech, LLC
    Inventor: Manouk Vartan Manoukian
  • Patent number: 10209993
    Abstract: A branch predictor has a block address useable to access a block of instruction bytes of an instruction cache and first/second byte offsets within the block of instruction bytes. Hashing logic hashes a branch pattern and respective first/second address formed from the block address and the respective first/second byte offsets to generate respective first/second indexes. A conditional branch predictor receives the first/second indexes and in response provides respective first/second direction predictions of first/second conditional branch instructions in the block of instruction bytes. In one embodiment, a branch target address cache (BTAC) provides the byte offsets, and the first/second direction predictions are statically associated with first/second target addresses also provided by the BTAC.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoling Wang, Mengchen Yang, Guohua Chen
  • Patent number: 10185570
    Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: January 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 10133572
    Abstract: A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active threads, and perform a divergent operation on the selected active thread. The divergent operation may be a serial operation.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Evan Gruber, Lin Chen, Yun Du, Alexei Vladimirovich Bourd
  • Patent number: 10114652
    Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer, Ken V. Vu, Alfred T. Watson, III
  • Patent number: 10069855
    Abstract: A method for identifying security vulnerabilities in a third party software component includes generating a test application for the third party software component. The test application is generated such that every externally accessible data path in the third party component is called. The test application and the third party software component are analyzed using a static application security testing (SAST) code analyzer. One or more test results are obtained from the SAST code analyzer. The one or more test results are used to identify security vulnerabilities in the third party component.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 4, 2018
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jeremy W. Long, Mitch Moon
  • Patent number: 10063569
    Abstract: Embodiments of an invention for custom protection against side channel attacks are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive an instruction to provide for shielding code against side channel attacks, wherein the instruction includes a first operand to specify one of a plurality of levels of protection. The execution hardware is to execute the instruction, wherein execution of the instruction includes configuring the processor to provide a specified level of protection.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventor: Paul Caprioli
  • Patent number: 10025329
    Abstract: A method and apparatus adjust portable electronic device operation based on ambient temperature. A user input of a desired performance mode of a portable electronic device can be received. An ambient temperature in an environment surrounding the portable electronic device can be determined. A device temperature mitigation threshold value can be set based on the ambient temperature and based on the desired performance mode. Portable electronic device operation can be adjusted based on the portable electronic device temperature exceeding the device temperature mitigation threshold value.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 17, 2018
    Assignee: Google Technology Holdings LLC
    Inventors: Jiri Slaby, Morris B. Bowers, Itisha C. Deokar
  • Patent number: 10013243
    Abstract: According to an aspect of some embodiments of the present invention there is provided a computerized method of analyzing code of a software program for dominance relationships between a plurality of functions of the software program, the method comprising: receiving source code of a software program, the source code having a plurality of functions; identifying a plurality of intraprocedural dominator graphs each for another of the plurality of functions; combining the plurality of intraprocedural dominator graphs to create an interprocedural dominance graph with edges that logically connect between nodes of the plurality of functions; identifying a plurality of interprocedural dominance relations between nodes in different functions of the plurality of functions using the interprocedural dominance graph; and analyzing the software program according to the plurality of interprocedural dominance relations.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Jonathan Bnayahu, Yishai Feldman
  • Patent number: 9983878
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9977679
    Abstract: An apparatus and method are provided for processing instructions from a plurality of threads. The apparatus comprises a processing pipeline to process instructions, including fetch circuitry to fetch instructions from a plurality of threads for processing by the processing pipeline, and execution circuitry to execute the fetched instructions. Execution hint instruction handling circuitry is then responsive to the fetch circuitry fetching an execution hint instruction for a first thread, to treat the execution hint instruction, at least in a presence of a suspension condition, as a predicted branch instruction with a predicted behavior, and to cause the fetch circuitry to suspend fetching of instructions for the first thread. The execution circuitry is then arranged to execute the predicted branch instruction with a behavior different to the predicted behavior, in order to trigger a misprediction condition.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 22, 2018
    Assignee: ARM Limited
    Inventors: Ian Michael Caulfield, Antony John Penton, Robert Gwilym Dimond
  • Patent number: 9971614
    Abstract: This invention generates, when the application issues a request, the native code of a function required at the timing and registers the native code in a code cache. This makes it possible to perform processing at high speed as long as the function is requested at a timing earlier than the timing of actually executing the function. This apparatus includes an execution unit configured to execute a native code corresponding to a function requested from the application when the native code is stored in a cache memory and to execute the function requested from the application in an interpreter form when the native code is not stored in the cache memory, and a dynamic compilation unit configured to compile, when a compilation request is received from the application, a requested function and record a generated native code in the cache memory.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 15, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takenori Asami
  • Patent number: 9928046
    Abstract: A method, computer program product, and computer system for tracking tuples by ID as the tuples progress through an operator of a chain of operators within a processing element. Dynamic loading may be utilized to load a processing code for the operator in response to invoking fusion for the operator. Ownership of network I/O may be shifted from the operator to a final operator of the chain of operators within the processing element. A tuple ID may be rolled back to a last ID processed by the operator being added into the processing element.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, David M. Koster, Christopher R. Sabotta, Joseph C. Schmidt
  • Patent number: 9910701
    Abstract: A device, such as a constrained device that includes a processing device and memory, schedules user-defined independently executable functions to execute from a single stack common to all user-defined independently executable functions according to availability and priority of the user-defined independently executable functions relative to other user-defined independently executable functions and preempts currently running user-defined independently executable function by placing the particular user-defined independently executable function on a single stack that has register values for the currently running user-defined independently executable function.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 6, 2018
    Assignee: Tyco Fire & Security GmbH
    Inventors: Vincent J. Lipsio, Jr., Paul Rasband
  • Patent number: 9898299
    Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 9882923
    Abstract: An automatic context-sensitive sanitization technique detects errors due to the mismatch of a sanitizer sequence with a browser parsing context. A pre-deployment analyzer automatically detects violating paths that contain a sanitizer sequence that is inconsistent with a browsing context associated with outputting an untrusted input. The pre-deployment analyzer determines a correct sanitizer sequence which is stored in a sanitization cache. During the runtime execution of the web application, a path detector tracks execution of the web application in relation to the violating paths. The correct sanitizer sequence can be applied when the runtime execution follows a violating path.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 30, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventors: David Molnar, Benjamin Livshits, Patrice Godefroid, Prateek Saxena
  • Patent number: 9870466
    Abstract: There is disclosed in one example, a computing apparatus, including: first one or more logic elements providing a code module, the code module comprising a member having a branching policy designating either a public or private member; second one or more logic elements providing a policy engine, operable to: receive a first branch instruction to the member; determine that the branch instructions does not meet the policy; and take a security action. There is also disclosed a method of providing a policy engine, and a computer-readable medium having stored thereon executable instructions for providing a policy engine.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: January 16, 2018
    Assignee: McAfee, Inc.
    Inventors: Carl D. Woodward, Jennifer Eligius Mankin, Jeremy Bennett
  • Patent number: 9830156
    Abstract: One embodiment of the present invention sets forth a technique for optimizing parallel thread execution in a temporal single-instruction multiple thread (SIMT) architecture. When the threads in a parallel thread group execute temporally on a common processing pipeline rather than spatially on parallel processing pipelines, execution cycles may be reduced when some threads in the parallel thread group are inactive due to divergence. Similarly, an instruction can be dispatched for execution by only one thread in the parallel thread group when the threads in the parallel thread group are executing a scalar instruction. Reducing the number of threads that execute an instruction removes unnecessary or redundant operations for execution by the processing pipelines. Information about scalar operands and operations and divergence of the threads is used in the instruction dispatch logic to eliminate unnecessary or redundant activity in the processing pipelines.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 28, 2017
    Assignee: NVIDIA Corporation
    Inventor: Ronny M. Krashinsky
  • Patent number: 9824214
    Abstract: This invention teaches a system and methods of detecting software vulnerabilities in a computer program by analyzing the compiled code and optionally the source code of the computer program. The invention models compiled software to examine both control flow and data flow properties of the target program. A comprehensive instruction model is used for each instruction of the compiled code, and is complemented by a control flow graph that includes all potential control flow paths of the instruction. A data flow model is used to record the flow of unsafe data during the execution of the program. The system analyzes the data flow model and creates a security finding corresponding to each instruction that calls an unsafe function on unsafe data. The security findings are aggregated in a security report. The system further uses precomputation to improve performance by caching 1-to-many data flow mapping for each basic block in the code.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 21, 2017
    Assignee: SECURISEA, INC.
    Inventor: Joshua M. Daymont
  • Patent number: 9715593
    Abstract: This invention discloses a system and methods of detecting software vulnerabilities in a computer program. The invention models compiled software to examine both control flow and data flow properties of the target program. A comprehensive instruction model is used for each instruction of the compiled code, and is complemented by a control flow graph that includes all potential control flow paths of the instruction. A data flow model is used to record the flow of unsafe data during the execution of the program. The system analyzes the data flow model and creates a security finding corresponding to each instruction that calls an unsafe function on unsafe data. These security findings are aggregated in a security report along with the corresponding debug information, remediation recommendations and any ancillary information related to each instruction that triggered the security finding.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 25, 2017
    Assignee: SECURISEA, INC.
    Inventor: Joshua M. Daymont
  • Patent number: 9678866
    Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 13, 2017
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 9659168
    Abstract: A method of generating identification data for identifying software is disclosed. The method includes executing said software so as to alter one or more addresses of a memory stack reserved in memory for execution of the software. Identification data is then generated for identifying the software based on the one or more altered addresses of the memory stack.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: May 23, 2017
    Assignee: NXP B.V.
    Inventor: Arnaud Collard
  • Patent number: 9639361
    Abstract: A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behavior of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 2, 2017
    Assignee: ARM LIMITED
    Inventors: Paul Anthony Gilkerson, John Michael Horley
  • Patent number: 9632780
    Abstract: A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lisa C. Heller
  • Patent number: 9612881
    Abstract: Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 4, 2017
    Assignee: NXP USA, Inc.
    Inventor: Graham Edmiston
  • Patent number: 9606850
    Abstract: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 28, 2017
    Assignee: ARM Limited
    Inventors: John Michael Horley, Simon John Craske
  • Patent number: 9563430
    Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Daniel Lipetz, Brian R. Prasky, Anthony Saporito
  • Patent number: 9495237
    Abstract: Corruption of call stacks is detected by using guard words placed in the call stacks. A called function executing on a processor of a computing environment checks a guard word in a stack frame of a calling function. The checking determines whether the guard word has an expected value. Based on determining the guard word has an unexpected value, an indication of corruption of the stack frame is provided.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Ronald I. McIntosh
  • Patent number: 9483391
    Abstract: According to one general aspect, a method may include monitoring the execution of at least a portion of a software application. The method may also include collecting subroutine call information regarding a plurality of subroutine calls included by the portion of the software application, wherein one or more of the subroutine calls is selected for detailed data recording. The method may further include pruning, as the software application is being executed, a subroutine call tree to include only the subroutine calls selected for detailed data recording and one or more parent subroutine calls of each subroutine calls selected for detailed data recording.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: November 1, 2016
    Assignee: Identify Software Ltd.
    Inventors: Eyal Koren, Asaf Dafner, Shiri Semo Judelman
  • Patent number: 9477478
    Abstract: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 25, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kulin N. Kothari, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Daren Eugene Streett
  • Patent number: 9465746
    Abstract: Gathering diagnostics during a transactional execution in a transactional memory environment, a transactional memory environment for performing transactional executions is provided. Included is identifying a first indicator, by a computer system, signaling a beginning instruction of a transaction comprising a plurality of instructions; generating, by the computer system, a computed digest based on the execution of at least one of the plurality of instructions; accumulating, by the computer system, a diagnostic data of the transaction based on the execution of the plurality of instructions; identifying, by the computer system, a second indicator associated with the plurality of instructions signaling an ending instruction of the transaction comprising the plurality of instructions; and based on an abort of the transaction, not saving the memory store data of the transaction to memory.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura
  • Patent number: 9460020
    Abstract: Gathering diagnostics during a transactional execution in a transactional memory environment, a transactional memory environment for performing transactional executions is provided. Included is identifying a first indicator, by a computer system, signaling a beginning instruction of a transaction comprising a plurality of instructions; generating, by the computer system, a computed digest based on the execution of at least one of the plurality of instructions; accumulating, by the computer system, a diagnostic data of the transaction based on the execution of the plurality of instructions; identifying, by the computer system, a second indicator associated with the plurality of instructions signaling an ending instruction of the transaction comprising the plurality of instructions; and based on an abort of the transaction, not saving the memory store data of the transaction to memory.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura
  • Patent number: 9454659
    Abstract: This invention teaches a system and methods of detecting software vulnerabilities in a computer program by analyzing the compiled code and optionally the source code of the computer program. The invention models compiled software to examine both control flow and dataflow properties of the target program. A comprehensive instruction model is used for each instruction of the compiled code, and is complemented by a control flow graph that includes all potential control flow paths of the instruction. A data flow model is used to record the flow of unsafe data during the execution of the program. The system analyzes the data flow model and creates a security finding corresponding to each instruction that calls an unsafe function on unsafe data. These security findings are aggregated in a security report along with the corresponding debug information, any ancillary information, remediation recommendations and the optional source code information for each instruction that triggered the security finding.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 27, 2016
    Assignee: SECURISEA, INC.
    Inventor: Joshua M. Daymont
  • Patent number: 9442755
    Abstract: A method and a system are provided for hardware scheduling of indexed barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated and when each thread reaches the barrier instruction, the thread pauses execution of the instructions. A first sub-group of threads in the plurality of threads is associated with a first sub-barrier index and a second sub-group of threads in the plurality of threads is associated with a second sub-barrier index. When the barrier instruction can be scheduled for execution, threads in the first sub-group are executed serially and threads in the second sub-group are executed serially and at least one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 13, 2016
    Assignee: NVIDIA Corporation
    Inventors: John Erik Lindholm, Tero Tapani Karras
  • Patent number: 9430236
    Abstract: Embodiments relate to code stack management. An aspect includes a processor configured to execute a software application. Another aspect includes a code stack memory area and a data stack memory area, the code stack memory area being separate from the data stack memory area. Another aspect includes maintaining a data stack in the data stack memory area, the data stack comprising a plurality of stack frames comprising one or more data variables corresponding to the execution of the software application. Another aspect includes maintaining a code stack in the code stack memory area, the code stack comprising a plurality of code stack entries comprising executable computer code corresponding to the execution of the software application.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind