Abstract: A loop control circuit of the present invention includes a program counter for sequentially indicating an address of an instruction, a LSA calculation circuit for calculating a loop start address of a loop start instruction, a LEA calculation circuit for calculating a loop end address of a loop end instruction, an interlock generation circuit for generating an interlock until a pipeline of a loop instruction is completed so as to suspend a pipeline process of the loop end instruction, and a loop end evaluation circuit for setting the program counter to the loop start address according to a result of a comparison between the program counter and the loop end address after the pipeline process of the loop instruction is completed.

Abstract: According to one embodiment of the invention, an apparatus is provided which includes a first register to hold an initial value of a first index associated with a looping instruction to be executed for a number of iterations, a second register to hold an initial value of a second index associated with the respective looping instruction, and a third register to hold data indicating non-linear variation pattern associated with the second index. For each iteration, actual increment of the first index and actual increment of the second index are set based on a target increment and the data indicating the non-linear variation pattern associated with the second index.

Abstract: A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

Abstract: Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.

Abstract: A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

Abstract: This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number “;lx” and an iteration identifier “;ix” attached thereto. The line number “;lx” specifies a source code from which the instruction is generated, and the iteration identifier “;ix” specifies an iteration to which the instruction belongs. When the user sets a breakpoint at an instruction, displayed in the windows are (a) a source code for generating the instruction at the breakpoint and (b) another source code for generating another instruction that belongs to a different group of iteration-forming instructions than the breakpoint instruction.

Abstract: A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction stream; interleaving p steams of instances of the instruction in the pipeline; detecting an end of the iteration; and combining results obtained from the p streams after all programmed iterations have completed. A computational circuit comprises a register which can hold a value representing both an operand and result of an iterative operation; a multiplexer having a first input connected to receive the operand from the register, a second input connected to a source of an identify value for the iterative operation, and an output; and an operator circuit having an input connected to receive a value from the multiplexer output, and an output connected to return thee result to the register.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: A REPEAT instruction for repeated execution of an associated instruction (INSTR). Once a program counter stores the address for the instruction to be repeated, it remains unchanged until the associated instruction (INSTR) has been executed the number of times indicated by a COUNT value in a preloaded register, or alternatively, by the REPEAT instruction itself. In this manner, the present invention reduces the number of instruction fetches required to repeatedly execute the associated instruction (INSTR). Consequently, there is a significant improvement in the efficiency of the program code execution.

Abstract: Parallelization of loops is performed for loops having indirect loop index variables and embedded conditional statements in the loop body. Loops having any finite number of array variables in the loop body, and any finite number of indirect loop index variables can be parallelized. There are two particular limitations of the described techniques: (i) that there are no cross-iteration dependencies in the loop other than through the indirect loop index variables; and (ii) that the loop index variables (either direct or indirect) are not redefined in the loop body.

Abstract: The present invention relates to a processor system. The processor system is made up of a multithread control unit for selectively making switching among said threads to be executed in an arithmetic unit, a loop predicting unit for predicting a loop of an instruction string on the basis of a processing history of a branch instruction in the thread, and a loop detecting unit for, when the loop predicting unit predicts the loop, detecting the loop on the basis of an instruction. When the loop detecting unit detects the loop, the multithread control unit making the switching from the thread, which is in execution in the arithmetic unit, to a different thread. This prevents a wait condition stemming from the loop from interfering with the execution of other threads without retouching software.

Abstract: A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.

Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed.

Abstract: A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts storing normal instructions. The instruction buffer dispatches a VLIW instruction composed of n pieces of normal instructions to execution units each time n pieces of instructions are stored therein. The execution units concurrently execute the instructions. After all instructions comprised in a loop have been stored in the buffer and once dispatched as VLIW instructions to be executed, the loop is executed repeatedly.

Abstract: A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of a given loop. The loop predictor may also have one or more running counters to hold a count of the times that the stew value has repeated during the execution of the present loop. When the counter values match the predictor may issue a prediction that the loop will end.

Abstract: A method and apparatus for loop detection for improved branch prediction accuracy. In one embodiment, the method may comprise executing a branch instruction, updating a plurality of event counts corresponding to the branch instruction in response to its executing, determining a loop behavior status corresponding to the branch instruction in response to the event count updating, and promoting the branch instruction to a loop branch prediction type in response to the determination of loop behavior status.

Abstract: Methods and apparatus are disclosed for improved loop unrolling by a compiler. A large class of loops exists for which effective loop unrolling has not previously been performed because they are too large to be completely unrolled, but which do not have a single hot trace that covers an entire loop iteration. The present invention recognizes such loops that have partial hot traces identified using profile data. A set of instructions which constitute a proper superset of the hot trace and a proper subset of the entire loop, and which forms a complete loop iteration is identified. This set of instructions can then be unrolled without unrolling the entire loop.

Abstract: A system for optimizing computer code generation by carrying out interprocedural dead store elimination. The system carries out a top down traversal of a call graph in an intermediate representation of the code being compiled. Live on exit (LOE) sets are defined for variables at call points for functions in the code being compiled. Bit vectors representing the LOE sets for call points for functions are stored in an LOE table indexed or hashed by call graph edges. For each function definition reached in the call graph traversal, a LOE set for the function itself is generated by taking the union of the LOE call point sets. The entries in the LOE table for the LOE call point sets are then removed. The LOE set for each function is used to determine if variables that are the subject of a store operation in a function may be subject to a dead store elimination optimization.

Abstract: A method and an apparatus for reading instruction codes and for forwarding the corresponding instructions to the instruction unit that are distinguished, in particular, by buffer-storing the instructions of program loops that do not exceed the storage capacity of the instruction FIFO, in full, in the instruction FIFO. During a “loop mode”, such program loops are then executed only from the instruction FIFO itself and the instructions do not need to be repeatedly reloaded from the memory. This loop mode is then maintained until the jump instruction at the end of the program loop finally refers to an instruction other than that at the start of the loop.

Abstract: For use in a processor having an external memory interface, an instruction prefetch mechanism, a method of prefetching instructions and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a branch predictor that predicts whether a branch is to be taken, (2) prefetch circuitry, coupled to the branch predictor, that prefetches instructions associated with the branch via the external memory interface if the branch is taken and prefetches sequential instructions via the external memory interface if the branch is not taken and (3) a loop recognizer, coupled to the prefetch circuitry, that determines whether a loop is present in fetched instructions and reinstates a validity of instructions in the loop and prevents the prefetch circuitry from prefetching instructions outside of the loop until the loop completes execution.

Abstract: A loop control circuit and a loop control method that allow control on multiplexed loop operations to be executed with less overhead are provided. A loop control circuit comprises a means for address storage that stores in memory the address of a loop instruction at a second or subsequent stage in multiplexed loops or the address of the instruction immediately preceding the loop instruction when the loop instruction is executed for the first time, a means for loop instruction recurrence prediction that predicts a recurrence of the loop instruction at the second or subsequent stage by comparing the address of the loop instruction or the address of the instruction immediately preceding the loop instruction stored in memory with a value at a program counter and a means for loop instruction skipping that skips the loop instruction if it is predicted that the loop instruction is to occur next.

Abstract: A data processor apparatus having first and second instruction storages for holding a series of instructions to be executed reiteratively. The number of instructions is calculated based on the difference between a start address and an end address respectively stored in a start address register and an end address register. When the number of instructions constituting the series of instructions is less than the capacity of the second instruction storage, the series of instructions is read from the second instruction storage and executed. When the number of instructions is greater than the capacity of the second instruction storage, the series of instructions is read from the first instruction storage.

Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

Abstract: A method and system for enabling tracing of a repeat instruction are provided. A repeat instruction is executed within a processor. In response to detecting a repeat instruction flag set during a last execution of the repeat instruction, an interrupt is initiated within the processor. The processor enables reading a count of executions for the repeat instruction from a storage unit within the processor by a trace program or external hardware during the interrupt.

Abstract: A method and a system for scheduling a software pipelined loop with indirect loads. The system may include a data structure in communication with a processor and a memory. The processor may determine a condition associated with a potential for saturation of the data structure. Accordingly, the processor may provide a number of instructions associated with the software pipelined loop from the memory to a queue of the data structure prior to processing of the instructions by the processor based on the condition associated with a potential for saturation of the data structure.

Abstract: A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the processor includes a shadow ECX register operating in parallel with an architectural ECX count register. This enables the contents of the architectural ECX register, which are also stored in the shadow ECX register, to be immediately transferred to an internal count register from the shadow ECX register upon the first iteration of a repeat string micro code sequence.

Abstract: A system for performing matrix operations utilizes a processor, memory, and a matrix operation manager. The processor has a memory cache. The memory is external to the processor and stores first and second matrices. The matrix operation manager is configured to mathematically combine the first matrix with the scond matrix utilizing a hoisted matrix algorithm for hoisting values of the first matrix, and the hoisted matrix algorithm has an outer loop and an inner loop that is performed to completion for each iteration of the outer loop. The matrix operation manager, for each iteration of the outer loop, is configured to load to the cache and to write to a contiguous portion of the memory, before performing the inner loop, values from the first matrix that are to be combined, via performance of the inner loop, with values from the second matrix.

Abstract: A signal processor including a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory and an external memory provided external to the processor. In the signal processor, the process execution unit automatically returns to a start point of a loop-type data at an end of the loop-type data and sequentially reads out the loop-type data from the external memory to the cache memory.

Abstract: An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an initial instruction that is programmed at a start of the loop, and stores an identification of a different instruction that is programmed between the initial instruction and the particular instruction. According to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, the system initiates an additional fetch of the initial instruction.

Abstract: A comparator 172 compares the value held in an RPT_B register 171 with the address of the instruction which is held in an IA register 181 and is to be fetched next, and outputs coincidence information indicating whether these value coincide with each other. Based on the coincidence information, a control part 112 generates hardware-wise a control signal for switching an instruction processing sequence to the next instruction of a repeat block in the last repeat processing of the repeat block.

Abstract: An embodiment of the invention is a processor for processing loop branch instructions. The processor includes an instruction unit for fetching and decoding instructions including at least one loop branch instruction. A branch prediction unit predicts target instructions to be fetched and decoded by the instruction unit in response to the loop branch instruction. An execution unit executes instructions from the instruction unit and maintains a counter indicating an iteration of a loop. The execution unit includes detection logic for detecting when the counter equals a threshold and notifies the branch prediction unit when the counter equals the threshold.

Abstract: According to one embodiment, a processing element is disclosed. The processing element includes an instruction buffer, a first most often (MO) buffer coupled to the instruction buffer and an execution unit coupled to the instruction buffer and the first MO buffer. The execution unit is adaptable to execute instructions stored within the first MO buffer based upon a first predetermined profile.

Abstract: A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the content of the repeat count register, and to modify the content of the repeat count register. The repeat instruction comprises two parts, the first of which initializes the repeat count index register and initiates repeat of a subsequent instruction, and the second part of which modifies the content of the repeat count register.

Abstract: A branch prediction method using an address trace is described. An address trace corresponding to an executed instruction is stored itself with a decoded form. After appointing a start address and an end address of a repeated routine, current routine iteration count and total number of iterations are compared with each other, confirming the end of the routine and storing address information of the next routine. Therefore, access information of the repeated routine can be stored using a small amount of trace cache.

Abstract: A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

Abstract: A digital system is provided with means and methods for executing an instruction type wherein context information that pertains to that type instruction is automatically saved and restored during execution of the instruction type.

Abstract: A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruction may include an address of a register which holds the loop count value. The instruction immediately following the repeat instruction is the target instruction for repetition. The processing includes repeating execution of the target instruction according to the loop count value in a low processor cycle overhead manner. The processing may also include handling interrupts during repeat instruction processing in a low-overhead manner during the initial call of the interrupt service routine as well as upon returning from the interrupt service routine.

Abstract: A pattern generator includes an address generator, an address topology generator, and a data topology generator. The address generator is adapted to provide a first address having a plurality of address bits. The address topology generator includes a first plurality of programmable logic gates. Each programmable logic gate of the first plurality is coupled to receive at least a subset of the plurality of address bits. The first plurality of programmable logic gates generate a second address having a plurality of modified address bits. The data topology generator is adapted to receive at least a subset of the plurality of modified address bits and generate write data based on the subset of modified address bits. A method for generating a pattern includes generating a first address having a plurality of address bits. A second address having a plurality of modified address bits is generated. The second address is a programmable combination of subsets of the address bits.

Abstract: A method of executing loops in a computer system is described. The computer system has a sequence of instructions held in program memory and a prefetch buffer which holds instructions fetched from the memory ready for supply to a decoder of the computer system. If the size of the loop to be executed is such that it can by holly contained within the prefetch buffer, this is detected and a lock is put on the prefetch buffer to retain the loop within it while the loop is executed a requisite number of times. This thus allows power to be saved and reduces the overhead on the memory access buffers. According to another aspect, loops can be “skipped” by holding a value of zero in the loop counter register.

Abstract: A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating an initiation interval time (IN) for a pipelined stage of the loop. A loop operation time latency (Tld) and a number of loop operations (Np) from the pipelined stages to peel based on IN and Tld is then determined. The loop operation is peeled Np times and copied before the loop in the software code. A vector of registers is allocated and the results of the peeled loop operations and a result of an original loop operation is assigned to the vector of registers. Memory addresses for the results of the peeled loop operations and original loop operation are also assigned.

Abstract: A data processing device having a central processing unit for fetching instructions from a program memory, decoding the instructions and sending a signal to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal; and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, and wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.

Abstract: A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.

Abstract: Register adjustment is performed based on adjustment values determined at multiple stages within a pipeline of a processor. In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.

Abstract: The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.

Abstract: In one embodiment, a programmable processor is adapted to include loop hardware to increase processing speed without significantly increasing power consumption. During a first pass through a loop, a first subset of a sequence of instructions may be loaded into the loop hardware. Then, during subsequent passes through the loop the first subset may be issued from the loop hardware while a second subset is retrieved from a memory device. In this manner, the second subset may be issued with no additional penalty after the first subset has been issued.

Abstract: A data processing device having a PC controlling part for executing an operation of branch which has a first register for holding a result of decoding in an instruction decode unit, a register for holding a description indicating an execution condition of the operation (a value of field for designating condition), and a register for holding the description indicating a time for executing the operation (an address value of PC), wherein the execution condition is started when a value held in the register is in agreement with a PC value in accordance with the description of the register; and if the condition is satisfied, the PC controlling part executes the operation based on a content held in the register, whereby it is possible to delay the time for judging the execution condition during this delay, to thereby increase a degree of freedom in scheduling instructions such that the branch instruction is positioned prior to the operation instruction for determining the execution condition in the program.

Abstract: The invention presents a method for processing data in a processor having a processor core for processing a command in a pipeline form. The method comprises the steps of setting a repeat count value; executing a repeat block command to set a repeat ending address and a repeat starting address; comparing the repeat ending address and a memory address of the second command to identify whether they are identical to each other; checking whether the first command is a command for nonlinearly changing an executing order of a program if the repeat ending address and the memory address of the second command are identical to each other; and storing the memory address of the second command while not reducing the repeat count value if the first command is a command for nonlinearly changing the executing order of the program.

Abstract: A data processing system is provided with a digital signal processor which has an instruction for conditionally branching based on the contents of a specified test register. Each time a branch is taken, the register is decremented as a side effect of executing the branch instruction. In addition, a predicate register is specified by the instruction. A branch occurs only if both registers meet specified conditions.

Abstract: Optimizing compiler performance by applying data speculation within modulo scheduled loops to achieve a higher degree of instruction-level parallelism. The compiler locates a schedule for specifying an order of execution of the instructions and allocates rotating registers for the instruction execution. Based upon the schedule and the register allocation, the compiler determines an initiation interval specifying a number of instruction issue cycles between initiation of successive iterations related to the scheduling of the instructions.

Abstract: A processor that efficiently obtains target path instructions in the presence of tight program loops includes at least one execution unit for executing instructions and instruction sequencing logic that supplies instructions to the at least one execution unit for execution. The instruction sequencing logic includes an instruction fetch buffer and a branch prediction unit including a branch target cache. In response to prediction of a branch instruction as taken, the branch target cache causes multiple copies of a target instruction group to be loaded into the instruction fetch buffer under the assumption that the branch instruction is a member of the target instruction group. Thereafter, the branch target cache causes all but one of the multiple copies to be canceled from the instruction fetch buffer prior to dispatch if the branch instruction does not belong to the target instruction group.