Abstract: A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

Abstract: An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of the function code, and a redirection to a hook function is inserted at a target entry point within the called function. The access state of the processor may then be restored, and the hook function is executed in place of or in conjunction with the called function.

Abstract: A microcomputer has a built-in memory and is accessible to an external memory. The microcomputer executes a specific area branch instruction “JM” as an executable instruction. The specific area branch instruction “JM” is a branch instruction restricted to jump to only a specific area of a memory space and is a single instruction having a minimum instruction length. The microcomputer allocates at least one of a real arithmetic subroutine, an integer division subroutine, and a bit handling subroutine to the specific area. A program of this microcomputer is configured to jump to the selected subroutine allocated to the specific area in response to the specific area branch instruction “JM”. Accordingly, the required program size can be reduced. When the programs are stored in the external memory, it becomes possible to suppress an increase of the execution time which is required for invoking each of the subroutines.

Abstract: A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store an address previously first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run.

Abstract: An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro instructions in the same clock cycle as the pairing if a resource conflict or operand dependency is detected. The apparatus includes multiplexing logic that feeds back a second of a pair of micro instructions stored in an instruction register back into the instruction register for sequential execution after the first micro instruction if a translator detects late in the clock cycle that a resource conflict or operand dependency exists. An instruction pair indicator is provided along with the pair of micro instructions down to the execution stages to inform the execution stages whether the second micro instruction is valid for parallel execution with the first micro instruction. The method may also be used in conjunction with a micro instruction queue.

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract: A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one embodiment, the special function invoked may be a feature of the processor not included in the processor's publicly known instruction set. In another embodiment, the special function invoked may cause a set of instructions to be transferred from a memory external to the processor to a memory in the processor. In such an embodiment, the method and apparatus include authenticating and decrypting the instructions before transferring from the memory external to the processor to the memory in the processor. In such an embodiment, the method and apparatus may be used for upgrading microcode within a processor by executing the special RISC instruction stored on a writeable non-volatile memory located external to the processor.

Abstract: An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of floating point operations common to most floating point software algorithms where floating point exchange operations appear as every other instruction between floating point computational instructions. The apparatus includes translation logic, that pairs the operations directed by a floating point macro instruction and a floating point exchange macro instruction by generating a micro instruction with an exchange extension. The exchange extension directs the microprocessor to perform the floating point exchange operation in parallel with the operation prescribed by the floating point macro instruction within a single floating point unit.

Abstract: A serial communication system, which can improve a communication speed even when it takes long time to perform a process in accordance with a command. A serial communication apparatus includes a first and a second microcomputer, each of which has a relationship of a master/a slave. Each of the first and the second microcomputer has a CPU, a ROM, a RAM, a communication control portion, a serial communication block and so on. A serial communication clock (SCLK) is continuously sent from the first microcomputer to the second microcomputer. The serial communication block of each of the microcomputers has a pair of exchangeable shift registers. Each of the communication control portions reads a signal (SRXD) sent from the opposite side microcomputer by 16 clocks, and performs processes based on a process command in the read signal (SRXD) during the next 16 clocks.

Abstract: The invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs). To improve data throughput in applications with high memory access rates, the ASIC contains a TASK scheduler, which is implemented as hardware and which chronologically coordinates, in an appropriate manner, the processing of different TASKs on an ASIC internal processing means (EXU). Compared to conventional software control units for multitasking systems, this TASK scheduler which is implemented as hardware offers the advantage, among others, that the operating system is relieved of load, and an expensive memory architecture is not required.

Abstract: Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.

Abstract: A microprocessor includes a first memory to store microcode and a second memory to store predicted micro-operation addresses. Micro-operation addresses are predicted, stored in memory, and retrieved to get the next micro-operations from the microcode memory. Misprediction recovery logic is used to determine if the next predicted address is correct and to determine a recovery address to correct the predicted address if the predicted address is incorrect.

Abstract: A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of instruction is evaluated. Responsive to the one-of instruction control, a next instruction pointer is generated. A one-of-and-jump instruction is evaluated. Responsive to the one-of-and-jump instruction control, a first next instruction pointer and a second next instruction pointer are generated. The second next instruction pointer is a destination instruction pointer for the one-of-and-jump instruction.

Abstract: A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Abstract: A data processing system comprises means for identifying and replacing instructions to jump to functions having known prolog instructions with modified jump instructions, means for storing the known prolog instructions, and means for retrieving the known prolog instructions when such modified instructions are found and for supplying the known prolog instructions for processing. A compiler or preprocessor is arranged to detect and modify the jump instructions. A logic module is arranged to intercept the modified instructions, retrieve from its storage the prolog instructions, and supply the prolog instructions for processing. The compiler or preprocessor is further arranged to detect and modify the first instruction of known epilog code. A logic module is arranged to intercept the modified instruction, and to retrieve and supply for processing the epilog instructions.

Abstract: An apparatus and method for correcting a call/return stack internal to a microprocessor is provided. In the case of a call, the microprocessor pushes the return address onto the internal call/return stack and in the case of a return, the microprocessor pops the return address from the internal call/return stack into the instruction register. However, prior to speculative execution of the call or return, the correction apparatus stores correction information to enable correction of the internal call/return stack. If the conditional branch instruction was mispredicted, the correction apparatus corrects the internal call/return stack based on the correction information previously stored. The correction information is stored in stack memories so that corrections can be made in the reverse order of which the incorrect modifications to the internal call/return stack were made.

Abstract: A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application.

Abstract: A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address identifying an entry point address for a corresponding subroutine; and a first table second address identifying a return address of a return for the corresponding subroutine. A second table of entries is also maintained. Each entry in the second table includes: a second table first address identifying a return address of a return for a respective subroutine called by a corresponding subroutine call instruction; a second table second address identifying a target address of the return for the respective subroutine; and a second table third address identifying an entry point address for the respective subroutine. It is determined whether the second table stores an entry whose second table first address corresponds to a return address of a return for a considered subroutine.

Abstract: A microprocessor is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address. These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The microprocessor may continue to predict return addresses correctly following a mispredicted branch instruction.

Abstract: A method of compressing programs, especially those used in embedded systems, is provided which allows greater program compression without significantly degrading system performance. The method provides: first, examining an entire program for sequences of lines of code, which may or may not constitute basic blocks; determining which sequences are identical or are identical except for a variation in a predetermined number of Elements within the sequence; designating and saving one uncompressed version of the identified sequences in memory as a specific microroutine, saving the Elements which differentiate the saved sequence from the various nearly identical sequences; and, assembling a version of the program consisting of original lines of code and microcalls. The microcall is a line of code which instructs a processor to implement a previously saved microroutine and provides an indication as to which Elements in the microroutine are to be replaced and where to find the substitute Elements.

Abstract: A method and apparatus for reducing the amount of data copied during process switches. A method for reducing the amount of data copied during process switches is provided. In response to a processor performing a process switch to a process, a first write indication corresponding to the process is stored to indicate a first register file in the processor should not be saved. In response to the process causing the processor to write to the first register file, the first write indication is altered to indicate the first register file should be saved. In response to the processor performing a process switch from the process, a first value stored in the first register file is copied into a storage device accessible by the processor if the first write indication indicates the first register file should be saved.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.

Abstract: A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Abstract: A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.

Abstract: A method for performing 16 Bit BIOS interrupt calls under a 32 Bit protected mode application. This has been impossible to-date and has forced BIOS development teams to add support into the BIOS for 32 bit function calls from 32 bit applications.

Abstract: A microprocessor is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address. These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The microprocessor may continue to predict return addresses correctly following a mispredicted branch instruction.

Abstract: A return stack buffer mechanism that uses two separate return stack buffers is disclosed. The first return stack buffer is the Speculative Return Stack Buffer. The Speculative Return Stack Buffer is updated using speculatively fetched instructions. Thus, the Speculative Return Stack Buffer may become corrupted when incorrect instructions are fetched. The second return stack buffer is the Actual Return Stack Buffer. The Actual Return Stack Buffer is updated using information from fully executed branch instructions. When a branch misprediction causes a pipeline flush, the contents of the Actual Return Stack Buffer is copied into the Speculative Return Stack Buffer to correct any corrupted information.