Abstract: A topology of accelerators is provided, including a plurality of accelerators and a broadcast buffer. Each of the plurality of accelerators corresponds to a first memory and obtain input data from an external second memory respectively, wherein the accelerator can only directly access its corresponding first memory, and the broadcast buffer is coupled between one of the plurality of accelerators and the corresponding first memory. When receiving a write command and the input data from the accelerator to which it is coupled, the broadcast buffer is configured to write the input data into the corresponding first memory according to the write command, and when broadcast is enabled, the broadcast buffer is configured to broadcast the write command and the weight data in the input data. This application can improve the access performance of the accelerators and reduce the access delay.

Abstract: A method including an executing entity, including fencing dependency circuitry, communicating with physical memory including a work queue (WQ) including a first controlling work request (WR), and a first dependent WR, the first dependent WR including a fencing indication indicating that the first dependent WR should not be executed until the first controlling WR has completed, the fencing dependency circuitry determining that the first dependent WR is ready for execution and checking, based on the fencing indication in the first dependent WR, whether the first controlling WR has completed, and the executing entity executing the first dependent WR only when the first controlling WR has completed. Related apparatus and methods are also provided.

Abstract: An article of apparel includes a padding system that dynamically changes configuration in response to an impending impact. The padding system may change from a state that has a high flexibility and offers low protection from impact to a state that has a low flexibility and offers increase protection from impact. The system may use a filament to constrict a plurality of padding elements together in order to increase the overall stiffness of the pad. The filament may be tightened and loosened by a spool. The spool may receive a signal regarding the impending impact from a sensor that is a part of the article of apparel, or a sensor that is separate from it.

Abstract: Embodiments are disclosed for obtaining a call stack for binaries, where the call stack includes a sequence of frames, and each frame has a “from” address and a “to” address for a call instruction, and for determining basic blocks of instructions for the binaries, where each basic block of instruction has one or more instructions. Further, the embodiments include traversing the call stack to validate from/to address pairs of sequential frames based on control flow routes existing between “from” addresses and “to” addresses of the from/to address pairs, where each from/to address pair has a “from” address of a frame and a “to” address of an immediate previous frame on the call stack.

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Abstract: An information processing system includes multiple processing units the number of which is at least three and multiple communication paths that allow the multiple processing units to mutually communicate information. When at least one of the multiple processing units is brought into a power-off state, multiple processing units that are included in the multiple processing units and that are other than the processing unit brought into the power-off state perform processing for changing one of the communication paths used by the multiple processing units other than the processing unit brought into the power-off state to a different one of the communication paths that has low power consumption.

Abstract: A data compressor a zero-value remover, a zero bit mask generator, a non-zero values packer, and a row-pointer generator. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed from each respective bit stream. The zero bit mask generator receives the 2N bit streams of values and generates a zero bit mask for a predetermined number of values of each bit stream in which each zero bit mask indicates a location of a zero value in the predetermined number of values corresponding to the zero bit mask. The non-zero values packer receives the 2N non-zero-value bit streams and forms a group of packed non-zero values. The row-pointer generator that generates a row-pointer for each group of packed non-zero values.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

Abstract: A processing system includes a processing pipeline which includes fetch circuitry for fetching instructions to be executed from a memory. Buffer control circuitry is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry), to accumulate within one or more buffers fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Abstract: Various embodiments provide access control to unprotected data storage system endpoints. In one embodiment, an authenticated query request is received. The request includes a query associated with an unprotected data storage system endpoint configured to execute queries anonymously. The query is written in a Resource Description Framework (RDF) query language and requests one or more datasets stored in a relational data storage system. A user parameter within the query is identified. The user parameter uniquely identifies a user requesting the query. The query is automatically rewritten to include a set of access control list properties for one or more subject variables in the query. Each of the set of access control list properties configures the query to return data from the one or more datasets for which the user is authorized to access.

Abstract: A computing system includes an issue queue and a microprocessor. The issue queue receives a fused instruction, which includes a first instruction portion fused with a second instruction portion different from the first instruction portion. The microprocessor assigns a first instruction tag (ITAG) to the first instruction portion and a second ITAG to the second instruction portion. The microprocessor determines a first bit that represents the first ITAG, inverts the first bit to determine a second bit that represents the second ITAT, and determines an availability of one or more sources of a second instruction different from the fused instruction based at least in part on the first bit or the second bit.

Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

Abstract: Disclosed is a method for changing operation mode of a weapon that is connected to a maintenance device via an umbilical providing signals and power to the weapon. The method includes transmitting a mode change control signal to electronics in the weapon via a pin on an electrical interface connecting the umbilical to the weapon, and switching the weapon from an operational mode to a non-operational mode and vice versa after receiving the mode change control signal. Also disclosed is a weapon and system including a unit for performing the method.

Abstract: High-speed processing of packets to, and from, a virtualization environment can be provided while utilizing hardware-based segmentation offload and other such functionality. A hardware vendor such as a network interface card (NIC) manufacturer can enable the hardware to support open and proprietary stateless tunneling in conjunction with a protocol such as single root I/O virtualization (SR-IOV) in order to implement a virtualized overlay network. The hardware can utilize various rules, for example, that can be used by the NIC to perform certain actions, such as to encapsulate egress packets and decapsulate packets.

Abstract: In the present invention, a vacant block which is unwritten is identified as a temporary storage block when a writing destination block has already data written. Then, data writing step writing an incoming data to be written into the temporarily storage block, managing step including assigning a pair of the writing destination block and the temporarily storage block an index number which corresponds to the pair, and generating a management table which indicates the index number associating with a physical address indicating a physical position of the temporarily storage block in the nonvolatile memory are performed. In the data writing step, the physical address which corresponds to the index number assigned to the writing destination block is obtained from the management table. The incoming data to be written is written into the temporary storage block indicated by the physical address.

Abstract: Techniques for managing split packages in a module system are disclosed. A code conflict exists between two packages, in different modules, based at least in part on the packages being named identically and including executable code. No code conflict exists between two other identically-named packages, in different modules, based at least in part on the packages not including any executable code. Managing split packages may be based, at least in part, on module membership records associated with the modules.

Abstract: A multiprocessor system includes several processors, a prefetching instruction code interface block, a prefetching data code interface block, a Shared Local Memory (SLMEM), and Clock Gapping Circuits (CGCs). Each processor has the same address map. Each fetches instructions from SLMEM via the instruction interface block. Each accesses data from/to SLMEM via the data interface block. The interface blocks and the SLMEM are clocked at a faster rate than the processors. The interface blocks have wide prefetch lines of the width of the SLMEM. The data interface block supports no-wait single-byte data writes from the processors, and also supports no-wait multi-byte data writes. An address translator prevents one processor from overwriting the stack of another. If a requested instruction or data is not available in the appropriate prefetching circuit, then the clock signal of the requesting processor is gapped until the instruction or data can be returned to the requesting processor.

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM) that stores instructions and data, a system interface block, a posted transaction interface block, and an atomics block. Each processor is coupled to the system interface block via its AHB-S bus. The posted transaction interface block and the atomics block are shared resources that a processor can use via the same system interface block. A processor causes the atomics block to perform an atomic metering operation by doing an AHB-S write to a particular address in shared address space. The system interface block translates information from the AHB-S write into an atomics command, which in turn is converted into pipeline opcodes that cause a pipeline within the atomics block to perform the operation. An atomics response communicates result information which is stored into the system interface block. The processor reads the result information by reading from the same address.

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

Abstract: Methods and systems for cross-language program execution include setting a signature of a second programming language in a first program that is written in a first programming language. A second program that is written in the second programming language is called from the first program, such that the second program omits checks to verify a runtime environment for the second programming language based on the presence of the signature.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.

Abstract: Techniques for automatically persisting variable data are provided. In one embodiment, a computer system can identify, upon compiling or interpreting source code for an application, a variable in the source code that is declared with a predefined keyword. The predefined keyword can indicate that the variable should be persistent. The computer system can then generate, for each instance in the source code where data is assigned to the variable, runtime code for saving the data in a nonvolatile data store.

Abstract: Provided are a module division assistance device, a module division assistance method, and a module division assistance program for automatically extracting a divisible module by utilizing information relating to a function used by a module. A keyword obtaining unit of an information processing device collects data relating to a function used by a module into keyword use data organized by modules, and a data analysis unit uses the data and a calculation method for an indivisibility calculation item specified by a user and stored in an indivisibility calculation item list, thereby calculating an indivisibility, and stores the indivisibility into indivisibility data.

Abstract: A system is described for integrating menu bars of applications executed on a virtual machine in a computing device with menu bars in the host operating system. A hosted hypervisor is executed on the computing device. The hypervisor manages a virtual machine running a guest operating system (OS) on the computing device. An application is executed on the guest OS. A call by the application to the guest OS is detected, the call requesting the guest OS to set a menu bar for the application. The call is intercepted, information regarding the content of the menu bar is retrieved from the intercepted call, and the information is used to set a menu bar for the application in the host OS. Subsequently, when a selection is made from the menu bar in the host OS, the selection is translated to the application running in the virtual machine to effectuate the selection.

Abstract: A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.

Abstract: Placement of structural health monitoring sensors within a coupled bearing assembly. An exemplary structural health monitoring system comprises first and second bearings configured for rotatable positioning along a structure, and a spacer positioned between the first and second bearings. The first and second bearings are placed against opposing sides of the spacer, and have a preload force engaging the respective first and second bearings against the opposing sides of the spacer. A plurality of sensors are coupled to the spacer so as to be positioned between the spacer and at least one of the first and second bearings, the sensors further coupled to at least one of the first and second bearings so as to be configured to monitor a structural health of the at least one of the first and second bearings.

Abstract: A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.

Abstract: A method, computer program product, and system for improving the operation and management of a content management system, by managing data security and incremental refreshes of a compiled access control table. A user may be authorized to access an entity such as a data item by reference to a single table that compiles ACL information from a plurality of tables, without repetitive access to several system tables.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.

Abstract: In one embodiment, a method of informing a mainframe that a filesystem storing a plurality of virtual tapes is filled relative to a particular threshold includes returning, responsive to a write request to a virtual tape in the filesystem, a message indicating that the filesystem is filled relative to the particular threshold. The method can also include monitoring a plurality of filesystems for free space remaining on each of the plurality of filesystems. The method can additionally include indicating, in a data structure stored in a memory, a particular filesystem that is filled above the particular threshold. The data structure can be at least one of a table and a list. The method can further include mounting, responsive to a request to mount a particular virtual tape that is on a filesystem indicated in the data structure as being above the particular threshold, the particular virtual tape as read-only.

Abstract: A method executed by an apparatus includes receiving selection of a function, and determining whether to perform hardware processing or software processing on the function based on a free space in a storage unit configured to store hardware information relating to the hardware processing on the function and function information relating to the function.

Abstract: This document discusses, among other things, systems and methods to access n consecutive entries of a register file in a single operation using a register file entry index consisting of B bits, wherein B is less than the binary logarithm of a depth of the register file, which corresponds to the number of entries in the register file, and to automatically select, for a set of register arguments for the n consecutive entries, between a register port for each argument requiring a register port or one or more shared register ports for the set of register arguments according to description of an instruction set architecture associated with the register file.

Abstract: Extraction of functional semantics and isolated dataflow from imperative object oriented languages, in one aspect, may include identifying one or more methods and/or classes associated with one or more of a plurality of property labels in a computer code written in object oriented language to extract functional and isolation characteristics in the computer code. The plurality of property labels supported by one or more checking rules, are used to verify that the one or more methods and/or classes identified with the plurality of property labels have isolation characteristics. An object oriented language compiler is provided for supplying the plurality of property labels and checking rules. The object oriented language compiler further may include capability to transform methods into compute tasks and connect the compute tasks so as to create a dataflow graph.

Abstract: Extraction of functional semantics and isolated dataflow from imperative object oriented languages, in one aspect, may include identifying one or more methods and/or classes associated with one or more of a plurality of property labels in a computer code written in object oriented language to extract functional and isolation characteristics in the computer code. The plurality of property labels supported by one or more checking rules, are used to verify that the one or more methods and/or classes identified with the plurality of property labels have isolation characteristics. An object oriented language compiler is provided for supplying the plurality of property labels and checking rules. The object oriented language compiler further may include capability to transform methods into compute tasks and connect the compute tasks so as to create a dataflow graph.

Abstract: A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.

Abstract: Based on an input index sequence (702) composed of four indices (each having a bit width of 8 bits), a shift-copier generates an index sequence (902) by shifting each index leftward by 1 bit and making two copies of each index, and outputs the generated index sequence (902). An adder generates a shuffle pattern (703) by adding 1, 0, 1, 0, 1, 0, 1 and 0 to the indices in the index sequence (902) from left to right, and outputs the generated shuffle pattern (703).

Abstract: A method in a system for handling compiled code is provided. The system comprises a Just-In-Time, JIT, compiler for compiling code, and at least one array processor unit comprising a plurality of processors for executing program code. The method comprises compiling input program code, whereby compiled program code is generated for the input program code. While compiling at least two parts of the compiled program code to be executed in parallel are identified. The identified at least two parts of compiled code are executed in parallel speculatively on at least two respective of the plurality of processors. Control if the at least two parts of in parallel executed code are in conflict with each other is performed, and if the parts are in conflict, the parts are executed again.

Abstract: A system and method is disclosed for sharing type information between object maps. When an object data structure is modified in a dynamic programming environment to change an initial number of object properties a child object map for the modified object data structure is generated based on a parent object map for the unmodified object data structure, and a descriptor array associated with the base object map is shared with the child object map. The descriptor array is dynamically altered according to the modified object data structure, and access to the descriptor array is limited from the parent object map in accordance with the initial number of object properties of the unmodified object data structure.

Abstract: For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.

Abstract: Various embodiments of a virtualization system and method are provided herein, wherein computer resources are emulated and simulated by a hypervisor system. In order to provide improved signalization within a virtual computer system, various embodiments may use a virtual CPU for signalizing an external event, wherein the virtual CPU is used temporarily by a signalization routine for processing the signalization of the event.

Abstract: A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

Abstract: A technique for resolving deadlocks between an RCU subsystem and an operating system scheduler. An RCU reader manipulates a counter when entering and exiting an RCU read-side critical section. At the entry, the counter is incremented. At the exit, the counter is manipulated differently depending on the counter value. A first counter manipulation path is taken when the counter indicates a task-context RCU reader is exiting an outermost RCU read-side critical section. This path includes condition-based processing that may result in invocation of the operating system scheduler. The first path further includes a deadlock protection operation that manipulates the counter to prevent an intervening RCU reader from taking the same path. The second manipulation path is taken when the counter value indicates a task-context RCU reader is exiting a non-outermost RCU read-side critical section, or an RCU reader is nested within the first path. This path bypasses the condition-based processing.

Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for to a corresponding load, by determining if said store has an actual age but said corresponding load does not have an actual age, then said store is earlier than said corresponding load; if said corresponding load has an actual age but said store does not have an actual age, then said corresponding load is earlier than said store; if neither said corresponding load or said store have an actual age, then a virtual identifier table is used to determine which is earlier; and if both said corresponding load and said store have actual ages, then the actual ages are used to determine which is earlier.

Abstract: A technique for resolving deadlocks between an RCU subsystem and an operating system scheduler. An RCU reader manipulates a counter when entering and exiting an RCU read-side critical section. At the entry, the counter is incremented. At the exit, the counter is manipulated differently depending on the counter value. A first counter manipulation path is taken when the counter indicates a task-context RCU reader is exiting an outermost RCU read-side critical section. This path includes condition-based processing that may result in invocation of the operating system scheduler. The first path further includes a deadlock protection operation that manipulates the counter to prevent an intervening RCU reader from taking the same path. The second manipulation path is taken when the counter value indicates a task-context RCU reader is exiting a non-outermost RCU read-side critical section, or an RCU reader is nested within the first path. This path bypasses the condition-based processing.