Abstract: A method for execution by a computing device includes, for each update operation of a plurality of update operations, creating a new batch update containing the update operation. The update operation is evaluated in an empty transaction context to generate cached values. When it is determined that the new batch overlaps with an existing waiting batch, the new batch is merged with the existing waiting batch, and intermediate are generated based on serially composing the update operations of the merged batches. When it is determined that the new batch overlaps with a running batch, the new batch is added to the existing waiting batches. Otherwise, immediate running of the new batch is authorized. The new batch is run by creating a CASN transaction from its evaluated transaction context that includes the cached values.

Abstract: This disclosure describes systems and methods for using a primary device, communicatively coupled to a remote system, to configure or re-configure a secondary device in the same environment as the primary device. In some instances, the primary device may communicatively couple to the secondary device via a short-range wireless connection and to the remote system via a wireless area network (WAN), a wired connection, or the like. Thus, the primary device may act as an intermediary between the secondary device and the remote system for configuring the secondary device.

Abstract: Certain aspects of the present disclosure provide methods and apparatuses for wireless communications between devices. An example method generally includes obtaining, via a non-audible signal, identification information, and using the identification to establish a connection, via a radio access technology (RAT), with a second device for transferring data between the first device and the second device via the RAT.

Abstract: A middleware machine environment can provide message queues for multinode applications. The transactional middleware machine environment includes a message control data structure on a message receiver and a heap data structure in a shared memory that is associated with the message receiver. The message sender operates to write a message directly into the heap data structure, and to maintain metadata associated with the message in the message control data structure. Furthermore, the message control data structure can be a ring structure with a head pointer and a tail pointer. Additionally, the message receiver resides on a server that is connected with a plurality of clients, with each of said clients keeping a private copy of the message control data structure. Also, the message receiver can support concurrent access to the message control data structure associated with the message receiver.

Abstract: A system and method are provided of a node for use in a network having a plurality of nodes. The node is configured to identify neighboring node(s) within a predetermined closeness of said node, measured by any of physical, logical, network hops, network link, or vertices analysis closeness. The node determines a level of nervousness of itself and sends and/or receives communication as to the level of nervousness to the neighboring node(s).

Abstract: An audio processing system (100) for spatial synthesis comprises an upmix stage (110) receiving a decoded m-channel downmix signal (X) and outputting, based thereon, an n-channel upmix signal (Y), wherein 2?m<n. The upmix stage comprises a downmix modifying processor (120), which receives the m-channel downmix signal and outputting a modified downmix signal (d1, d2) obtained by cross mixing and non-linear processing of the downmix signal, and further comprises a first mixing matrix (130) receiving the downmix signal and the modified downmix signal, forming an n-channel linear combination of the downmix signal channels and modified downmix signal channels only and outputting this as the n-channel upmix signal. In an embodiment, the first mixing matrix accepts one or more mixing parameters (g, ?1, . . . ) controlling at least one gain in the linear combination performed by the first mixing matrix. The gains are polynomials of degree ?2.

Abstract: Disclosed are methods and apparatus for measuring performance of a multi-thread processor. The method and apparatus determine loading of a multi-thread processor through execution of an idle task in individual threads of the multi-thread processor during predetermined time periods. The idle task is configured to loop and run when no other task is running on the threads. Loop executions of the idle task on each thread are counted over each of the predetermined time periods. From these counts, loading of each of the threads of the multi-thread processor may then be determined. The loading may be used to develop a processor profile that may then be displayed in real-time.

Abstract: Systems and methods for rendering an image using a render setup graph are provided. The render setup graph may be used to configure and manage lighting configuration data as well as external processes used to render the computer-generated image. The render setup graph may include a dependency graph having nodes interconnected by edges along which objects and object configuration data may be passed between nodes. The nodes may be used to provide a source of objects and object configuration data, configure visual effects of an object, partition a set of objects, call external processes, perform data routing functions within the graph, and the like. In this way, the render setup graph may advantageously be used to organize configuration data and execution of processes for rendering an image.

Abstract: A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be translated from one format to another format. If so determined, a convert machine instruction is executed that obtains a single precision datum in a first representation in a first format from a first register; converts the single precision datum of the first representation in the first format to a converted single precision datum of a second representation in a second format; and places the converted single precision datum in a second register.

Abstract: Method for processing data, in which a Petri net is encoded, written into a memory and read and executed by at least one instance, wherein transitions of the Petri net read from at least one tape and/or write on at least one tape symbols or symbol strings, with the aid of at least one head. In an alternative, data-processing, co-operating nets are composed, the composition result is encoded, written into a memory and read and executed from the memory by at least one instance. In doing this, components can have cryptological functions. The data-processing nets can receive and process second data from a cryptological function which is executed in a protected manner. The invention enables processing of data which prevents semantic analysis of laid-open, possibly few processing steps and which can produce a linkage of the processing steps with a hardware which is difficult to isolate.

Abstract: Disclosed is an apparatus, system, and method to unlock a body area network (BAN) of a patient and to transmit medical data about the patient. The BAN, under the control of a body area controller (BAC), may be unlocked based upon a pre-defined patient action performed by the patient and the BAN may then be connected to a wireless device. The BAN medical data of the patient may then be transmitted by the wireless device.

Abstract: A method for rapid peer-to-peer link establishment among a set of mobile devices includes operating a first second device, advertising system attributes in a wireless beacon by the second device, receiving the system attributes from the wireless beacon at the first device, comparing the system attributes to a service needed by the first device, and, if the second device is compatible based on the comparing, establishing a wireless link by the first device to the second device. A system and wireless device for rapid peer-to-peer link establishment among a set of mobile devices are also described.

Abstract: A multi-frame data processing apparatus and method using frame disassembly is provided. The multi-frame data apparatus includes a data communication unit, a frame processing unit, and a data processing unit The data communication unit receives a transmission signal from a Line Adaptation Unit (LAU). The frame processing unit disassembles each frame of the transmission signal and acquires information data that is included in the transmission signal. The data processing unit transfers the information data to an Algorithm Processing Unit (APU), and acquires processed information data that is obtained by processing the information data via the APU based on a corresponding algorithm.

Abstract: A cooperative data stream processing system utilizing a plurality of independent, autonomous and heterogeneous sites in a cooperative arrangement process user-defined job requests over dynamic, continuous streams of data. A distributed plan is created that identifies the processing elements that constitute a job that is derived from user-defined inquiries. These processing elements are arranged into subjobs that are mapped to various sites within the system for execution. The jobs are executed across the plurality of distributed sites in accordance with the distributed plan. The distributed plan also includes requirements for monitoring and back-up of the execution sites in the event of a failure on one of those sites. Execution of the jobs in accordance with the distributed plan is facilitated by the identification of an owner site to which the distributed plan is communicated and which is responsible for driving the execution of the distributed plan.

Abstract: An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information handling system. The processor includes a resource allocation identifier (RAID) that links the processor hardware unit initiating a system bus request with a specific resource allocation group. The resource allocation group assigns a specific bandwidth allocation rate to the initiating processor. When a load, store, or I/O interface bus request reaches the I/O bus for execution, the resource allocation manager restricts the amount of bandwidth associated with each I/O request by assigning discrete amounts of bandwidth to each successive I/O requester. Successive stages of the instruction pipeline in the hardware unit contain the resource allocation identifiers (RAID) linked to the specific load, store, or I/O instruction.

Abstract: A facsimile transferring system is supplied capable of preventing a paper on which facsimile data transferred from his/her work place is printed from leaving as it is at a place where the destination person does not exist.

Abstract: An off-load for processing a data frame containing information has a memory for storing information on a plurality of processing paths. A processor in the off-load engine determines which processing path the data frame is to be processed. Each one of a plurality of processing engines processes the data frame depending on whether the processing engine is within the determined processing path. Some of the processing engines are implemented in hardware and/or data frame type specific software and others makes use of generic software. In some embodiments, the data frame is also parsed for further processing by the processing engines. In some embodiments, a static header is also pre-pended to the data frame to allow easy access to information associated with the data frame by the processing engines.

Abstract: A method, apparatus and system for adaptably distributing video server processes among processing elements within a video server such that video server operation may be adapted in a manner facilitating rigorous timing constraints.

Abstract: Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).

Abstract: Early issue of transaction ID is disclosed. An apparatus comprising decoder to generate a first node ID indicative of the destination of a cache transaction from a caching agent, a transaction ID allocation logic coupled to and operating in parallel to the decoder to select a transaction ID (TID) for the transaction based on the first node ID, a packet creation unit to create a packet that includes the transaction, the first node ID, the TID and a second node ID corresponding to the requestor.

Abstract: A processor including an architecture for limiting store operations includes: a data input and a cache input as inputs to data merge logic; a merge buffer for providing an output to an old data buffer, holding a copy of a memory location and two way communication with a new data buffer; compare logic for receiving old data from the old data buffer and new data from the new data buffer and comparing if the old data matches the new data, and if there is a match determining an existence of a silent store; and store data control logic for limiting store operations while the silent store exists. A method and a computer program product are provided.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: The Distributed Virtual I/O Tool replaces dedicated VIO server LPARs by distributing the virtual I/O functions across several application LPARs connected by a high-speed communication channel. The physical I/O devices are distributed across available LPARs. The Distributed Virtual I/O Tool assigns each I/O request to an appropriate I/O device. The Distributed Virtual I/O Tool monitors each I/O request and reassigns I/O devices when performance drops on a specific device or when a device is no longer available.

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Abstract: From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.

Abstract: A system for computer hardware serial number management includes a computer system chassis comprising a chassis serial number. The chassis serial number is embodied on the computer system chassis as a physical serial number. A first RFID tag is attached to the computer system chassis at a first location. The first RFID tag stores indicia of the physical serial number. A first electronic device couples to the computer system chassis, and comprises a first RFID reader configured to retrieve the stored indicia of the physical serial number from the first RFID tag and to determine the chassis serial number based on the retrieved indicia of the physical serial number.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.

Abstract: One embodiment of the present invention provides a system that facilitates receiving content at a client from one or more servers that can potentially provide the content. The client starts by sending a request for the content to a directory server. In response to the request, the client receives a list of candidate servers that can potentially provide the content from the directory server. Once the client has received the list of candidate servers, the client sends a request to one or more of the candidate servers for the content, and subsequently receives the content from one or more of the candidate servers.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing units. The processor core is clocked by a clock signal. A branching instruction received by the central unit, in the course of a current cycle, is processed in the course of the current cycle.

Abstract: A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is annotated with the results of the benchmarking of the program image. Basic blocks of the program are then grouped into bins. When the program image is executed, a drafting scheduler stops threads before they leave a bin and schedules any threads queued for the same bin.

Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The first communication port is used in support of the aforementioned link to the computer. A second slave processor, also having first and second serial ports, is linked by its first communication port to the second communication port of the first slave processor. The slave processors are programmed to read designated pins on their first communication ports. The read values determine the identification code of each processor. Thereafter, each slave processor outputs to its second port a value one greater than the value read from its first port. Therefore, each slave processor assigns itself a particular identification code and directs the next slave processor to assign itself an identification code one greater.

Abstract: A system and methods for implementing histogram computation, for example, into the rasterization pipeline of a 3-D graphics system, are provided. With the histogram computation mechanism, statistical histogram data may be generated for input data of any kind or retrieved from any source that may be specified in a 2-D array or specified in an immediate fashion to specialized data processing hardware. Depending on the nature of the input data, the data may be filtered before passing the data to data processing hardware for further processing. The data processing hardware may then apply an additional function to the input data set before calculation of the histogram data. Then, at some point, the data processing hardware may apply a function to the data to map the derived data to a real-valued function that can then be quantized to a histogram element in the range specified from zero to the number of histogram elements minus one.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: According to some embodiments, it is determined if a register is ready to exchange data with a processing element.

Abstract: An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N?2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of an input packet as the address; a unit that calculates a hash address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instuction inputs; and a unit that performs a waiting process in response to a select signal.

Abstract: An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stores the first half of the data result. A miscellaneous-logic unit determines when to release the first half of the data result from the register to synchronize the first half and the second half of the data result.

Abstract: A computer system includes a scoreboard mechanism that provides a locking scheme to preserve data dependencies. An index is used to unlock (i.e., invalidate) scoreboard entries when a terminating event associated with that entry's instruction has occurred. For a load instruction, the terminating event that triggers invalidation for a particular scoreboard entry is the return of the load data. An index is used to identify the scoreboard entry associated with the returning load instruction, since load instructions may return load data out of order.

Abstract: A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.

Abstract: A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.

Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to recieve executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Abstract: A packet generation unit divides a plurality of generated clocks to generate clocks with different frequencies, selects any of the frequencies, sets destination information and data depending on a selected clock rate and generates a data packet that stores the setting result. An input/output control unit taken the data packet generated by the packet generation unit and sends it to a program storage unit or a data memory interface unit according to the destination information. As a result, information can be internally processed in a predetermined frequency without depending on an outside clock. When the outside clock is slow, information can be internally processed in a higher-rate frequency. On the contrary, when the outside clock is too fast to internally process information, information can be internally processed in a lower-rate frequency to secure a processing time.

Abstract: Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

Abstract: In a data driven information processor, an operation apparatus includes a data select unit and a flag select unit selecting information according to the value of flag data in an input data packet. The data select unit selects the processed result for each data in the input data packet or the data itself. The flag select unit selects the flag data set with a value according to the processed result or the flag data of the input data packet. The selected information is stored in the input data packet, which is output to a program storage unit. Accordingly, the processed result can be obtained for certain data selected out of a plurality of data in the data packet to be reflected in the subsequent operation process without dividing the data packets.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.