Abstract: Disclosed are techniques for implementing an intelligent system with dynamic configurability. These techniques identifying a plurality of flow nodes for a software application and determine a dynamic flow for executions of the intelligent system with the plurality of flow nodes, one or more dynamic conditions, and one or more dynamic actions, without hard coded inter-dependency between two or more flow nodes of the plurality of flow nodes. The intelligent system is transformed into a dynamically configured intelligent system at least by performing a modification pertaining to one or more flow nodes in the dynamic flow, without affecting remaining flow nodes in the dynamic flow.

Abstract: Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

Abstract: Described herein is a merged data path unit that has elements that are configurable to switch between different instruction types. The merged data path unit is a pipelined unit that has multiple stages. Between different stages lie multiplexor layers that are configurable to route data from functional blocks of a prior stage to a subsequent stage. The manner in which the multiplexor layers are configured for a particular stage is based on the instruction type executed at that stage. In some implementations, the functional blocks in different stages are also configurable by the control unit to change the operations performed. Further, in some implementations, the control unit has sideband storage that stores data that “skips stages.” An example of a merged data path used for performing a ray-triangle intersection test and a ray-box intersection test is also described herein.

Abstract: Techniques are described for increasing the functionality of a data processing system via a computer-executed tool that converts programs, written in a procedural language, into components that may be executed as a dataflow graph. The dataflow graph generated from a program written in a procedural programming language may support various forms of parallelism, such as pipeline parallelism and/or component parallelism. In some embodiments, parallelism may be achieved by parsing the program based on a grammar and identifying control flow relationships between data operations performed by the program. In particular, types of dataflow graph components may be identified, according to the grammar, as corresponding to particular data operations (or groups of data operations) of the program. A dataflow graph may be generated to comprise the identified components, which may be connected together with flows in an order according to the identified control flow relationships between data operations.

Abstract: A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.

Abstract: A compiler system, method and computer program product for optimizing a program is disclosed. The compiler includes an extractor module configured to extract, from an initial program code, a hierarchical task representation wherein each node of the hierarchical task representation corresponds to a potential unit of execution. The root node of the hierarchical task representation represents the entire initial program code and each child node represents a sub-set of units of execution of its respective parent node. It further has a parallelizer module configured to apply to the hierarchical task representation pre-defined parallelization rules associated with the processing device to automatically adjust the hierarchical task representation by assigning particular units of execution to particular processing units of the processing device and by inserting communication and/or synchronization in that the adjusted hierarchical task representation reflects parallel program code for the processing device.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: A system for executing a data flow graph comprises: at least two first actors each comprising means for independently executing a computation of a same data set comprising at least one datum, and producing a quality descriptor of the data set, the execution of the computation by each of at least two first actors being triggered by a synchronization system; a third actor, comprising means for triggering the execution of the computation by each of at least two first actors, and initializing a clock configured to emit an interrupt signal when a duration has elapsed; a fourth actor, comprising means for executing, at the latest at the interrupt signal from the clock: the selection, from the set of at least two first actors having produced a quality descriptor, of the one whose descriptor exhibits the most favorable value; the transfer of the data set computed by the selected actor.

Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

Abstract: An intelligent function unit includes an input selector selecting, as an input signal, an actual input signal or a simulated input signal generated in advance; an output selector selecting whether to output an output signal to the second controlled device; and a calculator causing an input/output controller in which combination and order of use of general circuit blocks are set to process the input signal one step at a time and transmit the output signal to an engineering tool or causing the input/output controller in which combination and order of use of the general circuit blocks are set to process the input signal consecutively for a set period of two or more steps, store the output signal for each step in a logger, and transmit an output signal corresponding to the set period and stored in the logger to the engineering tool.

Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

Abstract: A computing system includes: a control circuit configured to: access a subject interaction representing communication between a customer and a service provider; identify a communication segment and a sourcing party associated with the communication segment from the subject interaction; generate a message label for the communication segment based on the sourcing party; generate a dialog-flow framework based on the message label for representing the subject interaction; and a storage circuit, coupled to the control circuit, configured to store the dialog-flow framework.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, the instruction includes at least an opcode, a field for a packed data source operand, and a field for a packed data destination operand. When executed, the instruction causes for each data element position of the source operand, multiply to a value stored in that data element position all values stored in preceding data element positions of the packed data source operand and store a result of the multiplication into a corresponding data element position of the packed data destination operand.

Abstract: Parallelism of processing can be improved while existing software resources are utilized substantially as they are. A data processing apparatus includes a plurality of processing units configured to process packets each including data and extended identification information added to the data, the extended identification information including identification information for identifying the data and instruction information indicating one or more processing instructions to the data, each processing unit in the plurality of processing units including: an input/output unit configured to obtain, in the packets, only a packet whose address information indicates said each processing unit in the plurality of processing units, the address information determined in accordance with the extended identification information; and an operation unit configured to execute the processing instruction in the packet obtained by the input/output unit.

Abstract: A pipelined run-to-completion processor has a special tripwire bus port and executes a novel tripwire instruction. Execution of the tripwire instruction causes the processor to output a tripwire value onto the port during a clock cycle when the tripwire instruction is being executed. A first multi-bit value of the tripwire value is data that is output from registers, and/or flags, and/or pointers, and/or data values stored in the pipeline. A field of the tripwire instruction specifies what particular stored values will be output as the first multi-bit value. A second multi-bit value of the tripwire value is a number that identifies the particular processor that output the tripwire value. The processor has a TE enable/disable control bit. This bit is programmable by a special instruction to disable all tripwire instructions. If disabled, a tripwire instruction is fetched and decoded but does not cause the output of a tripwire value.

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Abstract: A method is provided for interfacing a plurality of processing components with a shared resource. A token signal path is provided to allow propagation of a token through the processing components, wherein possession of the token enables a processing component to conduct a transaction with the shared resource. Token processing logic is provided for propagating the token from one processing component to another along the token signal path, the propagating being done at a propagation rate related to a transaction rate of the shared resource. The token processing logic also generates a trigger signal at least in part based on the token and propagates to trigger signal to the shared resource to convey initiation of a transaction with the shared resource. A circuit comprising a plurality of processing components and a shared resource is provided wherein the processing components and the shared resource interface with one another using the method proposed.

Abstract: A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

Abstract: A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.

Abstract: An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in the normal operation mode, and a second processor for processing an internal operation of the electric device in the normal operation mode. The second processor consumes power smaller than that of the first processor. In the electric device, power of the first processor is restricted through a restriction process in the power save operation mode. Further, in the power save operation mode, the second processor restricts the internal operation and processes the information input externally. When the second processor detects the information input externally, power of the first processor is released through a restriction releasing process.

Abstract: Techniques are described for abating the negative effects of wait conditions in a distributed system by temporarily decreasing the execution time of processing elements. Embodiments of the invention may generally identify wait conditions from an operator graph and detect the slowest processing element preceding the wait condition based on either historical information or real-time data. Once identified, the slowest processing element may be sped up to lessen the negative consequences of the wait condition. Alternatively, if the slowest processing element shares the same compute node with another processing element in the distributed system, one of the processing elements may be transferred to a different compute node to free additional computing resources on the compute node.

Abstract: The execution engine is a new organization for a digital data processing apparatus for highly parallel execution of structured fine-grain parallel computations. The execution engine includes a memory for storing data and a domain flow program, a controller for requesting the domain flow program from the memory, and further for translating the program into programming information, a processor fabric for processing the domain flow programming information and a crossbar for sending tokens and the programming information to the processor fabric.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: Various arrangements for processing data sets using multiple processors are presented. A plurality of constraints may be received by a computer system. Each constraint may identify a data relationship that requires a subset of records of one or more data sets to be processed by a same processing device. A plurality of final constraints may be calculated. Each final constraint of the plurality of final constraints may be linked with a record. Each final constraint of the plurality of final constraints may be at least partially based on the plurality of constraints. Final constraints of the plurality of final constraints having a same value may be linked with records that are to be processed by the same processing device. At least partially based on the final constraint, the set of records may be distributed to a plurality of processing devices for processing.

Abstract: An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in the normal operation mode, and a second processor for processing an internal operation of the electric device in the normal operation mode. The second processor consumes power smaller than that of the first processor. In the electric device, power of the first processor is restricted through a restriction process in the power save operation mode. Further, in the power save operation mode, the second processor restricts the internal operation and processes the information input externally. When the second processor detects the information input externally, power of the first processor is released through a restriction releasing process.

Abstract: Various arrangements for processing data sets using multiple processors are presented. A plurality of constraints may be received by a computer system. Each constraint may identify a data relationship that requires a subset of records of one or more data sets to be processed by a same processing device. A plurality of final constraints may be calculated. Each final constraint of the plurality of final constraints may be linked with a record. Each final constraint of the plurality of final constraints may be at least partially based on the plurality of constraints. Final constraints of the plurality of final constraints having a same value may be linked with records that are to be processed by the same processing device. At least partially based on the final constraint, the set of records may be distributed to a plurality of processing devices for processing.

Abstract: Techniques are described for abating the negative effects of wait conditions in a distributed system by temporarily decreasing the execution time of processing elements. Embodiments of the invention may generally identify wait conditions from an operator graph and detect the slowest processing element preceding the wait condition based on either historical information or real-time data. Once identified, the slowest processing element may be sped up to lessen the negative consequences of the wait condition. Alternatively, if the slowest processing element shares the same compute node with another processing element in the distributed system, one of the processing elements may be transferred to a different compute node to free additional computing resources on the compute node.

Abstract: The invention relates to a control device for lubrication systems, having a control processor which is arranged in a housing, having connections, which are formed on the housing, for sensor inputs and control outputs, which are connected to the control processor, and having an operator interface which is secured to the outside of the housing and is intended to input control parameters. Provision is made for the control processor to be set up with different control programs for different lubrication systems and for program switches for selecting the different control programs to be arranged inside the housing.

Abstract: Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

Abstract: A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute engine. The data flow path includes a recirculation path connecting the final compute engine to the initial compute engine with no compute engine therebetween.

Abstract: A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. The update engine supports dynamic updating without requiring processor shutdown, thereby allowing the processor to seamlessly continue operation during a live performance.

Abstract: A design verification system that verifies the operation of multi-processor architecture by generating test programs in which the behavior of the processor, when executing the test program, is evaluated against the behavior required by the design specification. The test program generator produces scenarios for a multi-processor design in which non-unique results may occur. The system is provided with facilities to report expected outcomes, and to evaluate the validity of non-unique results in multiple resources under conditions of non-unique result propagation and dependencies among adjacent and non-adjacent resources.

Abstract: A motherboard device includes a first connecting interface coupled to a first graphics card, a second connecting interface coupled to a second graphics card, a power source connected electrically to the first connecting interface for supplying electric power to the first graphics card via the first connecting interface, and a switch unit interconnecting electrically the power source and the second connecting interface, and operable so as to switch between an ON-state, where the power source supplies electric power to the second graphics card via the second connecting interface, and an OFF-state, where the electric power from the power source is not supplied to the second graphics card.

Abstract: Methods, systems, and machine-readable media are disclosed for passing executable instructions via synchronized data objects. According to one embodiment, passing executable instructions from a first device to a second device during a synchronization operation between the first device and the second device can comprise synchronizing one or more data objects between the first device and the second device. At least one of the one or more data objects can include one or more executable instructions from the first device. The one or more executable instructions can be read from the data objects on the second device. Each of the one or more executable instructions may then be executed on the second device.

Abstract: A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.

Abstract: In one embodiment, a process may be performed in parallel on a parallel server by defining a data type that may be used to reference data stored on the parallel server and overloading a previously-defined operation, such that when the overloaded operation is called, a command is sent to the parallel server to manipulate the data stored on the parallel server. In some embodiments, the previously-defined operation that is overloaded may be an operation of an operating system. Further, in some embodiments, when the data stored on the parallel server is no longer needed, a command may be sent to the parallel server to reallocate the memory used to store the data.

Abstract: A method and apparatus for selective control of display data sequencing in a mobile computing device is disclosed. The method may include storing a plurality of display data sequencing instruction sets in a memory of the mobile computing device, each of the display data sequencing instruction sets being usable for transferring data in accordance with a different sequencing of display data than other ones of the display data sequencing instruction sets, receiving an indication of a particular type of display data sequencing to be used, selecting one of the display data sequencing instruction sets based on the received indication of the particular type of display data sequencing to be used, transferring data for display based on the selected one of the display data sequencing instruction sets, and controlling the transfer of data to the display device in order to synchronize the data transfer with the data and timing requirements of the display device.

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: A system, apparatus and method of enhancing priority boosting of scheduled threads are provided. If, while being executed by a second CPU, a second thread determines that it has to wait for a lock on a shared resource held by a first thread that is scheduled to be executed by a first CPU, the second thread may boost the priority of the first thread by passing its priority to the first thread if its priority is higher than the first thread's priority. Further, to enhance the priority boost of the first thread, the second thread may reschedule the first thread to be processed by the second CPU. By having been rescheduled on the second CPU, the second thread may be dispatched for execution right thereafter.

Abstract: A virtual applications architecture is provided according to the present invention. The architecture includes a topology manager for managing applications across a plurality of members, and a virtual applications manager for defining a plurality of resources comprising the applications. The topology manager communicates with the plurality of members to initiate scaling of the applications associated with the virtual applications manager to the members. The architecture may also include a replication system for deploying the applications to the members.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation unit is configured to provide a lock signal and sequence information to the section controllers in each of the pipeline blocks. The section controllers are configured to maintain in order inter-pipeline execution of the sequence responsive to the sequence information and the lock signal.

Abstract: The flexible through-connection process, operational in a Mobile Switch Center, that provides support for allowing the call routing processor of the Mobile Switch Center to independently perform a through-connection/switch-connection based on different types of calls so that the Mobile Switch Center can make a through-connection at different stages of the outgoing call leg. In operation, the present flexible through-connection process includes in the call control processor of the switching system a new parameter in the existing inter-process message which is sent to the call routing processor at call setup time. The values supported for this new parameter will be pre-defined in the Mobile Switch Center and used by the call routing processor to determine when to perform through-connection/switch-connection for an outgoing call leg.

Abstract: Methods and apparatus provide for disabling at least some data path processing circuits of a SIMD processing pipeline, in which the processing circuits are organized into a matrix of slices and stages, in response to one or more enable flags during a given cycle.

Abstract: A technique is provided for use in a handheld multimedia device that uses the historical load profile statistics of a particular multimedia stream to dynamically scale the computational power of a computing engine, depending upon the complexity of the multimedia content and thereby reduce the power consumption for computationally less intensive content and consequently reduce the power consumption by a significant amount over a duration of time.

Abstract: From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.

Abstract: A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.

Abstract: A micro controller includes a first storing circuit configured to store program data for performing a power on operation of a system, and a second storing circuit configured to temporarily store algorithm program data for operation of the system loaded from an external storing means while the system operates in response to control of the first storing circuit.

Abstract: Defect detection in a software system made of multiple computer program programs is facilitated by using information about cross-program interactions and dependency relationships between programs to analyze the individual programs in such a way that the behavior of the system as a whole is accurately represented. A list of dependency relationships is read in; these dependency relationships are used to determine an order in which the programs should be analyzed. The programs are then analyzed in that order. Information from the analysis of the programs is used to inform the analysis of subsequently-analyzed programs.