Abstract: A computer comprising a plurality of interconnected processing nodes arranged in a configuration in which multiple layers of interconnected nodes are arranged along an axis, each layer comprising at least four processing nodes connected in a non-axial ring by at least respective intralayer link between each pair of neighbouring processing nodes, wherein each of the at least four processing nodes in each layer is connected to a respective corresponding node in one or more adjacent layer by a respective interlayer link, the computer being programmed to provide in the configuration two embedded one dimensional paths and to transmit data around each of the two embedded one dimensional paths, each embedded one dimensional path using all processing nodes of the computer in such a manner that the two embedded one dimensional paths operate simultaneously without sharing links.

Abstract: A command processor determines whether a command descriptor describing a current command is in a first format or in a second format, wherein the first format includes a source memory address pointing to a memory area in a shared memory having a binary code to be accessed according to direct memory access (DMA) scheme, and the second format includes one or more object indices, a respective one of the one or more object indices indicating an object in an object database. If the command descriptor describing the current command is in the second format, the command processor converts a format of the command descriptor to the first format, generates one or more task descriptors describing neural network model tasks based on the command descriptor in the first format, and distributes the one or more task descriptors to the one or more neural processors.

Abstract: An elastic request handling technique limits a number of threads used to service input/output (I/O) requests of a low-latency I/O workload received by a file system server executing on a cluster having a plurality of nodes deployed in a virtualization environment. The limited number of threads (server threads) is constantly maintained as “active” and running on virtual central processing units (vCPUs) of a node. The file system server spawns and organizes the active server threads as one or more pools of threads. The server prioritizes the low-latency I/O requests by loading them onto the active threads and allowing the requests to run on those active threads to completion, thereby obviating overhead associated with lock contention and vCPU migration after a context switch (i.e., to avoid rescheduling a thread on a different vCPU after execution of the thread was suspended).

Abstract: Techniques for distributing data associated with the weight values of a neural network model are described. The techniques can include performing computations associated with the neural network model in a neural network accelerator to generate data associated with weights of the neural network model. A multicast request packet is then generated to distribute the data. The multicast request packet may contain the data associated with the weights, and an address in a multicast address range of a peripheral bus multicast switch. The multicast request packet is sent to a port of the peripheral bus multicast switch, and in response, the peripheral bus multicast switch generates multiple packets containing the data from the multicast request packet and forwards them to multiple peripheral bus ports corresponding to other processing nodes of the system.

Abstract: Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes determining resource allocations for handling execution jobs directed to a computing cluster and forming compute units to handle the execution jobs based on the resource scheduling, the compute units comprising sets of computing components selected from among a pool of computing components coupled to at least a communication fabric. The method also includes initiating the execution jobs on the compute units, and responsive to completions of the execution jobs, decomposing the computing components of the compute units back into the pool of computing components.

Abstract: A heterogeneous processing system and method including a host processor, a first processor coupled to a first memory, a second processor coupled to a second memory, and switch and bus circuitry that communicatively couples the host processor, the first processor, and the second processor. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to directly access the second memory using the mapped physical addresses according to memory extension operation. The first processor may be a reconfigurable processor, a reconfigurable dataflow unit, or a compute engine. The first processor may directly read data from or directly write data to the second memory while executing an application. The method may include configuring the first processor to directly access the second memory while executing an application for reading or writing data.

Abstract: An information handling system may include a processor and a management controller electrically coupled to the processor and configured to provide out-of-band management facilities for management of the information handling system, the management controller further configured to in response to one or more heartbeat synchronization signals received from a software service of the information handling system, wherein each of the one or more heartbeat synchronization signals is associated with an item of software stored on the information handling system, determine if any critical software is missing from the information handling system, and for each item of missing critical software, cause a service operating system of the information handling system to stage installation of a restore image of such item.

Abstract: A method, system and apparatus for provisioning a computation into a trusted execution environment, including verifying the trusted execution environment, generating integrity information of the computation, generating sealed data, sending information of the computation, the sealed data, and integrity information to the trusted execution environment, confirming the sealed data, and verifying integrity of the computation information from the integrity information and the computation information.

Abstract: Dynamic thread count optimizations include determining: (i) a detected quantity of unassigned IO requests; (ii) a quantity of IO requests currently in process; (iii) a thread pipeline value required to fill a thread's pipeline capacity and based on ratio of (a) an IO duration time from when an IO request is issued until a corresponding IO completion is received and (b) an IO processing time from when an IO request is assigned to a thread until it is issued; and (v) an ideal thread quantity based on a ratio of (a) the quantity of IO requests to be processed and (b) the thread pipeline value. Said optimizations also include dynamically activating new threads whenever a quantity of active threads is determined to be less than the ideal thread quantity.

Abstract: Systems and methods for managing settings based upon Information Handling System (IHS) motion using heterogeneous computing platforms are described. In an illustrative, non-limiting embodiment, an IHS may include a heterogeneous computing platform and a memory coupled to the heterogeneous computing platform, where the memory comprises a plurality of sets of firmware instructions, where each of the sets of firmware instructions, upon execution by a respective device among a plurality of devices of the heterogeneous computing platform, enables the respective device to provide a corresponding firmware service, and where at least one of the plurality of devices operates as an orchestrator configured to: identify an IHS motion, at least in part, upon context or telemetry data received from at least a subset of the plurality of devices; and trigger a modification of an IHS setting based, at least in part, upon the identification.

Abstract: A processing-in-memory (PIM) system includes a host and a PIM controller. The host is configured to generate a request for a memory access operation or a multiplication/accumulation (MAC) operation of a PIM device and also to generate a mode definition signal defining an operation mode of the PIM device. The PIM controller is configured to generate a command corresponding to the request to control the memory access operation or the MAC operation of the PIM device. When the operation mode of the PIM device is inconsistent with a mode set defined by the mode definition signal, the PIM controller controls the memory access operation or the MAC operation of the PIM device after changing the operation mode of the PIM device.

Abstract: An information processing apparatus and an information processing method capable of fulfilling an image processing function expected in a selected power control mode are provided. The information processing apparatus includes a first processor, a second processor, and a power control unit that determines one power control mode from among a plurality of stages of power control modes different in rated power, and controls power consumption of the first processor and the second processor in the determined power control mode, wherein the power control unit stops an operation of the second processor in response to the determined power control mode being a low power control mode which is a power control mode with the rated power lower than predetermined rated power.

Abstract: A data processing apparatus includes obtain circuitry that obtains a stream of instructions. The stream of instructions includes a barrier creation instruction and a barrier inhibition instruction. Track circuitry orders sending each instruction in the stream of instructions to processing circuitry based on one or more dependencies. The track circuitry is responsive to the barrier creation instruction to cause the one or more dependencies to include one or more barrier dependencies in which pre-barrier instructions, occurring before the barrier creation instruction in the stream, are sent before post-barrier instructions, occurring after the barrier creation instruction in the stream, are sent. The track circuitry is also responsive to the barrier inhibition instruction to relax the barrier dependencies to permit post-inhibition instructions, occurring after the barrier inhibition instruction in the stream, to be sent before the pre-barrier instructions.

Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.

Abstract: A transmission device includes a communication circuit configured to wirelessly communicate with a reception device, by using a plurality of wireless services including a first wireless service having a first priority and a second wireless service having a second priority that is a priority lower than the first priority, and a processing circuit configured to perform, in accordance with a first information element, allocating of an uplink radio resource to transmission data of the first wireless service, the allocating of the uplink radio resource being performed in a situation, the situation being a situation that a medium access control-protocol data unit (MAC-PDU) has been generated or can be generated in response to allocating the uplink radio resource to a transmission data of the second wireless service, the first information element indicating a value configured to control logical channel prioritization (LCP) procedure.

Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.

Abstract: Systems and methods for providing surveillance services for an unmanned vehicle are described herein. One embodiment of a method includes receiving surveilled data from a surveillance monitor regarding the unmanned aerial vehicle and at least one other aircraft, receiving trajectory data from at least one trajectory data source, and comparing the surveilled data with the trajectory data to determine whether the unmanned aerial vehicle is on path to collide with a third party aerial vehicle. In some embodiments, in response to determining that the unmanned aerial vehicle is on path to collide with the third party aerial vehicle, the method includes determining an alternate route for the unmanned aerial vehicle; and communicating at least a portion of the alternate route to the unmanned aerial vehicle.

Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

Abstract: A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting operating condition; undarken the physical compute resource responsive to detecting the activation-warranting operating condition; detect a configuration-warranting operating condition; and configure the overprovisioned microprocessor to use the undarkened physical compute resource responsive to detecting the configuration-warranting operating condition.

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

Abstract: Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

Abstract: A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.

Abstract: Apparatus and method for a hierarchical beam tracer.

Abstract: A computer-implemented method, according to one embodiment, includes: in response to a determination that an available capacity of one or more buffers in a primary cache is not outside a predetermined range, using the one or more buffers in the primary cache to satisfy all incoming I/O requests. In response to a determination that the available capacity of the one or more buffers in the primary cache is outside the predetermined range, one or more buffers in a secondary cache are allocated, and the one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests.

Abstract: An embodiment includes activating, responsive to receiving an update notification, an update mode of a mobile device, wherein the activating of the update mode includes disabling a primary communication interface and enabling a secondary communication interface, and wherein the update notification includes notification of a software update available for the mobile device. The embodiment also includes initiating execution of the software update on the mobile device while the mobile device remains in the update mode. The embodiment also includes deactivating, responsive to completing the software update, the update mode of the mobile device, wherein the deactivating of the update mode includes enabling the primary communication interface and disabling the secondary communication interface.

Abstract: Methods and systems related to construction and implementation of high radix topologies are disclosed. The nodes of the network topology are divided into a number of groups. Intra-group connections are constructed by connecting the nodes of each group according to a first complementary base graph. Inter-group connections are constructed based on a second complementary base graph and a plurality of permutation matrices. Each permutation matrix represents a pattern for selecting source group and destination group for each inter-group connection. One permutation matrix is randomly assigned to each edge of the second complementary base graph. An inter-group connection is constructed by identifying a source node and a destination node corresponding to a selected edge of the second complementary base graph, and identifying a source group and a destination group according to the permutation matrix assigned to the selected edge.

Abstract: Certain example embodiments relate to techniques for use with mainframe computing systems that include both general-purpose processors (e.g., CPs) and special-purpose processors that can be used to perform only certain limited operations (e.g., zIIPs). Certain example embodiments automatically help these special-purpose processors perform user exits and other routines thereon, rather than requiring those operations to be performed on general-purpose processors. This approach advantageously can improve system performance when executing programs including these user exits and other routines, and in a preferred embodiment, it can be accomplished in connection with a suitably-configured user exit daemon. In a preferred embodiment, the daemon and its clients can use a user exit property table or the like to communicate with one another about the state of each user exit or other routine that has been analyzed, classified, and possibly modified.

Abstract: An accelerator system can include one or more clusters of eight processing units. The processing units can include seven communication ports. Each cluster of eight processing units can be organized into two subsets of four processing units. Each processing unit can be coupled to each of the other processing units in the same subset by a respective set of two bi-directional communication links. Each processing unit can also be coupled to a corresponding processing unit in the other subset by a respective single bi-directional communication link. Input data can be divided into one or more groups of four subsets of data. Each processing unit can be configured to sum corresponding subsets of the input data received on the two bi-directional communication links from the other processing units in the same subset with the input data of the respective processing unit to generate a respective set of intermediate data.

Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.

Abstract: A method includes determining, in accordance with a first ordering, a plurality of read requests for a memory device. The plurality of read requests are added to a memory device queue for the memory device in accordance with the first ordering. The plurality of read requests in the memory device queue are processed, in accordance with a second ordering that is different from the first ordering, to determine read data for each of the plurality of read requests. The read data for the each of the plurality of read requests is added one of a set of ordered positions, based on the first ordering, of a ring buffer as the each of the plurality of reads requests is processed. The read data of a subset of the plurality of read requests is submitted based on adding the read data to a first ordered position of the set of ordered positions of the ring buffer.

Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

Abstract: Methods, systems, and apparatus are described for throttling a distributed processing system. In one aspect, a method includes identifying records being processed by a distributed processing system that performs agent processes, each of the records including a corresponding timestamp; determining, based on timestamps of the records that have been processed by a first agent process, a first agent progress; identifying a dependent agent process performed by the distributed processing system, wherein the dependent agent process processes only records that have been processed by the first agent process; determining, based on timestamps of records that have been processed by the dependent agent process, a dependent agent progress; and throttling performance of the first process based on the first agent progress and the dependent agent progress.

Abstract: A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.

Abstract: Example implementations relate to scheduling of jobs for a plurality of graphics processing units (GPUs) providing concurrent processing by a plurality of virtual GPUs. According to an example, a computing system including one or more GPUs receives a request to schedule a new job to be executed by the computing system. The new job is allocated to one or more vGPUs. Allocations of existing jobs are updated to one or more vGPUs. Operational cost of operating the one or more GPUs and migration cost of allocating the new job are minimized and allocations of the existing jobs on the one or more vGPUs is updated. The new job and the existing jobs are processed by the one or more GPUs in the computing system.

Abstract: Systems and methods for adaptive content streaming based on bandwidth are disclosed. According to one example method, content is requested for delivery. An indication of complexity of a plurality of media content items associated with the content is received. Based on the indication of complexity and an available bandwidth at the user device, at least one of the plurality media content items is selected and retrieved from the media server.

Abstract: A memory for storing a directed acyclic graph (DAG) for access by an application being executed by one or more processors of a computing device is described. The DAG includes a plurality of nodes, wherein each node represents a data point within the DAG. The DAG further includes a plurality of directional edges. Each directional edge connects a pair of the nodes and represents a covering-covered relationship between two nodes. Each node comprises a subgraph consisting of the respective node and all other nodes reachable via a covering path that comprises a sequence of covering and covered nodes. Each node comprises a set of node parameters including at least an identifier and an address range. Each node and the legal address specify a cover path. Utilizing DAG Path Addressing with bindings the memory can be organized to store a generalization hierarchy of logical propositions.

Abstract: A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.

Abstract: There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry.

Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline.

Abstract: There is provided a parallel processing device which allows consecutive parallel data processing to be performed. The parallel processing device includes: a plurality of addition units configured to selectively receive input data among output data from the plurality of input units according to configuration values for each addition unit of the plurality of addition units, and perform addition operation for the input data in parallel; and the plurality of the delay units configured to delay input data for one cycle. Each delay unit of the plurality of the delay units delays output data from each addition unit of the plurality of addition units and outputs the delayed output data to each input unit of the plurality of input units.

Abstract: A transmission device includes: a communication circuit configured to wirelessly communicate with a reception device, by using a plurality of wireless services including a first wireless service having a first priority and a second wireless service having a second priority that is a priority lower than the first priority; and a processing circuit configured to perform, in accordance with a first information element, allocating of an uplink radio resource to transmission data of the first wireless service, the allocating of the uplink radio resource being performed in a situation, the situation being a situation that a medium access control—protocol data unit (MAC-PDU) has been generated or can be generated in response to allocating the uplink radio resource to a transmission data of the second wireless service, the first information element indicating a value configured to control logical channel prioritization (LCP) procedure.

Abstract: Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes receiving execution jobs directed to a computing cluster comprising a pool of computing components coupled to at least a communication fabric. Based on properties of the execution jobs, the method includes determining resource scheduling for handling the execution jobs, the resource scheduling indicating timewise allocations of resources of the computing cluster, and initiating the execution jobs on the computing cluster according to the resource scheduling by at least instructing the communication fabric to compose compute units comprising sets of computing components selected from among the pool of computing components to handle the execution jobs. Responsive to completions of the execution jobs, the compute units are decomposed back into the pool of computing components.

Abstract: This application relates to the field of mobile communication, and in particular, to a method, an apparatus, and a system for selecting MEC node. The method includes: receiving a domain name request initiated by a terminal forwarded by the UPF, the domain name request comprising at least one of: a domain name, a destination address, or a protocol port information; obtaining a corresponding edge-application VIP from the GSLB based on the domain name request; returning a domain name response to the terminal, the domain name response comprising the edge-application VIP; receiving a service request initiated from the terminal forwarded by the UPF, a destination address of the service request being the edge-application VIP; and determining a corresponding MEC processing server according to the service request and a preset offloading policy, and offloading the service request to the corresponding MEC processing server.

Abstract: Devices and techniques for pipeline merging in a circuit are described herein. A parallel pipeline result can be obtained for a transaction index of a parallel pipeline. Here, the parallel pipeline is one of several parallel pipelines that share transaction indices. An element in a vector can be marked. The element corresponds to the transaction index. The vector is one of several vectors respectively assigned to the several parallel pipelines. Further each element in the several vectors corresponds to a possible transaction index with respective elements between vectors corresponding to the same transaction index. Elements between the several vectors that correspond to the same transaction index can be compared to determine when a transaction is complete. In response to the transaction being complete, the result can be released to an output buffer in response to the transaction being complete.

Abstract: Disclosed is an image upscaling apparatus that includes: multiple convolution layers, each configured to receive an input image or a feature map outputted by a previous convolution layer and extract features to output a feature map; and a multilayer configured to receive a final feature map outputted from the last convolution layer and output an upscaled output image. The multilayer includes: a first partition layer including first filters having a minimum size along the x-axis and y-axis directions and the same size as the final feature map along the z-axis direction; and at least one second partition layer, each including second filters, having a size greater than that of the first filter in the x-axis and y-axis directions and having a number and size of the first filter in the z-axis direction, and configured to shuffle features in the x-axis and y-axis directions of the first shuffle map.

Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.

Abstract: Memory management unit (MMU) in an application processor responds to an access request, corresponding to inspection request, including target context and target virtual address and the inspection request is for translating the target virtual address to a first target physical address. The MMU includes context cache, translation cache, invalidation queue and address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts, while avoiding duplicating contexts. The translation cache stores first address and first context identifiers second addresses, the first address corresponds to virtual address, the first context identifiers corresponds to first context, and the second addresses corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated, of the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache and the invalidation queue.

Abstract: A database system, computer program product, and a method for evaluating aggregates in database systems includes hashing of aggregation keys on a per bucket basis, and depending on a number of hashed tuples per bucket, sorting said tuples. Additionally, depending on the number of hashed tuples per bucket, the bucket is kept without change. Moreover, depending on the number of hashed tuples per bucket, maintaining a secondary hash table for a particular bucket, map tuples to it, aggregate as you map.

Abstract: A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.

Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.