Operation Patents (Class 712/30)
  • Patent number: 11403731
    Abstract: Disclosed is an image upscaling apparatus that includes: multiple convolution layers, each configured to receive an input image or a feature map outputted by a previous convolution layer and extract features to output a feature map; and a multilayer configured to receive a final feature map outputted from the last convolution layer and output an upscaled output image. The multilayer includes: a first partition layer including first filters having a minimum size along the x-axis and y-axis directions and the same size as the final feature map along the z-axis direction; and at least one second partition layer, each including second filters, having a size greater than that of the first filter in the x-axis and y-axis directions and having a number and size of the first filter in the z-axis direction, and configured to shuffle features in the x-axis and y-axis directions of the first shuffle map.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: August 2, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong Ook Jung, Sung Hwan Joo, Su Min Lee
  • Patent number: 11237757
    Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Patent number: 11216385
    Abstract: Memory management unit (MMU) in an application processor responds to an access request, corresponding to inspection request, including target context and target virtual address and the inspection request is for translating the target virtual address to a first target physical address. The MMU includes context cache, translation cache, invalidation queue and address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts, while avoiding duplicating contexts. The translation cache stores first address and first context identifiers second addresses, the first address corresponds to virtual address, the first context identifiers corresponds to first context, and the second addresses corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated, of the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache and the invalidation queue.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Boem Park, Moinul Syed, Ju-Hee Choi
  • Patent number: 11194778
    Abstract: A database system, computer program product, and a method for evaluating aggregates in database systems includes hashing of aggregation keys on a per bucket basis, and depending on a number of hashed tuples per bucket, sorting said tuples. Additionally, depending on the number of hashed tuples per bucket, the bucket is kept without change. Moreover, depending on the number of hashed tuples per bucket, maintaining a secondary hash table for a particular bucket, map tuples to it, aggregate as you map.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajesh Ramkrishna Bordawekar, Vincent Kulandaisamy, Oded Shmueli
  • Patent number: 11188303
    Abstract: A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: November 30, 2021
    Assignee: Facebook, Inc.
    Inventors: Krishnakumar Narayanan Nair, Anup Ramesh Kadkol, Ehsan Khish Ardestani Zadeh, Olivia Wu, Yuchen Hao, Thomas Mark Ulrich, Rakesh Komuravelli
  • Patent number: 11157425
    Abstract: A memory device provides a first memory area and a second memory area. A smart buffer includes; a priority setting unit receiving sensing data and a corresponding weight, determining a priority of the sensing data based on the corresponding weight, and classifying the sensing data as first priority sensing data or second priority sensing data based on the priority, and a channel controller allocating a channel to a first channel group, allocating another channel to a second channel group, assigning the first channel group to process the first priority sensing data in relation to the first memory area, and assigning the second channel group to process the second priority sensing data in relation to the second memory area.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Jo, Daeseok Byeon, Tongsung Kim
  • Patent number: 11137438
    Abstract: A method of testing a self-contained device under test having at least a circuit under test and a power source is provided. The method may include at least temporarily enabling power from the power source to the circuit under test, determining a first voltage across the circuit under test, determining a second voltage across the circuit under test after a test duration, and calculating an average current of the circuit under test based at least partially on the first voltage, the second voltage and the test duration.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 5, 2021
    Assignee: Disruptive Technologies
    Inventor: Bjornar Hernes
  • Patent number: 11054883
    Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 6, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Leonardo De Paula Rosa Piga, Samuel Naffziger, Ivan Matosevic, Indrani Paul
  • Patent number: 10983921
    Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 20, 2021
    Assignee: Oracle International Corporation
    Inventors: John Feehrer, Patrick Stabile, Gregory Onufer, John Johnson
  • Patent number: 10977854
    Abstract: Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 13, 2021
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
  • Patent number: 10931825
    Abstract: A computer system routes contact center interactions. Interactions between contact center agents and contact center queries that are received at a contact center are monitored. A ranking model is trained according to the categories of the contact center queries and the interaction scores of each handled query using machine learning. The ranking model is tested according to various metrics to ensure that the ranking model ranks the agents according to one or more selected business outcomes. A net score may be determined for each contact center agent for each query category based on a predicted interaction score and one or more non-interaction features. Incoming queries may then be routed to an appropriate contact center agent based on the category of the incoming query. Embodiments may further include a method and program product for routing contact center interactions in substantially the same manner described above.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 23, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Ambareesh Revanur, Manigandan Ms, Sateesh Kumar Potturu Naga Venkata
  • Patent number: 10922412
    Abstract: A configuration manager is associated with a Networked Control System (NCS) comprising a plurality of sensors and actuators. The configuration manager automatically discovers the hardware and/or software configurations of the sensors and actuators, and analyzes that information in order to detect whether any of the sensors and actuators have been tampered with. Provided the configuration manager detects such tampering, the configuration manager indicates the tampering to a control manager of the NCS, which then functions to minimize potential damage to the NCS.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: February 16, 2021
    Assignee: The Boeing Company
    Inventor: Balaje T. Thumati
  • Patent number: 10831698
    Abstract: Embodiments are provided herein for facilitating high link bandwidth utilization in a disaggregated computing system. A plurality of general purpose links are used to connect respective pluralities of computing elements. A traffic pattern between respective ones of a first plurality of computing elements of a first type and respective ones of a second plurality of computing elements of a second type is detected. The first and second pluralities of computing elements are dynamically connected through the respective ones of the plurality of general purpose links according to the detected traffic pattern.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Min Li, John A. Bivens, Ruchi Mahindru, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10817214
    Abstract: Provided is a storage device set. The storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-geun Park, Phil-yong Jung, Ho-jun Shim, Sang-young Ye
  • Patent number: 10761585
    Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Paul S. Diefenbaugh, Eugene Gorbatov, Andrew Henroid, Eric C. Samson, Barnes Cooper
  • Patent number: 10732985
    Abstract: An information and entertainment system of a vehicle providing a number of functions that can be used by a user of the vehicle. In the method, an order of priority of the multiple functions is set by the user, wherein the order of priority states a time availability of the functions desired by the user after an activation of the information and entertainment system. In accordance with the set order of priority, the multiple functions are carried out after a starting of the information and entertainment system, and sub-functions of the multiple functions can be immediately made available.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 4, 2020
    Assignee: VOLKSWAGEN AKTIENGESELLSCHAFT
    Inventor: Sven Höhne
  • Patent number: 10685143
    Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 16, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
  • Patent number: 10613619
    Abstract: Techniques and apparatuses are described that provide an ultra-low power mode for a low-cost force-sensing device. These techniques extend battery life of the device by minimizing power consumption for potential wake-up events. To do this, a high-pass filter (e.g., differentiator) is used to evaluate sensor signals in a time domain to provide an estimate of a rate of change of the signal. When the rate of change of the signal deviates from a baseline value by a threshold amount, then a microcontroller is woken to evaluate a large number of historical samples, such as 200 or more milliseconds worth of historical data. If a human gesture is not recognized, then the microcontroller returns to an idle state, but if a human gesture is recognized, then a high-power application processor is woken to execute an application configured to perform an operation mapped to the human gesture.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 7, 2020
    Assignee: Google LLC
    Inventors: Debanjan Mukherjee, James Brooks Miller
  • Patent number: 10599347
    Abstract: An information processing system includes: a processor in one information processing apparatus among information processing apparatuses coupled via a ring bus corresponding to a closed-loop bus; and a first memory, wherein the processor: generate a verification request for verification of completion of a write request after issuing the write request to a second memory in the information processing apparatuses; transmit the verification request to a subsequent information processing apparatus; transmit, when a request from a preceding information processing apparatus is not a verification request, the request to the subsequent information processing apparatus; transmit, when the request is a verification request to another information processing apparatus, the verification request and a request to the first memory to the subsequent information processing apparatus in order of receiving; and execute, when the request is a verification request to the one information processing apparatus, processing and generate
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Jun Kawahara, Masanori Higeta
  • Patent number: 10564633
    Abstract: A cloud-based virtualization generation service collects industrial data from multiple industrial automation systems of multiple industrial customers for storage and analysis on a cloud platform. A virtualization management component (VMC) generates a virtualized industrial automation system of an industrial automation system based on data analysis results. The VMC facilitates remotely controlling the industrial automation system based on user interactions with the virtualized industrial automation system, and updates the virtualized industrial automation system based on collected data relating to the industrial automation system. The VMC customizes a user's view of the virtualized industrial automation system based on a user's role, authorization, location, or preferences, wherein different views of the virtualized industrial automation system with different data overlays are presented on different communication devices of different users.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 18, 2020
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Juan Asenjo, John Strohmenger, Stephen Nawalaniec, Bradford H. Hegrat, Joseph A. Harkulich, Jessica Lin Korpela, Jenifer Rydberg Wright, Rainer Hessmer, John Dyck, Edward Alan Hill, Sal Conti
  • Patent number: 10558490
    Abstract: An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Ronny Ronen, Boris Ginzburg, Eliezer Weissmann
  • Patent number: 10530823
    Abstract: A method, computer-readable medium, and device for processing a stream of records with a guarantee that each record is accounted for exactly once are disclosed. A method may receive, via a first operator, a data stream having a plurality of records, the plurality of records provided by a plurality of first data sources; allocate the data stream to a plurality of shards of the first operator; process the plurality of records by each shard of the plurality of shards to generate a first output stream, where each shard being implemented with at least two replicas; and output the first output stream to a third operator or a subscriber.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: January 7, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Theodore Johnson, Vladislav Shkapenyuk
  • Patent number: 10462251
    Abstract: A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and system can be used to limit the number of items within the directory, direct content and content components to different directories, and provide an internally recognizable name for the filename. When searching the storage medium, time is not wasted searching what appears to be a seemingly endless list of filenames or subdirectory names within any single directory. A client computer can have requests for content fulfilled quicker, and the network site can reduce the load on hardware or software components. While the method and system can be used for nearly any storage media, the method and system are well suited for cache memories used with web servers.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 29, 2019
    Assignee: Open Text SA ULC
    Inventors: Conleth S. O'Connell, Jr., Eric R. White, N. Isaac Rajkumar
  • Patent number: 10234841
    Abstract: A programmable logic controller includes a state monitoring unit to monitor a state of another programmable logic controller that is a counterpart in the duplication, and a system switching control unit to transmit, to a slave device, status information including information indicating whether the programmable logic controller is a control system or a standby system, to receive the control data that is addressed to the programmable logic controller that is the control system and is transmitted from the slave device in a case where the programmable logic controller is the control system, and to switch the programmable logic controller to the control system when hindrance in the another programmable logic controller is detected in a case where the programmable logic controller is the standby system.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: March 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsuhiro Annen, Katsumi Yamagiwa
  • Patent number: 10229357
    Abstract: The present disclosure is directed to a high-capacity training and prediction machine learning platform that can support high-capacity parameter models (e.g., with 10 billion weights). The platform implements a generic feature transformation layer for joint updating and a distributed training framework utilizing shard servers to increase training speed for the high-capacity model size. The models generated by the platform can be utilized in conjunction with existing dense baseline models to predict compatibilities between different groupings of objects (e.g., a group of two objects, three objects, etc.).
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 12, 2019
    Assignee: Facebook, Inc.
    Inventors: Ou Jin, Stuart Michael Bowers, Dmytro Dzhulgakov
  • Patent number: 10108455
    Abstract: Methods and apparatus to manage and execute action in computing environments are disclosed. An example system includes a virtual machine resource platform to host a virtual compute node and a resource manager to: in response to a user request associated with the virtual compute node: determine a type of the virtual compute node; determine if an installed adapter identifies a type associated with the type of the virtual compute node; and when the adapter identifies the type associated with the type of the virtual compute node, present a user selectable identification of the adapter.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: October 23, 2018
    Assignee: VMware, Inc.
    Inventors: Phillip Smith, Timothy Binkley-Jones, Sean Bryan, Lori Marshall, Kathleen McDonough, Richard Monteleone, David Springer, Brian Williams, David Wilson
  • Patent number: 10103940
    Abstract: A method of updating at least two interconnected devices in a local network, a local network comprising at least two interconnected devices and a method of operating a remote management client and a device in this local network are provided. A resource location information of an update archive is communicated from a remote management client in the local network to the other devices in said network. The devices participating in the update communicate participation acknowledgement messages to the remote management client. The participating devices determine whether a next one of a predefined sequence of update statuses is reached. They notify the other participating devices that this update status has been reached and pause until all other participating devices have notified that they also have reached the same update status.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: October 16, 2018
    Assignee: Thomson Licensing
    Inventors: Sylvain Dumet, Dirk Van De Poel
  • Patent number: 10067556
    Abstract: A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Patent number: 10055454
    Abstract: The present invention discloses a method for executing an SQL operator on compressed data chunk. The method comprising the step of: receiving SQL operator, accessing compressed data chunk blocks, receive e full set of derivatives of the compression scheme, check compression rules based on the compression scheme and relevant operator for approving SQL operation on compressed data and in case of approval applying respective SQL operator on relevant compressed data chunks.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 21, 2018
    Assignee: SQREAM TECHNOLOGIES LTD
    Inventors: Kostya Varakin, Ami Gal
  • Patent number: 10042417
    Abstract: A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Patent number: 9979710
    Abstract: A wireless local area network system establishes a PASSPOINT™ connection between a mobile station and a hotspot using an enhanced single SSID method or an enhanced dual SSID method. In the dual SSID method, an access point associates and authenticates a mobile device to a secondary SSID of the access point during enrollment and provisioning. After enrollment, the access point authenticates the mobile station to a primary SSID of the access point using the credential that the mobile station received from an online sign-up (“OSU”) server in connection with the secondary SSID. In the single SSID method, an access point performs two levels of authentication. During authentication, communications are limited to an 802.1x controlled port running on the mobile station and access point. After a first authentication, communications between the OSU server and the mobile station are unblocked. After the second authentication, all traffic from the mobile station is unblocked.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: May 22, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Liwen Chu, George A. Vlantis
  • Patent number: 9921886
    Abstract: A mobile terminal device receives a request for a sensing operation from an application program, specifies candidate processors that are to perform condition determination to determine whether an event output from a sensor performing the sensing operation of the received request satisfies conditions for notification, the conditions being designated by the application program, calculates an evaluation value of electricity consumed by each of the candidate processors in the condition determination, using frequency of the event of the sensing operation of the received request in frequency data, the frequency data linking an event output from a sensor to frequency of generation of the event, and selects a candidate processor having an optimal evaluation value.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 20, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Eiji Hasegawa, Manabu Nakao, Toru Kamiwada
  • Patent number: 9916344
    Abstract: Embodiments of the present invention provide efficient systems and methods for processing large data sets using a composite function. Embodiments of the present invention can be used to compute a broad range of composite functions in a single map-reduce job. Each mapper computes an additive function G on a set of specified data partitions, and then passes the results to one or more reducers. The one or more reducers can then compute a function F, using the aggregate results of function G and data from a single partition.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Svetlana Levitan, Damir Spisic
  • Patent number: 9839849
    Abstract: A software emulator for emulating a handheld video game platform such as GAME BOY®, GAME BOY COLOR® and/or GAME BOY ADVANCE® on a low-capability target platform (e.g., a seat-back display for airline or train use, a personal digital assistant, a cell phone) uses a number of features and optimizations to provide high quality graphics and sound that nearly duplicates the game playing experience on the native platform. Some exemplary features include use of bit BLITing, graphics character reformatting, modeling of a native platform liquid crystal display controller using a sequential state machine, and selective skipping of frame display updates if the game play falls behind what would occur on the native platform.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: December 12, 2017
    Assignee: Nintendo Co., Ltd.
    Inventor: Patrick J. Link
  • Patent number: 9842010
    Abstract: A computational device maintains a spinlock for exclusive access of a resource by a process of a plurality of processes. In response to determining by the process that a turn for securing the spinlock has not arrived for the process, a sleep duration is determined for the process, prior to making a next attempt to secure the spinlock.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seamus J. Burke, Trung N. Nguyen, Louis A. Rasor
  • Patent number: 9766875
    Abstract: A method of processing multimedia data includes: separating a defined application kernel into a data patch kernel and a data processing kernel; requesting, by the data processing kernel, access to patch data of the multimedia data, from the data patch kernel; performing, by the data patch kernel, an operation that is independent of the request and preparing data for the data access based on the request; and performing, by the data processing kernel, an arithmetic operation on work items of the prepared data when the data has been prepared by the data patch kernel.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongha Park, Hyunsuk Kim, Jinaeon Lee
  • Patent number: 9740511
    Abstract: A method of enhancing performance of an application executing in a parallel processor and a system for executing the method are disclosed. A block size for input to the application is determined. Input is partitioned into blocks having the block size. Input within each block is sorted. The application is executed with the sorted input.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 22, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Alexander Lyashevsky
  • Patent number: 9596295
    Abstract: Systems and methods for improving the time and cost to calculate connected components in a distributed graph are disclosed. One method includes reducing a quantity of map-reduce rounds used to determine a cluster assignment for a node in a large distributed graph by alternating between two hashing functions in the map stage of a map-reduce round and storing the cluster assignment for the node in a memory. Another method includes reducing a quantity of messages sent during map-reduce rounds by performing a predetermined quantity of rounds to generate, for each node, a set of potential cluster assignments, generating a data structure in memory to store a mapping between each node and its potential cluster assignment, and using the data structure during remaining map-reduce rounds, wherein the remaining map-reduce rounds do not send messages between nodes. The method can also include storing the cluster assignment for the node in a memory.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 14, 2017
    Assignee: Google Inc.
    Inventors: Seyed Vahab Mirrokni Banadaki, Raimondas Kiveris, Vibhor Rastogi, Silvio Lattanzi, Sergei Vassilvitskii
  • Patent number: 9582341
    Abstract: A semiconductor device may include a first processor transferring a plurality of command data sets, a mailbox receiving and storing the plurality of command data sets, and a second processor receiving command data sets of the mailbox, wherein the first processor may transfer at least one abort slot number to the mailbox, and wherein the mailbox may search and abort a command data set having a slot number which is identical to an abort slot number among the plurality of command data sets.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: February 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Joung Young Lee, Duk Rae Lee, Dong Jae Shin
  • Patent number: 9569365
    Abstract: A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: February 14, 2017
    Assignee: ARM Limited
    Inventors: Stuart David Biles, Richard Roy Grisenthwaite, Bruce James Mathewson
  • Patent number: 9535705
    Abstract: In a typical embodiment, a parallel processor is provided that includes: A plurality of parallel processing units that are interconnected to provide a flexible hardware programmable, scalable and re-configurable parallel processor that executes different functions in a parallel processor space domain instead of a processor (serial processor) time domain. Each parallel processing unit includes a flexible processing engine with its inputs and outputs connected to MDDP-RAM blocks. The MDDP-RAM blocks provide the processing engine with different channels' data and coefficients. The processing engine and the MDDP-RAM blocks are controlled by a system processor (or other control scheme hardware) via the parameter blocks to enable high hardware flexibility and software programmability.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: January 3, 2017
    Inventor: Asher Hazanchuk
  • Patent number: 9507638
    Abstract: One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: November 29, 2016
    Assignee: NVIDIA Corporation
    Inventors: Philip Alexander Cuadra, Karim M. Abdalla, Jerome F. Duluk, Jr., Luke Durant, Gerald F. Luiz, Timothy John Purcell, Lacky V. Shah
  • Patent number: 9454548
    Abstract: A method, article of manufacture, and apparatus for managing data. In some embodiments, this includes an initial instruction for a file stored in a first storage system, determining that the initial instruction is not supported by the first storage system, identifying a combination of instructions to the first storage system after determining that the initial instruction is not supported by the first storage system, wherein the combination of instructions is based on the initial instruction, performing the identified combination of instructions on the file stored in the first storage system, and storing results of the performed identified combination of instructions.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 27, 2016
    Assignee: EMC Corporation
    Inventors: Lei Chang, Tao Ma, Zhanwei Wang, Lirong Jian, Lili Ma, Gavin Sherry
  • Patent number: 9411532
    Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: August 9, 2016
    Assignee: PACT XPP Technologies AG
    Inventors: Martin Vorbach, Volker Baumgarte, Frank May, Armin Nuckel
  • Patent number: 9411832
    Abstract: A method, article of manufacture, and apparatus for managing data. In some embodiments, this includes an initial instruction for a file stored in a first storage system, determining that the initial instruction is not supported by the first storage system, identifying a combination of instructions to the first storage system after determining that the initial instruction is not supported by the first storage system, wherein the combination of instructions is based on the initial instruction, performing the identified combination of instructions on the file stored in the first storage system, and storing results of the performed identified combination of instructions.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 9, 2016
    Assignee: EMC Corporation
    Inventors: Lei Chang, Tao Ma, Zhanwei Wang, Lirong Jian, Lili Ma, Gavin Sherry
  • Patent number: 9405580
    Abstract: The present invention relates to the field of real-time executives and their adaptation for secure execution on a multicore processor. There is defined, in addition to the level of certification intrinsic to each task, a level of security relating to the criticality of the execution of the instance of the task in its context and by a method of sequencing distributed over the various cores which make it possible to exchange, during each time interval, the information relating to the level of certification and to the level of security of each of the tasks getting ready to be launched. A decision is then taken on each core for launching the task envisaged as a function of the relevant information received from the other cores.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 2, 2016
    Assignee: SAGEM DEFENSE SECURITE
    Inventor: Christian Valpard
  • Patent number: 9235792
    Abstract: High speed reading of fiscal information from memory is enabled while complying with financial regulations. Including fiscal memory 10 that stores fiscal information, a first control unit 5 that controls communication with the host computer 2 and operates at a first processing speed, and a second control unit 7 that controls operation of the fiscal memory 10 and operates at a second processing speed that is lower than the first processing speed, the second control unit 7 performs a write process writing fiscal information received from the host computer 2 to fiscal memory 10, and the first control unit 5 executes a read process reading the fiscal information stored in the fiscal memory 10 without involving processing by the second control unit 7.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 12, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Koji Koseki
  • Patent number: 9152554
    Abstract: A memory system includes a non-volatile memory, a compressor capable of compressing data, an encryptor which encrypts data, a decryptor which decrypts data, and a data flow controller. The data flow controller is configured to perform first and second processes. In the first process, the data flow controller causes the encryptor to encrypt user data received from a host in a non-compressed state, and causes the encrypted user data to be written into the non-volatile memory via the second area. In the second process, the data flow controller causes the encrypted user data to be read out from the non-volatile memory, causes the decryptor to decrypt the encrypted user data, causes the compressor to compress the decrypted user data, causes the encryptor to encrypt the compressed user data, and causes the encrypted and compressed user data to be written into the non-volatile memory.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toru Uno
  • Patent number: 9135060
    Abstract: Provided are a method and apparatus for migrating a task in a multi-core platform including a plurality of cores. The method includes transmitting codes of the task that is being performed in a first core among the plurality of cores to a second core among the plurality of cores, the transmitting of the codes being performed while performing the task at the first core, and resuming performing of the task in the second core based on the transmitted codes.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung-keun Park
  • Publication number: 20150134931
    Abstract: According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the processor device in executing an operation associated with a computer process.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, Michael S. Bertone, David A. Carlson