Abstract: Disclosed are embodiments for sorting rows of a dataset after a JOIN operation. In one embodiment, a method is disclosed comprising performing a JOIN operation on an annotation dataset, the performing of the JOIN operation generating an unordered dataset; grouping a plurality of rows in the unordered dataset into a plurality of buckets, the grouping performed based on a root dataset associated with the annotation dataset; sorting each bucket, the sorting comprising sorting each bucket independently; and combining each sorted bucket into a sorted dataset.

Abstract: Methods, systems, and devices for access control configurations for inter-processor communications are described to support reconfiguration of a dynamic access control configuration at a device. For example, additional configuration fields may be added to existing access control rules of the device, where these additional fields may be configured by a processor sending information to a receiving processor, via a shared memory resource or region of the device. The additional fields may include a read-only value which may specify a processor which has exclusive write permission for a memory region of the share memory. This value may indicate the sending processor of the memory region, and the value may be set by access control hardware when the additional field is changed. Other processors of the device may be prevented from writing to the memory region.

Abstract: A service processing method and system, and a device to reduce a large quantity of back end servers, and to simplify a structure of a distributed system where the method includes receiving, by a master device in a resource pool, a service processing request, determining, by the master device, a resource required by a service, determining, according to a remaining resource of each slave device in the resource pool, a slave device that satisfies the resource required by the service, and assigning, by the master device, the service to the corresponding slave device for processing, where the master device and the slave device are both video surveillance front end devices, and the master device determines a device that is in the front end devices and whose remaining resource satisfies a preset threshold as the slave device.

Abstract: A global-level manager access a work order from a client and parameters associated with the work order. A service level agreement to meet the work order parameters is determined. The service level agreement includes a price. An indication is received from the client that the service level agreement is accepted. The one or more input files are partitioned into multiple shards, and the work order into multiple jobs. The jobs are distributed among a plurality of clusters to be processed using underutilized computing resources in the clusters. The job outputs are combined to form the work order output. The jobs are monitored to insure that the deadline for completion of the work order will be met.

Abstract: A series circuit and a computing device includes a power supply terminal, a ground terminal and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series. A communication line is connected between adjacent chips of the first predetermined number of chips. A portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a second connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: A bluetooth communication method includes: a first communication device establishing bluetooth connection with a second communication device, wherein the first communication device is configured to execute multiple tasks; the first communication device communicating with the second communication device through the bluetooth connection, to allocate at least one task of the multiple tasks to the second communication device for execution; wherein the at least one task includes a scan task; and the first communication device receiving an execution result of the at least one task from the second communication device through the bluetooth connection.

Abstract: Techniques disclosed herein provide an approach for managing aggregation service hierarchies. In some embodiments, a hierarchy of an aggregation service is identified. The hierarchy comprises a plurality of nodes, where a respective node is associated with at least one host computer. The aggregation service places resource consumers based on the nodes. A host computer is assigned as a child host of a leaf node based on a clustering heuristic. The clustering heuristic requires the host computer to have access to at least one resource that is accessible to an existing child host of the leaf node. A resource consumer associated with the leaf node is executed on the host computer.

Abstract: An apparatus is provided which comprises: a first engine buffer to receive a first engine request; a first engine register coupled to the first engine buffer, wherein the first engine register is to store first engine credits associated with the first engine buffer; a second engine buffer to receive a second engine request; a second engine register coupled to the second engine buffer, wherein the second engine register is to store second engine credits associated with the second engine buffer; and a common buffer which is common to the first and second engines, wherein the first engine credits represents one or more slots in the common buffer for servicing the first engine request for access to a common resource, and wherein the second engine credits represents one or more slots in the common buffer for servicing the second engine request for access to the common resource.

Abstract: Configuration devices in a module. In some embodiments, a radio frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a first switch coupled to a first device and a third line. The radio-frequency module further includes a module coupled to the serial bus and the first switch, the module configured to determine whether first data is detected on a first serial data line, determine whether second data is detected on a second serial data line, adjust a configuration of the first switch when the first data is detected on the first serial data line and the second data is detected on the second serial data line.

Abstract: A service processing method and system, and a device to reduce a large quantity of back end servers, and to simplify a structure of a distributed system where the method includes receiving, by a master device in a resource pool, a service processing request, determining, by the master device, a resource required by a service, determining, according to a remaining resource of each slave device in the resource pool, a slave device that satisfies the resource required by the service, and assigning, by the master device, the service to the corresponding slave device for processing, where the master device and the slave device are both video surveillance front end devices, and the master device determines a device that is in the front end devices and whose remaining resource satisfies a preset threshold as the slave device.

Abstract: The disclosure relates to a method, terminal and storage medium for starting software. A method for starting software carried out in an electronic apparatus includes: configuration information, which is information for configuring a starting acceleration mode adopted for starting target software, is acquired; a starting acceleration level of the target software is determined according to the configuration information; at least one of a number of prefetching operations and number of files prefetched in each prefetching operation corresponding to the determined starting acceleration level is acquired; starting files of the target software are opened and data in the target software is prefetched into a memory in each prefetching operation according to the at least one of the determined number of prefetching operations and number of files prefetched in each prefetching operation; and the target software is started according to the data prefetched into the memory.

Abstract: Systems and methods related to processing transaction verification operations in decentralized applications via a fixed pipeline hardware architecture are described herein. The fixed pipeline hardware architecture may include and/or support at least a crypto engine and a read set validation engine. The crypto engine may itself comprise a hardware architecture configured to perform cryptographic operations necessary to validate signatures for transactions in decentralized applications. In various implementations, the hardware architecture of a crypto engine may include a scheduler and a series of crypto execution units configured to operate in parallel. The read set validation engine may be configured to verify whether a transaction is valid based on a comparison of an incoming transaction state indicating transaction data for the transaction and a local state related to the transaction.

Abstract: Multiple processors share access, via a bus, to a pipelined NFA engine. The NFA engine can implement an NFA of the type that is not a DFA (namely, it can be in multiple states at the same time). One of the processors communicates a configuration command, a go command, and an event generate command across the bus to the NFA engine. The event generate command includes a reference value. The configuration command causes the NFA engine to be configured. The go command causes the configured NFA engine to perform a particular NFA operation. Upon completion of the NFA operation, the event generate command causes the reference value to be returned back across the bus to the processor.

Abstract: An implementation of a method for live-migrating virtual machines includes: acquiring, when receiving a request for live-migrating a virtual machine to a target physical machine, CPU information of a source physical machine and CPU information of the target physical machine; determining whether a CPU instruction set architecture of the source physical machine is compatible with a CPU instruction set architecture of the target physical machine; determining whether CPU features of the source physical machine are compatible with CPU features of the target physical machine, if the two CPU instruction set architecture are compatible; determining whether incompatible CPU features between the source physical machine and the target physical machine are in a preset list, if the two CPU instruction set architecture are not compatible; and live-migrating the virtual machine from the source physical machine to the target physical machine, in response to determining that the incompatible CPU features are in the preset lis

Abstract: Techniques disclosed herein provide an approach for creating and managing aggregation service hierarchies, such as hierarchies used in distributed scheduling services and heartbeat services. In one embodiment, management nodes accept host computer registration events and add host computers to a hierarchy used as the aggregation mechanism in an aggregation service. The management nodes each manage a portion of the hierarchy and configure registered hosts to take the roles of leaf, branch, and root nodes in the hierarchy. Further, the management nodes dynamically mutate the hierarchy by reassigning host roles, in response to host additions and failures, thereby maximizing fault tolerance/high availability and efficiency.

Abstract: A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector.

Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.

Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.

Abstract: A synchronization method of multiple threads is executed by a computer. The synchronization method includes determining a type of a synchronization process of a first thread performing the synchronization process for synchronization with a second thread; starting time measurement when the type of the synchronization process of the first thread is a first type; performing the synchronization process of the first thread and a synchronization process of the second thread based on a synchronization process history of the second thread when the measured time exceeds a permitted response period of the first thread; and updating the permitted response period and performing the synchronization processes of the first thread and the second thread based on the synchronization process history of the second thread, when another processing request is received.

Abstract: This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

Abstract: Adaptive data collection practices in a multi-processor device. The device may include a first processor and a second processor. The first processor may operate in any of a plurality of power states. The first processor may indicate to the second processor when it transitions to a different power state. The second processor may collect information relating to its operation. The second processor may collect the information according to different information collecting modes depending on in which power state the first processor is operating. Less information may be collected in an information collecting mode corresponding to a lower power state of the first processor than in an information collecting mode corresponding to a higher power state of the first processor.

Abstract: Methods and systems for load generation for scalable load testing are disclosed. A plurality of job descriptions are generated based on a load step description. The load step description specifies a total transaction frequency or a total number of concurrent connections for a load test of a service over a period of time. The job descriptions specify subdivisions of the total transaction frequency or the total number of concurrent connections and subdivisions of the period of time. The job descriptions are placed in a job queue. A plurality of worker hosts remove the job descriptions from the job queue and concurrently execute local jobs based on the job descriptions.

Abstract: An electronic device and an input method are provided.

Abstract: A method is disclosed for safe communication between a communication system by way of an OFDM method between a master and a slave, the master being able to communicate via a management channel and via a payload data channel with the slave. In an embodiment, the master assigns frequency spectra to be used for the payload data channel. The master is allocated an address of the slave and the master subsequently allocates the address to one of the frequency spectra to be used for the payload data channel. The slave stores the address transferred to it in its first microcontroller and the slave stores the address received via the payload data channel in the second microcontroller. The slave then checks whether the stored addresses match.

Abstract: The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced.

Abstract: An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume different amounts of power. Also, any of the multiple processors may perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.

Abstract: Systems, methods and products directed toward facilitating firmware updates in a hybrid computing environment. One aspect includes providing a primary operating environment and a secondary operating environment in an information handling device; downloading one or more firmware update packages appropriate for the secondary operating environment to the primary operating environment; and executing a firmware update tool from the primary operating environment, the firmware update tool being configured to install the one or more firmware update packages on the secondary operating environment. Other embodiments are described herein.

Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Abstract: In one example, a network device includes a network interface that receives a packet, a storage card that stores session data for monitored network sessions, a plurality of service processing cards that process packets of respective subsets of the network sessions, wherein each of the service processing cards comprises a respective memory to store session data for the respective subset of the network sessions processed by the corresponding service processing card, and a switch fabric coupled to the network interface, the storage card, and the plurality of service processing cards. One or more of the plurality of service cards process the received packet based on the session data stored by the storage card. The one or more of the plurality of service cards retrieve the session data for the network session to which the packet corresponds from the storage card and store the retrieved session data in the respective memory.

Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.

Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.

Abstract: The present application is directed towards systems and methods for coordination and management of a shared resource in a multi-core system. In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core, and independent and uncoordinated initialization by multiple cores may cause errors. The present invention provides systems and methods for coordinating such initialization and use through a handshaking protocol.

Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

Abstract: An information processing device includes: a measurement unit 10 for measuring respective use rates of a plurality of coprocessors each for executing a job, respective use rates of a plurality of interface cards each for passing data input or output by each of the plurality of coprocessors, and respective latencies and respective throughputs in communication between the plurality of coprocessors and the plurality of interface cards; and a determination unit 20 for determining a coprocessor that is to execute the job from among the plurality of coprocessors, based on a result of the measurement by the measurement unit 10.

Abstract: An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.

Abstract: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread independent of the operation of the slave hardware thread/hardware resource.

Abstract: A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective channels, and the interconnect device performs an arbitrating operation on the requests. The service controllers control request flows from the master devices adaptively depending on an operational environment change of the SOC.

Abstract: System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a device. The SPI bridge additionally includes a first analog multiplexor control configured to route signals to a circuitry. The SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control.

Abstract: A method is disclosed to manage a multi-processor system with one or more multiple-core coprocessors by intercepting coprocessor offload infrastructure application program interface (API) calls; scheduling user processes to run on one of the coprocessors; scheduling offloads within user processes to run on one of the coprocessors; and affinitizing offloads to predetermined cores within one of the coprocessors by selecting and allocating cores to an offload, and obtaining a thread-to-core mapping from a user.

Abstract: Executing an accelerator application program in a hybrid computing environment with a host computer having a host computer architecture; an accelerator having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions; the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where executing an accelerator application program on an accelerator includes receiving, from a host application program on the host computer, operating information for an accelerator application program; designating a directory as a CWD for the accelerator application program, separate from any other CWDs of any other applications running on the accelerator; assigning, to the CWD, a name that is unique with respect to names of other CWDs of other applications in the computing environment; and starting the accelerator application program on the a

Abstract: A multistage module expansion system and multistage module communication method, applicable to a set-top box, are introduced. The system includes a master module, at least a preceding expansion module, and at least a succeeding expansion module. The master module generates and sends a control instruction to the preceding expansion module and the succeeding expansion module. The preceding expansion module and the succeeding expansion module each determine whether the control instruction is of a type executable by the preceding expansion module and the succeeding expansion module, respectively. If the determination is affirmative, the preceding expansion module creates and sends a preceding data packet to the master module, and the succeeding expansion module creates and sends a succeeding data packet to the preceding expansion module, such that the preceding expansion module sends the succeeding data packet to the master module.

Abstract: A system and method are provided for controlling a printing press including a plurality of print units and, optionally, a folder. Each print unit has one or more cylinders, a motor for driving the cylinders; an encoder for providing a cylinder position signal, a controller coupled to the encoder, the motor, a bus which interconnects each of the controllers and an input port for designating the controller as either master or slave. Any one of the controllers is selectively set as a master controller and the remaining controllers are set as slave controllers. The master controller generates a control signal based on a signal from the input port and outputs the control signal to the motor via the output port and to the slave controllers via the bus. Each of the slave controllers outputs a signal on the respective output port based on the received control signal.

Abstract: Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.

Abstract: The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced.

Abstract: A processor of a data processing system executes a controlling thread of a program and detects occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the controlling thread of the program, the processor initiates execution of an assist thread of the program such that the processor simultaneously executes the assist thread and controlling thread of the program.

Abstract: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.

Abstract: One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.

Abstract: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.

Abstract: Aspects of the present invention reduce a lock wait time in a distributed processing environment. A plurality of wait-for dependencies between a first plurality of transactions and a second plurality of transactions in a distributed processing environment is identified. The first plurality of transactions waits for the second plurality of transactions to release a plurality of locks on a plurality of shared resources. An amount of time the first plurality of transactions will wait for the second plurality of transactions in the distributed processing environment is determined based on the plurality of wait-for dependencies between the first plurality of transactions and the second plurality of transactions. Historical transaction data related to the plurality of wait-for dependencies between the first plurality of transactions and the second plurality of transactions is analyzed.

Abstract: An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored.