Master/slave Patents (Class 712/31)
  • Patent number: 10805231
    Abstract: A service processing method and system, and a device to reduce a large quantity of back end servers, and to simplify a structure of a distributed system where the method includes receiving, by a master device in a resource pool, a service processing request, determining, by the master device, a resource required by a service, determining, according to a remaining resource of each slave device in the resource pool, a slave device that satisfies the resource required by the service, and assigning, by the master device, the service to the corresponding slave device for processing, where the master device and the slave device are both video surveillance front end devices, and the master device determines a device that is in the front end devices and whose remaining resource satisfies a preset threshold as the slave device.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 13, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Jianbing Jiao
  • Patent number: 10747550
    Abstract: The disclosure relates to a method, terminal and storage medium for starting software. A method for starting software carried out in an electronic apparatus includes: configuration information, which is information for configuring a starting acceleration mode adopted for starting target software, is acquired; a starting acceleration level of the target software is determined according to the configuration information; at least one of a number of prefetching operations and number of files prefetched in each prefetching operation corresponding to the determined starting acceleration level is acquired; starting files of the target software are opened and data in the target software is prefetched into a memory in each prefetching operation according to the at least one of the determined number of prefetching operations and number of files prefetched in each prefetching operation; and the target software is started according to the data prefetched into the memory.
    Type: Grant
    Filed: October 1, 2017
    Date of Patent: August 18, 2020
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Wangsheng Zhou
  • Patent number: 10404473
    Abstract: Systems and methods related to processing transaction verification operations in decentralized applications via a fixed pipeline hardware architecture are described herein. The fixed pipeline hardware architecture may include and/or support at least a crypto engine and a read set validation engine. The crypto engine may itself comprise a hardware architecture configured to perform cryptographic operations necessary to validate signatures for transactions in decentralized applications. In various implementations, the hardware architecture of a crypto engine may include a scheduler and a series of crypto execution units configured to operate in parallel. The read set validation engine may be configured to verify whether a transaction is valid based on a comparison of an incoming transaction state indicating transaction data for the transaction and a local state related to the transaction.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 3, 2019
    Assignee: Accelor Ltd.
    Inventors: Shiwen Hu, Xiaohan Ma, Guojun Chu
  • Patent number: 10362093
    Abstract: Multiple processors share access, via a bus, to a pipelined NFA engine. The NFA engine can implement an NFA of the type that is not a DFA (namely, it can be in multiple states at the same time). One of the processors communicates a configuration command, a go command, and an event generate command across the bus to the NFA engine. The event generate command includes a reference value. The configuration command causes the NFA engine to be configured. The go command causes the configured NFA engine to perform a particular NFA operation. Upon completion of the NFA operation, the event generate command causes the reference value to be returned back across the bus to the processor.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: July 23, 2019
    Assignee: Netronome Systems, Inc.
    Inventors: Gavin J. Stark, Steven W. Zagorianakos
  • Patent number: 10318331
    Abstract: An implementation of a method for live-migrating virtual machines includes: acquiring, when receiving a request for live-migrating a virtual machine to a target physical machine, CPU information of a source physical machine and CPU information of the target physical machine; determining whether a CPU instruction set architecture of the source physical machine is compatible with a CPU instruction set architecture of the target physical machine; determining whether CPU features of the source physical machine are compatible with CPU features of the target physical machine, if the two CPU instruction set architecture are compatible; determining whether incompatible CPU features between the source physical machine and the target physical machine are in a preset list, if the two CPU instruction set architecture are not compatible; and live-migrating the virtual machine from the source physical machine to the target physical machine, in response to determining that the incompatible CPU features are in the preset lis
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: June 11, 2019
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Wen Chai, Yu Zhang
  • Patent number: 10305745
    Abstract: Techniques disclosed herein provide an approach for creating and managing aggregation service hierarchies, such as hierarchies used in distributed scheduling services and heartbeat services. In one embodiment, management nodes accept host computer registration events and add host computers to a hierarchy used as the aggregation mechanism in an aggregation service. The management nodes each manage a portion of the hierarchy and configure registered hosts to take the roles of leaf, branch, and root nodes in the hierarchy. Further, the management nodes dynamically mutate the hierarchy by reassigning host roles, in response to host additions and failures, thereby maximizing fault tolerance/high availability and efficiency.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 28, 2019
    Assignee: VMWARE, INC.
    Inventors: Vadim Spivak, Maithem Munshed, Amar Padmanabhan, Michi Mutsuzaki
  • Patent number: 9941943
    Abstract: A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 10, 2018
    Assignee: XILINX, INC.
    Inventors: Michael Wu, Christopher H. Dick, Christoph E. Studer
  • Patent number: 9898301
    Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
  • Patent number: 9817670
    Abstract: When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Nitin Gupta, Mehulkumar J. Patel, Deepak C. Shetty
  • Patent number: 9690633
    Abstract: A synchronization method of multiple threads is executed by a computer. The synchronization method includes determining a type of a synchronization process of a first thread performing the synchronization process for synchronization with a second thread; starting time measurement when the type of the synchronization process of the first thread is a first type; performing the synchronization process of the first thread and a synchronization process of the second thread based on a synchronization process history of the second thread when the measured time exceeds a permitted response period of the first thread; and updating the permitted response period and performing the synchronization processes of the first thread and the second thread based on the synchronization process history of the second thread, when another processing request is received.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Toshiya Otomo
  • Patent number: 9632492
    Abstract: This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: April 25, 2017
    Assignee: Rockwell Automation Asia Pacific Business Ctr. Pte., Ltd.
    Inventor: Kian Kiat Koh
  • Patent number: 9411396
    Abstract: Adaptive data collection practices in a multi-processor device. The device may include a first processor and a second processor. The first processor may operate in any of a plurality of power states. The first processor may indicate to the second processor when it transitions to a different power state. The second processor may collect information relating to its operation. The second processor may collect the information according to different information collecting modes depending on in which power state the first processor is operating. Less information may be collected in an information collecting mode corresponding to a lower power state of the first processor than in an information collecting mode corresponding to a higher power state of the first processor.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 9, 2016
    Assignee: Apple Inc.
    Inventors: Ben-Heng Juang, Arjuna Sivasithambaresan, Jesus A Gutierrez Gomez, Karthik Anantharaman, Srinivasan Nimmala
  • Patent number: 9396039
    Abstract: Methods and systems for load generation for scalable load testing are disclosed. A plurality of job descriptions are generated based on a load step description. The load step description specifies a total transaction frequency or a total number of concurrent connections for a load test of a service over a period of time. The job descriptions specify subdivisions of the total transaction frequency or the total number of concurrent connections and subdivisions of the period of time. The job descriptions are placed in a job queue. A plurality of worker hosts remove the job descriptions from the job queue and concurrently execute local jobs based on the job descriptions.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 19, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Carlos Alejandro Arguelles, Ramakrishnan Hariharan Chandrasekharapuram
  • Patent number: 9354664
    Abstract: An electronic device and an input method are provided.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 31, 2016
    Assignees: BEIJING LENOVO SOFTWARE LTD., LENOVO (BEIJING) CO., LTD.
    Inventor: Qian Zhao
  • Patent number: 9112642
    Abstract: A method is disclosed for safe communication between a communication system by way of an OFDM method between a master and a slave, the master being able to communicate via a management channel and via a payload data channel with the slave. In an embodiment, the master assigns frequency spectra to be used for the payload data channel. The master is allocated an address of the slave and the master subsequently allocates the address to one of the frequency spectra to be used for the payload data channel. The slave stores the address transferred to it in its first microcontroller and the slave stores the address received via the payload data channel in the second microcontroller. The slave then checks whether the stored addresses match.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: August 18, 2015
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Markus Premke
  • Patent number: 9032115
    Abstract: The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: May 12, 2015
    Assignee: ZTE Corporation
    Inventors: Zhiwei Mo, Ning Chen, Hao Wang
  • Patent number: 9003208
    Abstract: An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume different amounts of power. Also, any of the multiple processors may perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: April 7, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Gregory H. Parks, Erik Michael Geidl, Andrew John Fuller, Troy Scott Jones
  • Patent number: 8972995
    Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: March 3, 2015
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Ruben Khazhakyan, Harutyan Aslanyan, Drew E. Wingard, Chien-Chun Chou
  • Patent number: 8972966
    Abstract: Systems, methods and products directed toward facilitating firmware updates in a hybrid computing environment. One aspect includes providing a primary operating environment and a secondary operating environment in an information handling device; downloading one or more firmware update packages appropriate for the secondary operating environment to the primary operating environment; and executing a firmware update tool from the primary operating environment, the firmware update tool being configured to install the one or more firmware update packages on the secondary operating environment. Other embodiments are described herein.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: March 3, 2015
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Scott E. Kelso, Jian Li, Steven R. Perrin, Matthew P. Roper, Bradley P. Strazisar, Jianbang Zhang
  • Patent number: 8937942
    Abstract: In one example, a network device includes a network interface that receives a packet, a storage card that stores session data for monitored network sessions, a plurality of service processing cards that process packets of respective subsets of the network sessions, wherein each of the service processing cards comprises a respective memory to store session data for the respective subset of the network sessions processed by the corresponding service processing card, and a switch fabric coupled to the network interface, the storage card, and the plurality of service processing cards. One or more of the plurality of service cards process the received packet based on the session data stored by the storage card. The one or more of the plurality of service cards retrieve the session data for the network session to which the packet corresponds from the storage card and store the retrieved session data in the respective memory.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: January 20, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Xianzhi Li, Qingming Ma, Jianhua Gu, Sanjay Gupta, Zeyong Lin, Dongsheng Mu
  • Publication number: 20150019839
    Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
    Type: Application
    Filed: October 1, 2014
    Publication date: January 15, 2015
    Inventors: Charles S. Cardinell, Bernhard Laubli, Timothy J. Van Patten
  • Patent number: 8935511
    Abstract: Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles S. Cardinell, Bernhard Laubli, Timothy J. Van Patten
  • Patent number: 8892783
    Abstract: The present application is directed towards systems and methods for coordination and management of a shared resource in a multi-core system. In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core, and independent and uncoordinated initialization by multiple cores may cause errors. The present invention provides systems and methods for coordinating such initialization and use through a handshaking protocol.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 18, 2014
    Assignee: Citrix Systems, Inc.
    Inventor: Ramanjaneyulu Y Talla
  • Publication number: 20140281381
    Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.
    Type: Application
    Filed: January 23, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: DONG-HAN LEE, SUNG-CHUL YOON, SUNG-HOO CHOI, JAE-SOP KONG, KEE-MOON CHUN
  • Publication number: 20140250287
    Abstract: An information processing device includes: a measurement unit 10 for measuring respective use rates of a plurality of coprocessors each for executing a job, respective use rates of a plurality of interface cards each for passing data input or output by each of the plurality of coprocessors, and respective latencies and respective throughputs in communication between the plurality of coprocessors and the plurality of interface cards; and a determination unit 20 for determining a coprocessor that is to execute the job from among the plurality of coprocessors, based on a result of the measurement by the measurement unit 10.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 4, 2014
    Applicant: NEC CORPORATION
    Inventor: SHUNSUKE AKIMOTO
  • Publication number: 20140229706
    Abstract: A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread independent of the operation of the slave hardware thread/hardware resource.
    Type: Application
    Filed: March 11, 2013
    Publication date: August 14, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Publication number: 20140229707
    Abstract: An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 14, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ryutaro FUTAMI
  • Publication number: 20140208071
    Abstract: A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective channels, and the interconnect device performs an arbitrating operation on the requests. The service controllers control request flows from the master devices adaptively depending on an operational environment change of the SOC.
    Type: Application
    Filed: March 13, 2013
    Publication date: July 24, 2014
    Inventors: BUB-CHUL JEONG, Jun-Hee Yoo, Sung-Hyun Lee
  • Publication number: 20140208070
    Abstract: System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a device. The SPI bridge additionally includes a first analog multiplexor control configured to route signals to a circuitry. The SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control.
    Type: Application
    Filed: December 14, 2011
    Publication date: July 24, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Daniel Milton Alley, Xiaomin Hu, Ye Xu
  • Publication number: 20140208072
    Abstract: A method is disclosed to manage a multi-processor system with one or more multiple-core coprocessors by intercepting coprocessor offload infrastructure application program interface (API) calls; scheduling user processes to run on one of the coprocessors; scheduling offloads within user processes to run on one of the coprocessors; and affinitizing offloads to predetermined cores within one of the coprocessors by selecting and allocating cores to an offload, and obtaining a thread-to-core mapping from a user.
    Type: Application
    Filed: April 6, 2013
    Publication date: July 24, 2014
    Applicant: NEC Laboratories America, Inc.
    Inventors: Srihari Cadambi, Kunal Rao, Srimat T. Chakradhar, Rajat Phull, Giuseppe Coviello, Murugan Sankaradass, Cheng-Hong Li
  • Patent number: 8776084
    Abstract: Executing an accelerator application program in a hybrid computing environment with a host computer having a host computer architecture; an accelerator having an accelerator architecture, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions; the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where executing an accelerator application program on an accelerator includes receiving, from a host application program on the host computer, operating information for an accelerator application program; designating a directory as a CWD for the accelerator application program, separate from any other CWDs of any other applications running on the accelerator; assigning, to the CWD, a name that is unique with respect to names of other CWDs of other applications in the computing environment; and starting the accelerator application program on the a
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, Gordon G. Stewart, Cornell G. Wright, Jr.
  • Publication number: 20140189303
    Abstract: A multistage module expansion system and multistage module communication method, applicable to a set-top box, are introduced. The system includes a master module, at least a preceding expansion module, and at least a succeeding expansion module. The master module generates and sends a control instruction to the preceding expansion module and the succeeding expansion module. The preceding expansion module and the succeeding expansion module each determine whether the control instruction is of a type executable by the preceding expansion module and the succeeding expansion module, respectively. If the determination is affirmative, the preceding expansion module creates and sends a preceding data packet to the master module, and the succeeding expansion module creates and sends a succeeding data packet to the preceding expansion module, such that the preceding expansion module sends the succeeding data packet to the master module.
    Type: Application
    Filed: February 6, 2013
    Publication date: July 3, 2014
    Applicant: ASKEY COMPUTER CORP.
    Inventor: TENG-KUEI CHANG
  • Patent number: 8690461
    Abstract: A system and method are provided for controlling a printing press including a plurality of print units and, optionally, a folder. Each print unit has one or more cylinders, a motor for driving the cylinders; an encoder for providing a cylinder position signal, a controller coupled to the encoder, the motor, a bus which interconnects each of the controllers and an input port for designating the controller as either master or slave. Any one of the controllers is selectively set as a master controller and the remaining controllers are set as slave controllers. The master controller generates a control signal based on a signal from the input port and outputs the control signal to the motor via the output port and to the slave controllers via the bus. Each of the slave controllers outputs a signal on the respective output port based on the received control signal.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 8, 2014
    Assignee: Goss International Americas, Inc.
    Inventor: John Sheridan Richards
  • Patent number: 8695010
    Abstract: Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Michael K. Gschwind, Naresh Nayar
  • Publication number: 20140095829
    Abstract: The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced.
    Type: Application
    Filed: May 31, 2011
    Publication date: April 3, 2014
    Applicant: ZTE CORPORATION
    Inventors: Zhiwei Mo, Ning Chen, Hao Wang
  • Patent number: 8667253
    Abstract: A processor of a data processing system executes a controlling thread of a program and detects occurrence of a particular asynchronous event during execution of the controlling thread of the program. In response to occurrence of the particular asynchronous event during execution of the controlling thread of the program, the processor initiates execution of an assist thread of the program such that the processor simultaneously executes the assist thread and controlling thread of the program.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Venkat R. Indukuru
  • Patent number: 8656355
    Abstract: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 18, 2014
    Assignee: CA, Inc.
    Inventors: Steven M. Oberlin, David W. McAllister
  • Patent number: 8645634
    Abstract: One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: February 4, 2014
    Assignee: NVIDIA Corporation
    Inventors: Michael Brian Cox, Nicholas Patrick Wilt, Richard Hough
  • Patent number: 8635620
    Abstract: A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alain Benayoun, Jean-Francois Le Pennec, Patrick Michel, Claude Pin
  • Patent number: 8607238
    Abstract: Aspects of the present invention reduce a lock wait time in a distributed processing environment. A plurality of wait-for dependencies between a first plurality of transactions and a second plurality of transactions in a distributed processing environment is identified. The first plurality of transactions waits for the second plurality of transactions to release a plurality of locks on a plurality of shared resources. An amount of time the first plurality of transactions will wait for the second plurality of transactions in the distributed processing environment is determined based on the plurality of wait-for dependencies between the first plurality of transactions and the second plurality of transactions. Historical transaction data related to the plurality of wait-for dependencies between the first plurality of transactions and the second plurality of transactions is analyzed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Abhinay Ravinder Nagpal, Sri Ramanathan, Sandeep Ramesh Patil, Matthew Bunkley Trevathan
  • Patent number: 8601238
    Abstract: An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: December 3, 2013
    Assignee: Sony Corporation
    Inventors: Kenji Yamane, Tsuyoshi Kano, Masahiro Takahashi
  • Patent number: 8578132
    Abstract: Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. Each accelerator includes a Power Processing Element (‘PPE’) and a plurality of Synergistic Processing Elements (‘SPEs’). Direct injection includes reserving, by each SPE, a slot in a shared memory region accessible by the host computer; loading, by each SPE into local memory of the SPE, a portion of data to be transferred to the host computer; executing, by each SPE in parallel, a data processing operation on the portion of the data loaded in local memory of each SPE; and writing, by each SPE, the processed data to the SPE's reserved slot in the shared memory region accessible by the host computer.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Michael A. Blocksome, Joseph D. Ratterman, Gary R. Ricard, Brian E. Smith
  • Patent number: 8578133
    Abstract: Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module. Each accelerator includes a Power Processing Element (‘PPE’) and a plurality of Synergistic Processing Elements (‘SPEs’). Direct injection includes reserving, by each SPE, a slot in a shared memory region accessible by the host computer; loading, by each SPE into local memory of the SPE, a portion of data to be transferred to the host computer; executing, by each SPE in parallel, a data processing operation on the portion of the data loaded in local memory of each SPE; and writing, by each SPE, the processed data to the SPE's reserved slot in the shared memory region accessible by the host computer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Michael A. Blocksome, Joseph D. Ratterman, Gary R. Ricard, Brian E. Smith
  • Patent number: 8564600
    Abstract: A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more slave hardware threads, e.g., collision detection hardware threads, to perform the actual collision detection. Because the slave hardware threads receive the level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric Oliver Mejdrich, Paul Emery Schardt, Robert Allen Shearer
  • Patent number: 8559544
    Abstract: Disclosed herein are lattice reduction systems and methods for a MIMO communication system. One such method includes providing a channel matrix corresponding to a channel in a MIMO communication system, preprocessing the channel matrix to form at least an upper triangular matrix, implementing a relaxed size reduction process, and implementing a basis update process. Implementing the relaxed size reduction process comprises choosing a first relaxed size reduction parameter for a first-off-diagonal element of the upper triangular matrix, choosing a second relaxed size reduction parameter, which is greater than the first relaxed size reduction parameter, for a second-off-diagonal element of the upper triangular matrix evaluating whether a first relaxed size reduction condition is satisfied for the first-off-diagonal element of the upper triangular matrix, and evaluating whether a second relaxed size reduction condition is satisfied for the second-off-diagonal element of the upper triangular matrix.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 15, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: David Verl Anderson, Brian Joseph Gestner, Wei Zhang, Xiaoli Ma
  • Patent number: 8561073
    Abstract: Embodiments of the invention intelligently associate processes with core processors in a multi-core processor. The core processors are asymmetrical in that the core processors support different features or provide different resources. The features or resources are published by the core processors or otherwise identified (e.g., via a query). Responsive to a request to execute an instruction associated with a thread, one of the core processors is selected based on the resource or feature supporting execution of the instruction. The thread is assigned to the selected core processor such that the selected core processor executes the instruction and subsequent instructions from the assigned thread. In some embodiments, the resource or feature is emulated until an activity limit is reached upon which the thread assignment occurs.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: October 15, 2013
    Assignee: Microsoft Corporation
    Inventors: Yadhu Nandh Gopalan, John Mark Miller, Bor-Ming Hsieh
  • Patent number: 8533716
    Abstract: A method and apparatus for resource management in a multicore processor is disclosed. A system management controller (130) provides omnipresent scheduling, synchronization, load balancing, and power and memory management services to each processing resource (150) within in a multicore processor (10), via a plurality of system management clients (120) implemented in hardware or software. The controller (130) allocates the tasks executing in each processing resource (150) by means of interrupt control signals, which interact directly with the system management clients (120), enabling processing resources (150) to autonomously create, execute and distribute tasks around a parallel system architecture whilst monitoring and policing the use of shared system resources (140).
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 10, 2013
    Assignees: Synopsys, Inc., Fujitsu Semiconductor Limited
    Inventor: Mark David Lippett
  • Publication number: 20130185521
    Abstract: A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag.
    Type: Application
    Filed: December 18, 2012
    Publication date: July 18, 2013
    Applicant: Fujitsu Limited
    Inventor: Fujitsu Limited
  • Patent number: 8468534
    Abstract: Techniques are provided for dynamically re-ordering operation requests that have previously been submitted to a queue management unit. After the queue management unit has placed multiple requests in a queue to be executed in an order that is based on priorities that were assigned to the operations, the entity that requested the operations (the “requester”) sends one or more priority-change messages. The one or more priority-change messages include requests to perform operations that have already been queued. For at least one of the operations, the priority assigned to the operation in the subsequent request is different from the priority that was assigned to the same operation when that operation was initially queued for execution. Based on the change in priority, the operation whose priority has change is placed at a different location in the queue, relative to the other operations in the queue that were requested by the same requester.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: June 18, 2013
    Assignee: Apple Inc.
    Inventor: Brian R. Tunning
  • Patent number: 8453152
    Abstract: A scheduler receives at least one flexible reservation request for scheduling in a computing environment comprising consumable resources. The flexible reservation request specifies a duration and at least one required resource. The consumable resources comprise at least one machine resource and at least one floating resource. The scheduler creates a flexible job for the at least one flexible reservation request and places the flexible job in a prioritized job queue for scheduling, wherein the flexible job is prioritizes relative to at least one regular job in the prioritized job queue. The scheduler adds a reservation set to a waiting state for the at least one flexible reservation request.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Alexander Druyan, Wei Li, Kailash N. Marthi, Yun T. Xiang, Linda C. Cham