Abstract: A flexible TFT backplane includes, a flexible substrate, a first set of address line contacts associated with the substrate, and a second set of address line contacts associated with the substrate. The first set of address line contacts and the second set of address line contacts are located at opposite sides of the substrate from each other, defining a vertical direction. A first set of address lines designed to run in one of the vertical direction and a diagonal or non-vertical direction with respect to the defined vertical direction, with the first set of address lines connected to the first set of address line contacts. Also provided is a second set of address lines designed to run in one of a diagonal or non-vertical direction with respect to the defined vertical direction, and a combination of diagonal and horizontal directions with respect to the vertical direction, with the second set of address lines connected to the second set of address line contacts.

Abstract: Techniques and mechanisms for providing test functionality at an integrated circuit (IC) chip. In an embodiment, the IC chip includes protocol stacks variously coupled each between a switch fabric and other switch circuitry which is configurable to selectively implement, at least in part, either of an operational mode and a test mode. The operational mode facilitates communication, via the switch circuitry, between a first protocol stack and physical layer circuitry. The test mode instead enables communication, between the first protocol stack and a second protocol stack, of test packet information which is based on a test packet received from the switch fabric. In another embodiment, the protocol stacks support communication according to a Thunderbolt™ protocol.

Abstract: Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware accelerator, and a controller programmed to monitor the instruction queue to detect a first type of instructions stored in the instruction queue, reprogram the programmable hardware accelerator to execute the first type of instructions, and transmit the first type of instructions to the programmable hardware accelerator to be executed.

Abstract: A pin removal mode signal generation circuit includes: a set signal generation unit configured to activate a set signal when an activated test mode signal pulse is generated by a mode register set and an activated flag signal pulse is applied, and a pin removal mode signal generation unit configured to activate a pin removal mode signal when the set signal is activated, and deactivate the pin removal mode signal when a reset signal is activated.

Abstract: A high volume manufacturing (HVM) and circuit marginality validation (CMV) test for an integrated circuit (IC) is disclosed. The IC comprises a port binding and bubble logic in the front end to provide flexibility in binding a port to the uop and to create empty spaces (bubbles) in the uop flow. The out-of-order (OOO) cluster of the IC comprises reservation disable logic to control the flow sequence of the uops and stop schedule logic to temporarily stop dispatching the uops from the OOO cluster to the execution (EXE) cluster. The EXE cluster of the IC comprises signal event uops to generate fault information and fused uJump uops to specify combination of branch prediction, direction, and resolution in any portion of the test. Such features provide a tester the flexibility to perform HVM and CMV testing of the OOO and EXE clusters of the IC.

Abstract: In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Abstract: Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.

Abstract: In an accounting apparatus, a conflict determination unit determines whether or not the accounting mode is in a conflict state where a process is executing in another logical CPU and stores the determination result in an accounting information storage unit, when a process of the user starts to be executed in a logical CPU of an SMT processor. And a CPU use time acquisition unit collects the CPU use time of the process in the conflict state or the non-conflict state distinctively and stores it in an accounting information storage unit. Thereafter, a CPU use time conversion unit converts the CPU use time in the conflict state, with a predetermined weighting, based on the CPU use time in the conflict state and the non-conflict state, after the end of executing the process, and an accounting calculation unit calculates the accounting amount for the process from an effective use time.

Abstract: A network tap port aggregator for use in monitoring a network is provided. The network tap port aggregator includes a first device interface terminal for receiving a first network feed. The network tap port aggregator also includes a second device interface terminal for receiving a second network feed. The network tap port aggregator further includes a circuitry coupled with the first device interface terminal and with the second device interface terminal, the circuitry configured to monitor the first network feed and the second network feed and to aggregate the first network feed and the second network feed into an aggregated network feed. The network tap port aggregator yet also includes a first monitor interface terminal coupled to the circuitry for providing the aggregated network feed to a first network monitor that is external to the network tap port aggregator.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

Abstract: The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the present invention, a new higher bit address latching signal is added in order to latch the higher bit address so that an original lower bit address latching signal and the higher bit address latching signal can respectively latch the lower bit address and the higher bit address.

Abstract: A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode. Depending on whether or not signal(s) satisfying predetermined criteria are applied to at least one of the control I/O pins, the controller will cause the circuit to enter one of two or more post-initial operation modes. Accordingly, by initializing the controller, and by controlling a signal on the control I/O pin(s), the operating mode of the circuit may be controlled. In one embodiment, a given control pin might be configurable to be both analog and digital, depending on the circuit's operation mode.

Abstract: Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.

Abstract: The invention concerns electronics devices like X-ray detectors with an array of pixels (303) that can be combined (binned) into binning blocks of m×n pixels. According to the invention the available read-out lines (325) of the device are all connected to different binning blocks in each read-out step, such that up to m binning blocks are addressed simultaneously in the verticle direction when m×n binning is used. In this case, the output signals from the m vertically arranged blocks are distributed over the m read-out columns present in the m×n blocks. In a preferred embodiment, row address lines (361) together with diagonal address lines (371) and a simple activation logic (372) guarantee the required versatile addressing of the pixels.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: A single-IC subsystem controller for controlling electronic devices and subsystems within computer systems and other large electronic systems. The single-IC subsystem controller includes a micro-controller, a complex programmable logic device, an EEPROM, an SRAM, and various electronic bus interfaces and additional signal long interfaces for interfacing the single-IC subsystem controller device to electronic devices and electrical components. The single-IC subsystem controller allows for flexible partitioning of control functionality between hardware circuits programmed into the CPLD and software routines executed by the micro-controller.

Abstract: A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.

Abstract: In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the first and second bit line precharge circuits. The first and second bit line precharge circuits are each configured to precharge the first bit line and the second bit line. The control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and is configured to activate both the first and second bit line precharge circuits responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.

Abstract: The dynamic switching of a bi-endian processor between endian modes is described. A device having the bi-endian processor may also have an endian select circuit. The endian select circuit may receive a signal from the processor that determines what the endian-ness should be after the processor resets. Special instruction code may be executed by the processor in both little and big endian modes. The special instruction code may, for instance, cause a processor in a first endian mode to output a signal and reset, while the same instruction code may cause a processor in a second endian mode to neither output the signal nor reset. Instead, the processor in the second endian mode may jump to a new instruction address and proceed with normal processing.

Abstract: An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: The network interface device has multiple blocks having internal connections, and has an external interface. The network interface device is configurable to reroute one or more of the internal connections onto the external interface to allow testing of the blocks of the device. The external interface may also be coupled so as to pass data between the network interface device and higher levels in a network protocol stack. In an exemplary embodiment a network interface device has a media access controller (MAC) and a physical layer device (PHY). An internal media independent interface (MII) between the MAC and the PHY may be selectively rerouted to an external MII for independently testing operation of either the MAC or the PHY.

Abstract: A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.

Abstract: A microcomputer is provided with a data-transfer unit such as a DMA (direct memory access) controller for controlling a transfer of data through an external bus. Used in an access to an external device controlled by the data-transfer unit, a bus-interface means of the microcomputer includes a buffer-register means which can be specified as either a source location or a destination location of a data transfer. Thus, an internal-bus master such as a CPU employed in the microcomputer is capable of reading out information such as a packet command from the buffer-register means at a high speed through an internal bus without using the external bus and, hence, capable of carrying out an operation reflecting a transfer control condition specified by the packet command.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: Provided are an integrated circuit and a method thereof, in which different types of signals can be applied to an internal circuit via one pin. The integrated circuit device includes a distribution unit, a level fixing unit, and an activation unit. The distribution unit receives and outputs a first input signal input via the first input pin, and receives and outputs a second input signal input via the first input pin in response to a control signal. The level fixing unit receives the first input signal from the distribution unit and applies a signal having the same voltage level as the first input signal to a first internal circuit in response to the control signal. The activation unit receives the second input signal input via the second input pin and then applies the second input signal to a second internal circuit or applies the second input signal output from the distribution unit to the second internal circuit in response to the control signal.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: The present invention relates to a method for providing a master-slave hot-swapping apparatus and mechanism for use with an ATA bus. A bus controller and a bus separator are employed for isolating the hot-swapping apparatus and the host system, and a power supply switch is used.

Abstract: A system for programming a periphery flash ROM is provided. The system in-cludes a host computer, an IDE interface, a flash controller, a flash ROM, and a micro-processor. The flash controller is coupled to the host computer through the IDE interface. The flash ROM and the microprocessor are also coupled to the flash controller. When the system enters a flash ROM programming mode, task files used between the IDE interface and the host computer are redefined by the host computer and is interpreted by the flash controller so that a firmware code from the host computer is written into the flash ROM through the flash controller. After the flash ROM is completely programmed, the task files return to their original definition. The microprocessor is required to disable the access to the flash ROM during the flash ROM programming mode.

Abstract: A digital signal processing device applicable to a signal processing system using a CPU is mainly configured by an external memory and a digital signal processor (i.e., DSP), which are connected together using a data bus and an address bus. The external memory stores multiplier data and coefficient data as well as basic instructions. In the DSP, an ALU calculates addresses for accessing the external memory via the address bus. A bus control unit identifies the multiplier data, coefficient data and basic instructions respectively, which are read from the external memory. The DSP performs calculations containing multiplication using the multiplier data and coefficient data. The DSP is controlled in operations in response to a CPU mode and a DSP mode, one of which is selected by decoding the basic instruction(s) identified by the bus control unit. At the CPU mode, the basic instructions of sixteen bits are subjected to coding to produce high-speed instructions of thirty-two bits for controlling the DSP.

Abstract: A method and apparatus for interfacing a weighing scale and one or more peripheral devices which includes a single intelligent interface cable assembly connected between a weighing scale and a plurality of peripheral devices, the IICA detects the peripheral device protocol by receiving a logic signal indicating which protocol is in operation, if necessary, the IICA then switches the signal protocol of the weighing scale to correspond with the signal protocol of the detected peripheral device protocol. Simultaneous, tripping of a mailing machine to print postage amounts may occur.

Abstract: The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Abstract: In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.

Abstract: A method and apparatus for allowing developers to develop software for their product. The method includes providing a first mode signal to a processor to operate in a development mode. The method also includes executing instructions stored in a first region of the memory in response to the first mode signal, providing data to the processor, and writing the data into a second region of the memory.

Abstract: A method and system for performing a task in an intrinsically safe environment using an intrinsically safe, integrated module located on the safe side to convey signals to and from a field device on the hazardous side. The integrated module is configurable in order to suit the electrical characteristics and requirements of the field device. Preferably, the integrated module is software configurable, in that the module can be configured by a command signal without using switches. Furthermore, the integrated module is configurable in order to control the field device in performing the task. The integrated module includes an input/output module which is electrically connected to the field device through a Zener barrier or a galvanic isolation barrier, and a power supply to power the field device through a Zener barrier.

Abstract: A circuit for efficiently time-sharing the output and input configuration of a microprocessor I/O pin. The circuit includes a microprocessor having at least one I/O pin which can be selectively reconfigured for either output or input functions, a pull-up resistor, a dropping resistor and an output device. The pull-up resistor, dropping resistor and output device each have a common electrical connection at a terminal connected to the selected I/O pin. The pull-up resistor also has a terminal connected to the regulated power supply (Vcc) of the circuit. An input device or configuration switch, which is selectable between a first state and a second state, has one terminal connected to the dropping resistor and a second terminal connected to a point of the circuit at ground potential. The selected I/O pin is normally configured as an output pin for controlling the output device.

Abstract: A plurality of parallel execution units are selectively powered from a plurality of power sources, the power to each execution unit being selected based upon expected time to completion of processing within the execution unit. Maximum power is gated to execution units executing complex instructions, or time-critical instructions. Less than maximum power is gated to execution units executing simple instructions, or instructions which are not time-critical, or in response to pipeline hazards or stalls. When less than maximum power is gated to an execution unit, a step up circuit may be employed to raise the output of that execution unit to maximum power.

Abstract: A microcomputer is realized having a built-in SIO which is able to correspond to a LAN which requires strict timing control and also correspond to a high speed serial communication. A counter supplies.a clock signal for data shift to an SIO register which performs serial-parallel conversion and vice versa. Two D flip-flop circuits detect the rise of an SRDY signal, an input signal expressing the start of transmission, and give the counter a reset signal.

Abstract: For rewriting data, which includes programs, stored in a programmable ROM, a receiving-side information processing apparatus first transfers a reception program included in the data stored in the ROM to a RAM. Control jumps to the reception program stored in the RAM, whereby reception is executed. Received data is written in the ROM according to the program stored in the RAM. The programs stored in the ROM can thus be rewritten.

Abstract: A data processing system and method are described for remotely controlling execution of a processor utilizing the processor's built-in test access port for debugging the execution of the processor. The client computer system is coupled to a server computer system utilizing a network. The server computer system transmits a signal to said client computer system to control execution of the processor utilizing the test access port. The signal identifies one of a plurality of processor actions. In response to a receipt of the signal, the processor executes the one of the plurality of processor actions such that the server computer system remotely debugs the execution of the processor utilizing the built-in test access port, wherein additional debug hardware is not utilized.

Abstract: A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit outputs the same value as that of the internal signal from each of external terminals. In the case where the internal signal does not need to be monitored, e.g., in the same manner as ordinary user's use, the output control circuit outputs an invariable value from each of the external terminals. Thus, in the case where the internal signal does not need to be monitored, the invariable value is outputted. Consequently, power consumption can be suppressed.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract: In the CIS installation area of a PC card, the A region contains the basic attribute information of the card, the B region contains data of CIS1 for a modem, and the C region contains CIS2 for an ATA memory. The PC card is provided with a selection signal input means which selectively designates the CIS. A selection signal discriminator receives a signal from the selection signal input means and determines the selective designation of the CIS. When CIS1 and CIS2 are selectively designated together, a CIS switch setting element sets the start of the CIS read-in by a personal computer to the leading address of CIS1, and when CIS2 only is selectively designated, it switchably sets the start of the CIS read-in by the personal computer to the leading address of CIS2.

Abstract: A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.