Microprocessor Or Multichip Or Multimodule Processor Having Sequential Program Control Patents (Class 712/32)
  • Patent number: 10545960
    Abstract: There is provided a system and method for set overlap searching of a data lake. The method includes: receiving input tables; generating an inverted index from the input tables; receiving a query set of data values to be searched; receiving a requested set quantity; while a comparison condition is true, the comparison condition based on at least a size of the query set, iteratively performing: determining whether a first net cost of reading a candidate set is greater than a second net cost of reading an unread one of the posting lists; where its true, adding the unread one of the posting lists to the candidate set; and where its negative, determining whether the overlap between the query set and the candidate set is greater than the lowest ranked candidate set in a heap, and adding the candidate set to the heap.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: January 28, 2020
    Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventor: Er Kang Zhu
  • Patent number: 10440377
    Abstract: In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Ram K. Krishnamurthy
  • Patent number: 10379906
    Abstract: A method and apparatus for system call command batch processing are provided. The method enable system call commands of a same type to be processed in a same CPU core according to a sequence of entering a kernel, thereby ensuring that returned results of the system call commands are sequential.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 13, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Kai Qi, Wei Wang, Yi Cai
  • Patent number: 10216499
    Abstract: Method, program and system for code optimization. A sign assignment instruction with input and output operands identical in size, which assigns a value of zero to a packed decimal data value that has a value of negative zero, is detected in source code or an executable program. A first instruction that checks for a possibility that the input operand is negative zero is generated based on that detection. The first instruction skips the sign assignment instruction when the input and output operand have identical addresses when and there is no possibility that the input value is negative zero; and executes a copy instruction copying the input value in the input operand to the output operand when the input and output operands have different addresses and are not overlapping. The first instruction is inserted into one of the source code or the binary executable program that is output.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventor: Motohiro Kawahito
  • Patent number: 10133672
    Abstract: Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. The pointer chasing command indicates the number of interdependent memory accesses and information needed for the identified interdependent memory accesses. An address computing unit associated with the memory node determines the relevant memory address for an interdependent memory access absent further interaction with the issuing node or without having to return to the issuing node.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 20, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paula Aguilera Diez, Amin Farmahini-Farahani, Nuwan Jayasena
  • Patent number: 10073707
    Abstract: An improved system and method are disclosed for configuring a platform instance at runtime using predefined configuration information and contexts that contain at least a portion of the predefined configuration information and also contain dynamically generated information that is not available until the platform instance is started. A core server of the platform instance is started and configured, contexts are created, and services and blocks are started and configured using the contexts.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: September 11, 2018
    Assignee: n.io Innovations, LLC
    Inventors: Douglas A. Standley, Matthew R. Dodge, Randall E. Bye
  • Patent number: 9984434
    Abstract: The present disclosure describes techniques for removing unnecessary processing stages from a graphics processing pipeline based on the format of data passed between the stages. Starting with a stage at a middle point in a pipeline, formats of data that are input to and output from the middle stage may be compared to each other. If the formats match, the middle stage may be removed from the pipeline. Thereafter, the format of data input to a pair of middle stages of the pipeline and output from the pipeline may be compared and, if they match, the middle pair may be deleted. This process may repeat until a middle pair is found where no match occurs between the input and output format. The remaining stages of the pipeline may be retained. In cases where a pipeline is not symmetrical, the formats of data at each node may be compared to each other.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 29, 2018
    Assignee: APPLE INC.
    Inventors: Aaron M. Ballow, Kenneth I. Greenebaum
  • Patent number: 9953693
    Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventor: Kuljit S Bains
  • Patent number: 9946482
    Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 17, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Kevin Kilzer, Joseph Julicher, Jacobus Albertus Van Eeden
  • Patent number: 9910717
    Abstract: A synchronization method in a computer system with multiple cores, wherein a group of threads executes in parallel on a plurality of cores, the group of threads being synchronized using barrier synchronization in which each thread in the group waits for all the others at a barrier before progressing; the group of threads executes until a first thread reaches the barrier; the first thread enters a polling state, repeatedly checking for a release condition indicating the end of the barrier; subsequent threads to reach the barrier are moved to the core on which the first thread is executing; and other cores are powered down as the number of moved threads increases; and wherein when the first thread detects the release condition, the powered down cores are powered up and are available for use by the threads.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 6, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Nicholas Wilson, James Alastair Southern
  • Patent number: 9898330
    Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Atul Khare, Leena Puthiyedath, Asit Mallick, Jim Coke, Michael Mishaeli, Gilbert Neiger, Vivekananthan Sanjeepan, Jason Brandt
  • Patent number: 9875348
    Abstract: A device configured to utilize training techniques and to gather information while training and administering certification examinations. Certification examinations may require security to ensure users taking the certification examination are actually the user designated on any issued certificate. When certification examinations are administered remotely from a proctor, different techniques to identify the user and attempt to guarantee that the user is not obtaining outside aid during the examination may be performed. Tests may be administered off-line while not connected to any network and locally cached data may be collected on the testing device for later transmittal to a back-end server for further analysis. In addition to remote proctoring/invigilating capabilities, the disclosed techniques and device may collect metrics that have a number of uses. For example, skill level of different geographical regions may be calculated to assist companies in determining a location for a new factory (e.g.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 23, 2018
    Assignee: Green Grade Solutions Ltd.
    Inventor: Sharon Sadeh
  • Patent number: 9823957
    Abstract: A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: November 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsushi Okamoto
  • Patent number: 9780789
    Abstract: An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 3, 2017
    Assignee: Altera Corporation
    Inventors: Sean R. Atsatt, Robert Landon Pelt
  • Patent number: 9772674
    Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 26, 2017
    Assignee: Intel Corporation
    Inventors: Nadav Bonen, Ron Gabor, Zeev Sperber, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes, Naveen Kumar, Shantanu Gupta
  • Patent number: 9740607
    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second sense line and configured to store a second element. An example apparatus might also include a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kyle B. Wheeler
  • Patent number: 9652210
    Abstract: A provisioning system to automatically determine the appropriate components to install or make available for installation on a target computer system. The provisioning system ensures the provisioning of software components that are appropriate to each target computer system without requiring user input. The provisioning system can identify support for 64-bit software components. The provisioning system checks a field in the processor to determine longword, that is 64-bit support, or checks an entry in a file maintained by an operating system to determine 64 bit support. If 64-bit support is not detected then a 32-bit component is installed to ensure that the target computer system is capable of executing the software component.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: May 16, 2017
    Assignee: Red Hat, Inc.
    Inventors: Miroslav Suchy, Milan Zazrivec
  • Patent number: 9530328
    Abstract: An intelligent teaching and tutoring test method is provided with a remote learning online test mode, a remote learning test paper test mode, a classroom teaching online test mode, and a classroom teaching test paper test mode. Based on the diversified data input methods and intelligent data analyzing process offered by an intelligent teaching and tutoring test system, the invention is a proprietary teaching and tutoring test method for different learners according to their differentiated individual learning situations so as to substantially enhance the learning efficiency of the learners.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: December 27, 2016
    Inventors: Chien Cheng Liu, Kuan Chen Wang
  • Patent number: 9529980
    Abstract: In a computer-implemented method for deduplicating a plurality of instances of end user licensing agreements (EULAs), an end user licensing agreement (EULA) from a software bundle is accessed. Only a single instance of the EULA is displayed such that there is a deduplication of a plurality of instances of EULAs.
    Type: Grant
    Filed: June 28, 2014
    Date of Patent: December 27, 2016
    Assignee: VMware, Inc.
    Inventor: John Powell
  • Patent number: 9519583
    Abstract: The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: George L. Chiu, Alexandre E. Eichenberger, John K. P. O'Brien
  • Patent number: 9519486
    Abstract: A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 13, 2016
    Assignee: XILINX, INC.
    Inventors: Michaela Blott, Thomas B. English, Kornelis A. Vissers
  • Patent number: 9517402
    Abstract: Various exemplary embodiments of the present invention uniquely identify players in a video game based on how a player interacts with a game and/or other players to generate a unique player identifier or player fingerprint. The player may also be categorized by player data or category to identify certain behavior (e.g., fraud). This unique information may be used to accurately authenticate the player to address fraud and other situations involving an unauthorized player. By verifying the identity of the player, an embodiment of the present invention may detect, minimize and/or prevent fraud and/or other situations where someone else is improperly playing or accessing another player's account. Authentication of player identity can also be used to detect cheating, improper sale of accounts, and other undesirable player behavior. Player fingerprint information may also be used to tailor information to the player (e.g., suggestions for other games, advertisements, instructional information, etc.).
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: December 13, 2016
    Assignee: EPIC GAMES, INC.
    Inventor: Daniel Vogel
  • Patent number: 9511729
    Abstract: The present invention includes systems and methods for dynamic allocation of computing resources. Computing resources on an aircraft are divided amongst several avionics applications that are responsible for controlling sub-systems on the aircraft (e.g. the navigation system). A resource manager assigns computing resources (e.g. processor cycles) to individual applications based on the present condition of the aircraft and then instructs the throttling mechanisms to allocate the computing resources among the applications. The resource manager determines the aircraft condition by correlating inputs from the aircraft to a set of rules stored in a condition table. The resource manager then determines the computing resource allocation by correlating the aircraft condition to a set of resource allocations stored in an allocation table.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: December 6, 2016
    Assignee: Rockwell Collins, Inc.
    Inventors: Geoffrey J. Barnes, Richard G. Moore
  • Patent number: 9471326
    Abstract: A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping of physical registers to the set of architectural registers using the stored information.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: October 18, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Achenbach, Francesco Spadini
  • Patent number: 9465767
    Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 11, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Matthew D Pierson, Daniel B Wu, Timothy D Anderson
  • Patent number: 9417801
    Abstract: Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware interface, and a virtual GPIO controller. The driver receives a GPIO command from an operating system of the computing device. The GPIO command specifies an operation to be performed by a GPIO pin. The driver sends the GPIO command to the firmware interface. In response to the firmware interface receiving the command, the virtual GPIO controller emulates a virtual GPIO pin to implement the GPIO command. The firmware interface may trigger an interrupt that can be received by the operating system. The virtual GPIO controller may emulate the virtual GPIO pin using firmware-reserved backing memory, an embedded controller, or an interface to a peripheral device of the computing device. The firmware interface may be an ACPI control method. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Nicholas J. Adams, Robert E. Gough, Sai Prasad Paithara Balagangadhara, Pronay Dutta
  • Patent number: 9405349
    Abstract: A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: August 2, 2016
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Woong Seo, Yeon-Gon Cho, Soo-Jung Ryu, Seok-Woo Song, John Dongjun Kim, Min-Seok Lee
  • Patent number: 9324072
    Abstract: A memory is organized into blocks. In a bit-flipping operation, a memory block is read, the read bit data values are inverted, and the inverted data is written back to the memory block. Inverted memory blocks are tracked by setting a flag bit in the memory block, or by storing a pointer to a memory block. In a read operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the read data values are reverted before being returned. In a write operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the write data values are inverted before being written. Inversion of data values and tracking of inverted memory blocks may be performed by a specialized memory controller or by a processor executing secure memory code. Data remanence is thus prevented in the memory.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 26, 2016
    Assignee: IXYS Intl Limited
    Inventors: David A. Roberts, Russell B. Lloyd, Joshua J. Nekl
  • Patent number: 9317359
    Abstract: A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 19, 2016
    Assignee: Artesyn Embedded Computing, Inc.
    Inventors: Pasi Jukka Petteri Vaananen, Martin Peter John Cornes
  • Patent number: 9298673
    Abstract: The present disclosure provides an electronic device and an information processing method. The electronic device comprises: a processor which comprises N processing units to process data and perform data input and output; a data processing interface coupled to Q processing units among the N processing units, which compresses raw data received from the Q processing units to obtain compressed data; and a memory coupled to the data processing interface, which receives and stores the compressed data, where N?1 and 1?Q?N.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 29, 2016
    Assignee: Lenovo (Beijing) Limited
    Inventors: Huaping Liu, Wei Xie
  • Patent number: 9292426
    Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 22, 2016
    Assignee: INTEL CORPORATION
    Inventor: Kuljit S. Bains
  • Patent number: 9239643
    Abstract: An embodiment of a method of recognizing finger detection data in a detection data map produced by a touch screen includes converting the data from the x, y, z space into a three-descriptor space including: a first coordinate representative of the number of intensity peaks in the map, a second coordinate representative of the number of nodes (i.e., pixels) absorbed under one or more of the intensity peaks. A third coordinate may be selected as the angular coefficient or slope of a piecewise-linear approximating function passing through points having the numbers of nodes absorbed under the intensity peaks ordered in decreasing order over said intensity peaks, which permits singling out finger data with respect to non-finger data over the whole of the touch screen.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 19, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nunziata Ivana Guarneri, Alessandro Capra, Sebastiano Battiato, Giovanni Maria Farinella, Francesco Cristaldi
  • Patent number: 9141361
    Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.
    Type: Grant
    Filed: September 30, 2012
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
  • Patent number: 9105244
    Abstract: A panel control apparatus and an operating method thereof are provided, and which includes a scalar and a timing controller. The scalar transmits a present display data for composing a display frame, and determines whether to generate a refresh request signal according to a state of the display frame. The timing controller includes a memory, an over driving unit and a panel self refresh unit. When the refresh request signal is not generated, the over driving unit converts the present display data into an over driving display data according to a previous compression data from the memory. When the refresh request signal is generated, the panel self refresh unit compresses the present display data into a refresh display data, and stores the refresh display data into the memory.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 11, 2015
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Tung-Ying Wu, Chun-Te Ho
  • Patent number: 9098244
    Abstract: A non-transitory, computer-readable storage medium comprising instructions stored thereon. When executed by at least one processor, the instructions may be configured to cause a computer system to at least monitor for a post-tactile keyboard input within a post-tactile input threshold time after receiving a tactile input device input, ignore the tactile input device input if the post-tactile keyboard input is received within the post-tactile input threshold time after receiving the tactile input device input, and recognize the tactile input device input if the post-tactile keyboard input is not received within the post-tactile input threshold time after receiving the tactile input device input.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: August 4, 2015
    Assignee: Google Inc.
    Inventor: James Roskind
  • Patent number: 9087381
    Abstract: A method and apparatus for extracting surface representation from images and video data for segmenting image plane according to the surface connectivity, and identifying areas of images taken by a moving camera according to the object surfaces wherefrom the areas of images are taken, are disclosed. The invention discloses a method and apparatus comprising a plurality of processing modules for extracting from images in a video sequence the occluding contours delineating images into regions in accordance with the spatial connectivity of the correspondent visible surfaces, and diffeomorphism relations between areas of images taken from different perspective centers for identifying image areas of different frames as of the surface of same object, and specifying the fold contours of the surfaces that owns the contour, and thus producing the surface representations from video images taken from persistent objects by a moving camera.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 21, 2015
    Inventors: Thomas Tsao, Xuemei Cheng
  • Patent number: 9083725
    Abstract: The embodiments herein develop a system for providing hierarchical cache for big data processing. The system comprises a caching layer, a plurality of actors in communication with the caching layer, a machine hosting the plurality of actors, a plurality of replication channels in communication with the plurality of actors, a predefined ring structure. The caching layer is a chain of memory and storage capacity elements, configured to store a data from the input stream. The plurality of actors is configured to replicate the input data stream and forward the replicated data to the caching layer. The replication channels are configured to forward the replicated data from a particular actor to another actor. The predefined ring structure maps the input data to the replica actors.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 14, 2015
    Inventors: Fred Korangy, Hamed Ghasemzadeh, Mohsen Arjmandi, Reza Azmi
  • Patent number: 9053812
    Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: June 9, 2015
    Assignee: INTEL CORPORATION
    Inventor: Kuljit S. Bains
  • Patent number: 9026239
    Abstract: A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Feng Tsai, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
  • Patent number: 9015504
    Abstract: A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power management configuration; and (3) a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads, wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Thang Tran
  • Patent number: 8996895
    Abstract: A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Alon Naveh, Eliezer Weissmann, Ofer Nathan, Nadav Shulman
  • Patent number: 8996278
    Abstract: In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the internal combustion engine, the control unit includes a selecting unit, that selects at least one core used in the computation from among the plurality of cores, a computing unit that distributes the tasks to the at least one core selected by the selecting unit to perform computation, and an acquisition unit that acquires an engine, rotational speed of the internal combustion engine, and, when the engine rotational speed acquired by the acquisition unit is higher than or equal to a predetermined threshold, the selecting unit increases the number of the cores selected as compared with when the acquired engine rotational speed is lower than the predetermined threshold.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 31, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hayato Nakada, Akira Ohata, Keisuke Osakabe
  • Patent number: 8972995
    Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: March 3, 2015
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Ruben Khazhakyan, Harutyan Aslanyan, Drew E. Wingard, Chien-Chun Chou
  • Patent number: 8930635
    Abstract: Processing within a multiprocessor computer system is facilitated by: setting, in association with invalidate page table entry processing, a storage key at a matching location in central storage of a multiprocessor computer system to a predefined value; and subsequently executing a request to update the storage key to a new storage key, the subsequently executing including determining whether the predefined value is an allowed stale value, and if so, replacing in central storage the storage key of predefined value with the new storage key without requiring purging or updating of the storage key in any local processor cache of the multiprocessor computer system, thus minimizing interprocessor communication pursuant to processing of the request to update the storage key to the new storage key.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventor: Gary A. Woffinden
  • Patent number: 8929376
    Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Netronome Systems, Incorporated
    Inventors: Gavin J. Stark, Steven W. Zagorianakos, Ron L. Swartzentruber, Richard P. Bouley
  • Patent number: 8930676
    Abstract: A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: January 6, 2015
    Assignee: Via Technologies, Inc.
    Inventors: G. Glenn Henry, Darius D. Gaskins
  • Publication number: 20150006850
    Abstract: Provided is a processor with a heterogeneous clustered architecture. The processor comprises a first cluster comprising a first functional unit configured to process a first type of instruction, and a register whose I/O ports are connected to I/O ports of the functional unit; and a second cluster comprising a second functional unit configured to process the first type of instruction and second type of instruction, and a second register whose I/O ports are connected to I/O ports of the second functional unit.
    Type: Application
    Filed: June 25, 2014
    Publication date: January 1, 2015
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Ki-Seok KWON, Min-Wook AHN, Dong-Kwan SUH, Suk-Jin KIM
  • Patent number: 8886917
    Abstract: A multi-core processor includes at least one first core and at least one second core. The first core is optimized to run applications, and the second core is optimized to meet the computing demands of operating-system-like code. The first core and the second core execute the same instruction set.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: November 11, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathan L. Binkert, Jeffrey C. Mogul, Jayaram Mudlgonda, Parthasarathy Ranganathan
  • Patent number: 8880485
    Abstract: According to some embodiments, a data source is accessed from which data will be retrieved via a plurality of processing threads. The data source may have, for example, a plurality of records with each record being associated with a plurality of identifiers. Each of the plurality of identifiers may be dynamically evaluated as a potential range identifier, and the evaluation may be based at least in part on a number of distinct values present within each identifier. One of the potential range identifiers may be selected as a selected range identifier, and the plurality of records may be divided into ranges defined using the selected range identifier.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 4, 2014
    Assignee: SAP SE
    Inventors: Guy Rozenwald, Uri Haham, Tal Kellner
  • Patent number: RE45487
    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton