Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. Based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated.

Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

Abstract: A method for executing new instructions includes receiving an instruction, and determining whether the received instruction is a new instruction according to an operation code of the received instruction. When the received instruction is a new instruction, the basic decoding information of the received instruction is stored in a private register. And, the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information includes the operation code.

Abstract: A method for executing new instructions includes receiving an instruction, and determining whether the received instruction is a new instruction according to an operation code of the received instruction. When the received instruction is a new instruction, the basic decoding information of the received instruction is stored in a private register. And, the system for executing the new instructions enters a system management mode, and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode; wherein the basic decoding information includes the operation code.

Abstract: The electronic device may comprise: a display; a processor electrically connected to the display and including a plurality of cores; and a memory electrically connected to the processor, wherein the memory is configured to store a plurality of application programs, and stores instructions which, when executed, allow the processor to perform parallel compilation of two or more application programs among the plurality of application programs by using two or more cores among the plurality of cores during a booting operation, and when at least one application program which has failed to be compiled is sensed, perform a rebooting operation, and perform series compilation of the at least one application program which has failed to be compiled, by using one core among the plurality of cores during the rebooting operation. Other embodiments may also be possible.

Abstract: In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.

Abstract: A multi-lender loan management system is provided herein. The multi-lender management system includes an external network gateway, an internal network gateway, a messaging service, a plurality of Application Programming Interface (API) modules coupled between the external network gateway and the internal network gateway, and a plurality of micro services coupled to the internal network gateway and configured to communicate with each other via the messaging service. API modules can include a client API module and a lender API module. Microservices can include a loan applications microservice and an offers microservice.

Abstract: The present disclosure is directed to systems and methods that maintain consistency between a system architectural state and a microarchitectural state in the system cache circuitry to prevent a side-channel attack from accessing secret information. Speculative execution of one or more instructions by the processor circuitry causes memory management circuitry to transition the cache circuitry from a first microarchitectural state to a second microarchitectural state. The memory management circuitry maintains the cache circuitry in the second microarchitectural state in response to a successful completion and/or retirement of the speculatively executed instruction. The memory management circuitry reverts the cache circuitry from the second microarchitectural state to the first microarchitectural state in response to an unsuccessful completion, flushing, and/or retirement of the speculatively executed instruction.

Abstract: The technology disclosed provides a novel and innovative technique for compact deployment of application code to stream processing systems. In particular, the technology disclosed relates to obviating the need of accompanying application code with its dependencies during deployment (i.e., creating fat jars) by operating a stream processing system within a container defined over worker nodes of whole machines and initializing the worker nodes with precompiled dependency libraries having precompiled classes. Accordingly, the application code is deployed to the container without its dependencies, and, once deployed, the application code is linked with the locally stored precompiled dependencies at runtime. In implementations, the application code is deployed to the container running the stream processing system between 300 milliseconds and 6 seconds. This is drastically faster than existing deployment techniques that take anywhere between 5 to 15 minutes for deployment.

Abstract: A system links data objects associated with a common event and includes at least one processor. The system compares data objects associated with an entity and corresponding to a plurality of events for the entity, wherein the data objects are stored within a plurality of different source systems. Candidate data objects associated with a common event for the entity are identified based on the comparing. The candidate data objects are linked to form a set of data objects representing the common event for the entity. Embodiments of the present invention further include a method and computer program product for linking data objects associated with a common entity.

Abstract: Edge-based recognition systems and methods are presented. Edges of the object are identified from the image data based on co-circularity of edgels, and edge-based descriptors are constructed based on the identified edges. The edge-based descriptors along with additional perception metrics are used to obtain a list of candidate objects matched with the edge-based descriptors. Through various filtering processes and verification processes, false positive candidate objects are further removed from the list to determine the final candidate object.

Abstract: An image processing system, an image processing method, and a program capable of implementing an association of a person appearing in a video image through a simple operation are provided. The image processing system includes an input device which accepts input of video images captured by a plurality of video cameras, a display screen generating unit which causes a display device to display at least one video image among the video images inputted from the input device, and a tracked person registering unit which is capable of registering one or more persons appearing in the video image displayed by the display device. When a person appears in the video image displayed by the display device, the display screen generating unit selectably displays person images of one or more persons, which are associable with the person appearing in the video image and which are registered by the tracked person registering unit, in a vicinity of the video image.

Abstract: Techniques are provided for dynamically self-balancing communication and computation. In an embodiment, each partition of application data is stored on a respective computer of a cluster. The application is divided into distributed jobs, each of which corresponds to a partition. Each distributed job is hosted on the computer that hosts the corresponding data partition. Each computer divides its distributed job into computation tasks. Each computer has a pool of threads that execute the computation tasks. During execution, one computer receives a data access request from another computer. The data access request is executed by a thread of the pool. Threads of the pool are bimodal and may be repurposed between communication and computation, depending on workload. Each computer individually detects completion of its computation tasks. Each computer informs a central computer that its distributed job has finished. The central computer detects when all distributed jobs of the application have terminated.

Abstract: A defect inspection device includes a sample support member, a negative voltage, an imaging element, an ultraviolet light source, a movement stage, and a control device. The control device controls the movement stage such that a portion of a linear part included in the image or a location on an extensional line of the linear part is positioned at a specific location in an irradiated region of the electron beam. The control device also repeats the control of the movement stage until an end of the linear part is positioned within the irradiated region of the electron beam.

Abstract: There is provided a system and method for set overlap searching of a data lake. The method includes: receiving input tables; generating an inverted index from the input tables; receiving a query set of data values to be searched; receiving a requested set quantity; while a comparison condition is true, the comparison condition based on at least a size of the query set, iteratively performing: determining whether a first net cost of reading a candidate set is greater than a second net cost of reading an unread one of the posting lists; where its true, adding the unread one of the posting lists to the candidate set; and where its negative, determining whether the overlap between the query set and the candidate set is greater than the lowest ranked candidate set in a heap, and adding the candidate set to the heap.

Abstract: In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.

Abstract: A method and apparatus for system call command batch processing are provided. The method enable system call commands of a same type to be processed in a same CPU core according to a sequence of entering a kernel, thereby ensuring that returned results of the system call commands are sequential.

Abstract: Method, program and system for code optimization. A sign assignment instruction with input and output operands identical in size, which assigns a value of zero to a packed decimal data value that has a value of negative zero, is detected in source code or an executable program. A first instruction that checks for a possibility that the input operand is negative zero is generated based on that detection. The first instruction skips the sign assignment instruction when the input and output operand have identical addresses when and there is no possibility that the input value is negative zero; and executes a copy instruction copying the input value in the input operand to the output operand when the input and output operands have different addresses and are not overlapping. The first instruction is inserted into one of the source code or the binary executable program that is output.

Abstract: Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. The pointer chasing command indicates the number of interdependent memory accesses and information needed for the identified interdependent memory accesses. An address computing unit associated with the memory node determines the relevant memory address for an interdependent memory access absent further interaction with the issuing node or without having to return to the issuing node.

Abstract: An improved system and method are disclosed for configuring a platform instance at runtime using predefined configuration information and contexts that contain at least a portion of the predefined configuration information and also contain dynamically generated information that is not available until the platform instance is started. A core server of the platform instance is started and configured, contexts are created, and services and blocks are started and configured using the contexts.

Abstract: The present disclosure describes techniques for removing unnecessary processing stages from a graphics processing pipeline based on the format of data passed between the stages. Starting with a stage at a middle point in a pipeline, formats of data that are input to and output from the middle stage may be compared to each other. If the formats match, the middle stage may be removed from the pipeline. Thereafter, the format of data input to a pair of middle stages of the pipeline and output from the pipeline may be compared and, if they match, the middle pair may be deleted. This process may repeat until a middle pair is found where no match occurs between the input and output format. The remaining stages of the pipeline may be retained. In cases where a pipeline is not symmetrical, the formats of data at each node may be compared to each other.

Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

Abstract: A synchronization method in a computer system with multiple cores, wherein a group of threads executes in parallel on a plurality of cores, the group of threads being synchronized using barrier synchronization in which each thread in the group waits for all the others at a barrier before progressing; the group of threads executes until a first thread reaches the barrier; the first thread enters a polling state, repeatedly checking for a release condition indicating the end of the barrier; subsequent threads to reach the barrier are moved to the core on which the first thread is executing; and other cores are powered down as the number of moved threads increases; and wherein when the first thread detects the release condition, the powered down cores are powered up and are available for use by the threads.

Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

Abstract: A device configured to utilize training techniques and to gather information while training and administering certification examinations. Certification examinations may require security to ensure users taking the certification examination are actually the user designated on any issued certificate. When certification examinations are administered remotely from a proctor, different techniques to identify the user and attempt to guarantee that the user is not obtaining outside aid during the examination may be performed. Tests may be administered off-line while not connected to any network and locally cached data may be collected on the testing device for later transmittal to a back-end server for further analysis. In addition to remote proctoring/invigilating capabilities, the disclosed techniques and device may collect metrics that have a number of uses. For example, skill level of different geographical regions may be calculated to assist companies in determining a location for a new factory (e.g.

Abstract: A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system.

Abstract: An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value.

Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second sense line and configured to store a second element. An example apparatus might also include a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.

Abstract: A provisioning system to automatically determine the appropriate components to install or make available for installation on a target computer system. The provisioning system ensures the provisioning of software components that are appropriate to each target computer system without requiring user input. The provisioning system can identify support for 64-bit software components. The provisioning system checks a field in the processor to determine longword, that is 64-bit support, or checks an entry in a file maintained by an operating system to determine 64 bit support. If 64-bit support is not detected then a 32-bit component is installed to ensure that the target computer system is capable of executing the software component.

Abstract: An intelligent teaching and tutoring test method is provided with a remote learning online test mode, a remote learning test paper test mode, a classroom teaching online test mode, and a classroom teaching test paper test mode. Based on the diversified data input methods and intelligent data analyzing process offered by an intelligent teaching and tutoring test system, the invention is a proprietary teaching and tutoring test method for different learners according to their differentiated individual learning situations so as to substantially enhance the learning efficiency of the learners.

Abstract: In a computer-implemented method for deduplicating a plurality of instances of end user licensing agreements (EULAs), an end user licensing agreement (EULA) from a software bundle is accessed. Only a single instance of the EULA is displayed such that there is a deduplication of a plurality of instances of EULAs.

Abstract: The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute.

Abstract: A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.

Abstract: Various exemplary embodiments of the present invention uniquely identify players in a video game based on how a player interacts with a game and/or other players to generate a unique player identifier or player fingerprint. The player may also be categorized by player data or category to identify certain behavior (e.g., fraud). This unique information may be used to accurately authenticate the player to address fraud and other situations involving an unauthorized player. By verifying the identity of the player, an embodiment of the present invention may detect, minimize and/or prevent fraud and/or other situations where someone else is improperly playing or accessing another player's account. Authentication of player identity can also be used to detect cheating, improper sale of accounts, and other undesirable player behavior. Player fingerprint information may also be used to tailor information to the player (e.g., suggestions for other games, advertisements, instructional information, etc.).

Abstract: The present invention includes systems and methods for dynamic allocation of computing resources. Computing resources on an aircraft are divided amongst several avionics applications that are responsible for controlling sub-systems on the aircraft (e.g. the navigation system). A resource manager assigns computing resources (e.g. processor cycles) to individual applications based on the present condition of the aircraft and then instructs the throttling mechanisms to allocate the computing resources among the applications. The resource manager determines the aircraft condition by correlating inputs from the aircraft to a set of rules stored in a condition table. The resource manager then determines the computing resource allocation by correlating the aircraft condition to a set of resource allocations stored in an allocation table.

Abstract: A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping of physical registers to the set of architectural registers using the stored information.

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract: Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware interface, and a virtual GPIO controller. The driver receives a GPIO command from an operating system of the computing device. The GPIO command specifies an operation to be performed by a GPIO pin. The driver sends the GPIO command to the firmware interface. In response to the firmware interface receiving the command, the virtual GPIO controller emulates a virtual GPIO pin to implement the GPIO command. The firmware interface may trigger an interrupt that can be received by the operating system. The virtual GPIO controller may emulate the virtual GPIO pin using firmware-reserved backing memory, an embedded controller, or an interface to a peripheral device of the computing device. The firmware interface may be an ACPI control method. Other embodiments are described and claimed.

Abstract: A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.

Abstract: A memory is organized into blocks. In a bit-flipping operation, a memory block is read, the read bit data values are inverted, and the inverted data is written back to the memory block. Inverted memory blocks are tracked by setting a flag bit in the memory block, or by storing a pointer to a memory block. In a read operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the read data values are reverted before being returned. In a write operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the write data values are inverted before being written. Inversion of data values and tracking of inverted memory blocks may be performed by a specialized memory controller or by a processor executing secure memory code. Data remanence is thus prevented in the memory.

Abstract: A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.

Abstract: The present disclosure provides an electronic device and an information processing method. The electronic device comprises: a processor which comprises N processing units to process data and perform data input and output; a data processing interface coupled to Q processing units among the N processing units, which compresses raw data received from the Q processing units to obtain compressed data; and a memory coupled to the data processing interface, which receives and stores the compressed data, where N?1 and 1?Q?N.

Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

Abstract: An embodiment of a method of recognizing finger detection data in a detection data map produced by a touch screen includes converting the data from the x, y, z space into a three-descriptor space including: a first coordinate representative of the number of intensity peaks in the map, a second coordinate representative of the number of nodes (i.e., pixels) absorbed under one or more of the intensity peaks. A third coordinate may be selected as the angular coefficient or slope of a piecewise-linear approximating function passing through points having the numbers of nodes absorbed under the intensity peaks ordered in decreasing order over said intensity peaks, which permits singling out finger data with respect to non-finger data over the whole of the touch screen.