Abstract: The present invention provides a method for reducing program memory size required for a dual-issue processor with a scalar processor plus a SIMD vector processor. Coding the map of next group of instruction pairs in a no-operation (NOP) instruction of scalar and vector processor reduces the cases where one of the scalar or vector opcode being a NOP opcode. NOP for either scalar or vector processor defines the next 13 instructions as scalar-plus-vector, scalar-followed-by-scalar, or vector-followed-by-vector so that execution unit performs accordingly until next NOP or a branch instruction.

Abstract: Formatting disk drive data using format field elements (FFEs). A processing module (which can be a general purpose processor or a RISC (Reduced Instruction Set Computer) processor) is employed to generate FFEs that are employed to govern operation of the various data formatting modules within a formatting system within a HDD. The determination of when a data formatting module stops operating in accordance with a first FFE and begins operating in accordance with a second FFE can be a predetermined period of time, a number of operations being performed, the meeting of some condition, or some other means. Each FFE can be viewed as being a multi-dimensional instruction that not only includes a configuration for a data formatting module, but also includes the conditions by which the configuration is to be governed by a subsequent FFE, among other things.

Abstract: A RISC processor apparatus and method for supporting an X86 virtual machine.

Abstract: A multithreaded processor with dynamic thread based throttling, more specifically, based at least in part on the aggregated execution bandwidth requests of the threads, is disclosed herein. In various embodiments, the multithreaded processor may throttle by scaling clock frequency and/or voltage provided to the processor, based at least in part on the aggregated execution bandwidth requests of the threads. The aggregation and scaling may be performed when a bandwidth allocation request of an instruction execution thread is modified or when a computation intensive instruction execution thread is activated or re-activated. Other embodiments and/or features may also be described and claimed.

Abstract: Bit reductions in program instructions are achieved by determining the set of bit patterns in bit locations of the instructions. If only a subset of bit patterns is present in the instructions, they may be represented by an index value having a smaller number of bits. The index value may be substituted into the instruction and later used in decoding by referencing a corresponding bit pattern in a lookup table. The bit-reduction in the instruction makes way for supplemental data bits which may then be embedded.

Abstract: An RISC processor and a method for converting and looking-up instruction address in the RISC processor. The device comprises a decoder, which includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table. The look-up table module includes: a looking-up sub-module for indexing the look-up table based on content, wherein if looking-up is hit, the corresponding content will be stored in a target register, and if not, an entry address of the not-hit service program will be stored in the target register; and an indexing sub-module for indexing the look-up table based on content and getting an index of the table entry in which the content resides.

Abstract: An RISC processor device and a method of emulating a floating-point stack operation thereof The processor device comprises: a floating-point register file containing a plurality of floating-point registers; a decoding section for decoding operation instructions of the RISC processor; a floating-point operation section connected to the decoding section; a control register for controlling the status of the floating-point registers and controlling the decoding section and the floating-point operation section to emulate a floating-point register stack using the floating-point register file.

Abstract: The present invention discloses a RISC processor and a method of processing flag bits of a register in the RISC processor. Said RISC processor comprises a physical register stack, an operating component connected to the physical register stack and an decoder connected to the operating component; the physical register stack comprises an emulation flag register for emulating to realize flag bits of a flag register in a CISC processor; the operating component comprises a flag read-write module for reading and writing the values of the flag bits of the emulation flag register. The operating component further comprises an operating controller for performing an operation control according to the values of the flag bits of the emulation flag register when the RISC processor is in the working mode of X86 virtual machine during an operation process.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

Abstract: An apparatus and method for managing stacks in a virtual machine are provided. The apparatus includes a first memory which checks the space of a stack chunk and allocates a frame pointer if at least one of a push and a pop are performed in a virtual machine; and a second memory which is connected with an external bus, and stores frame pointers copied from the first memory via the external bus.

Abstract: A system and method by which a memory device can adapt or retrain itself in response to changes in its inputs or operating environment. The memory device, such as a DRAM, includes in its interface an embedded programmable component. The programmable component can be, for example and without limitation, a microprocessor, a microcontroller, or a microsequencer. A programmable component is programmed to make changes to the operation of the interface of the memory device, in response to changes in the environment of the memory device.

Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.

Abstract: A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions and can be used to unify one or more ISA extensions such as application specific ASEs. The re-encoded ISA maintains assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions.

Abstract: The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where the SIMD processor could perform N LUT operations per instruction. Histogram operation is partitioned into a vector LUT operation, followed by vector increment, vector LUT update, and at the end by reduction of vector histogram components. The present invention could be used for intensity, RGBA, YUV, and other type of multi-component images.

Abstract: Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits in the P-register from 9 to 10. A tenth bit signals an extended instruction mode. When the tenth bit is not set, microprocessor instructions perform legacy functions. When the tenth bit is set, the extended instruction mode is active and instructions perform different or enhanced functions.

Abstract: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

Abstract: A multicore processor for industrial control provides for the execution of separate operating systems on the cores under control of one of the cores to tailor the operating system to optimum execution of different applications of industrial control and communication. One core may provide for a reduced instruction set for execution of industrial control programs with the remaining cores providing a general-purpose instruction set.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating the interoperability of native and non-native program modules within a native computing platform. More specifically, this technology involves an emulation of the kernel of the non-native operating system. Instead of interacting with the native kernel of the native computing platform, the non-native program modules interact with a non-native kernel emulator. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Reduced instruction set computer (RISC) processor based disk manager architecture for HDD (Hard Disk Drive) controllers. A means is presented herein by which disk managers operations of a HDD are off-loaded from a main processor to a dedicated RISC processor. The main processor is operable to provide higher level instructions to the RISC processor, and the RISC processor is operable to translate those higher level instructions into bit level instructions that are subsequently provided to one or more control engines that is then operable to execute those bit level instructions to perform one or more channel interfacing protocol control functions that can include any one or more of low level timing for servo demodulation, timing for data formatting operations, media control operations, transfer control operations, and/or other disk manager related functions.

Abstract: The invention relates to a process for compression of executable code (2) by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part (BC) of predefined fixed length and a part (VLI) of variable length whereof the length is defined by the part of fixed length; and combining all the parts of fixed length and all the parts of variable length of the words respectively into a block of parts of fixed length and in a block (12) of parts of variable length, the respective positions of at least certain parts of variable length in the block of parts of variable length being saved in an addressing table (13).

Abstract: This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.

Abstract: A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerator circuits are coupled to both the RISC and CISC cores, with both cores and both accelerator circuit being incorporated into a single integrated circuit. In a first plurality of operational modes, the RISC core is active, while the CISC core is in one of a sleep state or a power off state. In a second plurality of modes, both the RISC and CISC cores are active.

Abstract: A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is annotated with the results of the benchmarking of the program image. Basic blocks of the program are then grouped into bins. When the program image is executed, a drafting scheduler stops threads before they leave a bin and schedules any threads queued for the same bin.

Abstract: A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.

Abstract: An effects processor for an effects module. The effects processor comprises a RISC processor, a DSP for fast integer multiplication and a small memory. The processor uses VARK language and a lookup table of VARK scripts to apply a variety of effects to images stored outside the effects module. The effects processor includes a serial bus interface which communicates with the Serial Bus of a compact printer system comprising one or more further modules. The Serial Bus communicates power and data between the effects module and one or more of the further modules. Methods of compositing, convolving, warping and color substitution are described.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A method of and an apparatus for performing efficient software emulation of a multi-processor target computer by a host computer. The software technique permits multiple processors to be emulated by a single processor. The use of software emulation permits the host computer to execute both host programs and target programs. The software emulation is made particularly efficient by utilizing the operation code combined with a separate four bit field to directly address the corresponding host instructions.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

Abstract: The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is then converted by the network device interface into digital signals and transmitted back to the controller. In one advantageous embodiment, the network device interface uses a specialized protocol for communicating across the network bus that uses a low-level instruction set and has low overhead for data communication.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions for a signal processor. The unified RISC/DSP pipeline controller is coupled to a program memory, a RISC control unit, and at least one signal processing unit. The program memory stores both DSP and RISC control instructions and the RISC control-unit controls the flow of operands and results between the signal processing unit and a data memory that stores data. The signal processing unit executes the DSP instruction. The unified RISC/DSP pipeline controller generates DSP control signals to control the execution of the DSP instruction by the signal processing unit and RISC control signals to control the execution of the RISC control instruction by the RISC control unit.

Abstract: A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus 102 through a bus bridge 113. A first set of processing resources operate from high speed bus 102 and includes an external memory interface 108, a direct memory access engine 105 for controlling the exchange of information through memory interface 108, and a boot memory 104 for storing boot code. A second set of processing resources operate from peripheral bus 103 and includes an interrupt controller 115 for issuing interrupt requests to microprocessor 101, a set of programmable timers 117 for generating timed interrupt signals, and a phase locked loop 131 for generating timing signals.

Abstract: A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality of flags each correspond to a class of instruction occurring in the instruction pipeline circuitry. Pipeline control circuitry cooperates with the instruction pipeline circuitry, as part of the basic execution cycle of the computer, to maintain the value of the flags to record failures of an attempt to execute in the first mode two mode instructions of the corresponding respective instruction classes, to be triggered by a timer expiry to switch the value of the flags, thereby to switch the instruction pipeline circuitry from one of the processing modes to the other for the corresponding instruction class.

Abstract: A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an application's register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an application's user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.

Abstract: The present invention provides a RISC processor with a debug interface unit that enables the external replication of the data processing sequence within a RISC processor for debug purposes. The data exchanged between the sequence controller and the instruction decoder are intermediately stored and forwarded via a free bus line to an interface unit. In the interface unit, the data pending at its inputs are forwarded to defined outputs of the interface. This allows the register contents to be co-read in real time. Accordingly, all the required information to perform an efficient error search are displayed for an outside operator who may then monitor the data processing sequence and conduct an error search.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The dependency logic then selects between first and second issue queue partitions for storing the first and second instructions pending issue based upon the dependency determination, wherein the first issue queue partition issues instructions to a first execution unit and the second issue queue partition issues instructions to a second execution unit. The first and second issue queue partitions may be asymmetric with respect to a first register file in which instruction results are stored. The first and second instructions are then stored in the selected partitions.

Abstract: A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions.

Abstract: A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.

Abstract: A method for improving instruction selection efficiency in a DSP/RISC compiler. Concurrently obtaining optimal performance and space, the method includes the following steps: determining a semantic tree for a basic block; finding all matching combinations for the semantic tree with reference to a set of patterns; determining cycle number and instruction length for all combinations; filtering the instruction length greater than a predetermined instruction length and extra ones having the same cycle number and instruction length according to the determined cycle number and instruction length; and choosing one combination with the smallest cycle number from the remaining combinations and outputting the one combination as the desired object code.

Abstract: A programmable single-chip device, comprising a programmable gate array (PGA) section, a DSP core and a RISC core. The device is ideal for prototyping and deploying low-to-moderate volume implementations of high-bandwidth algorithms, which have processing requirements split between front-end, high iteration, low-numeric-agility, “wide” loadings, middle-end, moderate iteration, high-numerical-precision loadings and back-end, low-iteration, highly conditional loadings, without the commensurate problems inherent in the custom ASIC, joint FPGA/DSP/RISC (or even direct compilation to FPGA) solutions.

Abstract: Microcomputer systems include an instruction processor therein that can process both normal length instructions and compressed instructions. The normal length instructions and the compressed instructions are provided from memory to an instruction register and then passed through decoding circuitry to a processor core. The decoding circuitry preferably comprises a demultiplexer having a data input that receives a first multi-bit instruction from the instruction register and a select input that receives a first select signal (SEL1). A compressed instruction decoder is also provided. The compressed instruction decoder has a data input electrically coupled to a first data output of the demultiplexer and a select input that receives a second select signal (SEL2). A multiplexer is also provided.

Abstract: A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: Legacy instructions of a guest system are dynamically emulated on a host system in blocks using block addresses. Detailed translation information is stored in a translation store. Translation indications for a subset of all the translated blocks are stored into a tracking table at block numbers determined by the block addresses. Each particular legacy instruction of a translated block is translated into one or more translated instructions for emulating the particular legacy instruction. If the particular legacy instruction is a store instruction, the indication in the tracking table is checked for the particular block number to determine if instruction data has been stored. If instruction data has been stored for the particular block number, the translation store is checked to determine if instruction data has been modified. If instruction data has not been stored for the particular block number, the checking of the translation store is bypassed adding to the efficiency of the emulation.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. The guest computer architecture has programs composed of legacy instructions. To perform the emulation of the legacy instructions on the host system, the legacy instructions are accessed in the host system. Each particular legacy instruction is translated into one or more particular translated instructions for emulating the particular legacy instruction. RISC blocks translated from CISC blocks are held in system memory cache. The efficiency of translation of CISC blocks to RISC blocks in the cache is improved by using small-, equal-sized RISC blocks that are linked into a logical entity. The logical entity is a linked group of one or more RISC blocks logically linked for each CISC block. The logical links from one RISC block to another RISC block are implemented by a linked-list.