Abstract: The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector.

Abstract: A wide memory architecture is provided for storing data associated with a vector processor. Additionally, a method for accessing a wide memory architecture is provided. The wide memory architecture includes a memory for storing an array of vector operands. The memory is coupled to a data bus which provides an access pathway connecting the memory to a processor. The wide memory architecture further includes at least one staging buffer disposed between the memory and the processor. The staging buffer is capable of providing intermediate storage of a vector operand upon which a function can be performed by the processor.