Speculative Instruction Execution, E.g., Conditional Execution, Procedural Dependencies, Instruction Invalidation (epo) Patents (Class 712/E9.05)
  • Patent number: 8656102
    Abstract: A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method includes an off-execution step of determining tasks that can be executed on a processing unit subsequently to the execution of a given task. The method also includes, during execution of the given task, computing a priority for each of the tasks that can be executed. The priority depends on information relating to the current execution of the given task. The method also includes, during execution of the given task, sorting the tasks that can be executed in the order of their priorities. The method also includes, during execution of the given task, preloading into the memory, bitstreams representing the information of the configurations for the execution of the tasks that can be executed, while favoring the tasks whose priority is the highest.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: February 18, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Stéphane Guyetant, Stéphane Chevobbe
  • Patent number: 8041926
    Abstract: Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include application code. The block of code does not necessarily indicate that the block of code should be speculatively executed.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 18, 2011
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf
  • Patent number: 8028132
    Abstract: The present invention relates to mechanisms for handling and detecting collisions between threads (5, 6, 7) that execute computer program instructions out of program order. According to an embodiment of the present invention each of a plurality of threads (5, 6, 7) are associated with a respective data structure (9, 10, 11) comprising a number of bits (12) that correspond to memory elements (m0, m1, m2, mn) of a shared memory (4). When a thread accesses a memory element in the shared memory, it sets a bit in its associated data structure, which bit corresponds to the accessed memory element. This indicates that the memory element has been accessed by the thread. Collision detection may be carried out after the thread has finished executing by means of comparing the data structure of the thread with the data structures of other threads on which the thread may depend.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: September 27, 2011
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Anders Widell, Per Holmberg, Marcus Dahlström
  • Patent number: 7840785
    Abstract: Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include application code. The block of code does not necessarily indicate that the block of code should be speculatively executed.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: November 23, 2010
    Assignee: Azul Systems, Inc.
    Inventors: Gil Tene, Michael A. Wolf