Abstract: Aspects relate to a stepped clocking frequency mode for integrated circuit components. An apparatus includes a processor core configured to perform operations at a received clocking frequency and a clock controller. The clock controller is configured to clock the processor core with a default frequency in response to the processor core operating in a default mode of operation, and, responsive to a parameter value associated with the processor core exceeding a first threshold, to enter a stepped clocking frequency mode, that includes alternating between clocking the processor core at a first frequency for a first time interval, and clocking the processor core at a second frequency different than the first frequency for a second time interval.

Abstract: According to various aspects, a controller may be configured to: control a transmission over a single-wire interface of an instruction corresponding to a high-current operation; and control an electrical behavior of a charging path to provide current at the single-wire interface during a time period corresponding to an execution of the instructed high-current operation.

Abstract: In certain aspects, a memory system may include at least one memory device and a memory controller coupled to the at least one memory device. Each memory device may include an array of memory cells and a control logic coupled to the array of memory cells. The memory controller and the control logic of the memory device may be powered by a first power source having a first predetermined power consumption threshold. The array of memory cells of the memory device may be powered by a second power source having a second predetermined power consumption threshold.

Abstract: A power system and method of operating the same. In one embodiment, the power system includes a plurality of power converters configured to power a host system. The power system also includes a power converter controller configured to provide a status of and control the plurality of power converters and at least one system element of the host system responsive to a plurality of host system signals. The control includes a scripted sequence of events as function of a change of an operational condition of at least one of the plurality of power converters and the host system.

Abstract: A datacenter includes a datacenter efficiency management system coupled to node devices. For each of the node devices and based on a power consumption associated with that node device and a performance associated with that node device, the datacenter efficiency management system generates a node group ranking that it uses to group subsets of the node devices into respective homogenous node groups, and then deploys a respective workload on at least one node device in each of the homogenous node groups. Based on at least one of a node workload bandwidth, a node power consumption, and a node health of each node device on which a workload was deployed, the datacenter efficiency management system then generates a workload performance efficiency ranking of the node devices that it then uses to migrate at least one workload between the node devices.

Abstract: A submodule for conversion of DC power capable of a plurality thereof being connected in series and used for DC-DC conversion in accordance with the present invention comprises: a power switching element for switching DC power supply to convert a source of DC including voltage transformation; a DC capacitor for storing DC power opened or closed by the power switching element; a power supply unit for supplying power required to drive the submodule from the DC capacitor; a submodule controller for controlling whole operation of the submodule; memory for storing data required for operating the submodule controller; and a communicating unit for performing data communication with an external device; wherein the submodule controller may perform a program update during a start sequence of the submodule or during a stop sequence thereof, while DC-DC conversion is operated.

Abstract: Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

Abstract: Example implementations described herein are directed to systems and methods for managing internet protocol (IP) address assignment to servers on rack(s) based on their physical locations within the rack(s). Through the example implementations, the physical location of a server within a data center rack can be determined based on the IP address. Example implementations can involve issuing a ping local to determine a plurality of servers; retrieving power on time, current system time, and operating system (OS) uptime for each of the plurality of servers; determining a power on order for the plurality of servers; determining physical locations of the plurality of servers within one or more racks based on installation instructions and power on order; and assigning IP addresses to the plurality of servers based on the physical locations.

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Abstract: A controller for generating a sequence of pulse is disclosed. The controller includes a plurality of pulse width modulation (PWM) modules. Each PWM Module configured to generate a first sequence of pulses and a second sequence of pulses each having a width that is modulated by a PWM value stored in a PWM register of the PWM module. Each PWM module includes two outputs. The first sequence of pulses is outputted on the first output and the second sequence of pulses is outputted on the second output. The controller also includes a memory having a plurality of memory tables and a plurality of direct memory access (DMA) modules. Each memory table configured to store PWM values to be written into the PWM register and each DMA module is coupled to a respective PWM module in the plurality of PWM modules and to a respective memory table in the plurality of memory tables and configured to write a PWM value from the memory table into the PWM register in response to a DMA trigger.

Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.

Abstract: Example implementations described herein are directed to systems and methods for managing internet protocol (IP) address assignment to servers on rack(s) based on their physical locations within the rack(s). Through the example implementations, the physical location of a server within a data center rack can be determined based on the IP address. Example implementations can involve issuing a ping local to determine a plurality of servers; retrieving power on time, current system time, and operating system (OS) uptime for each of the plurality of servers; determining a power on order for the plurality of servers; determining physical locations of the plurality of servers within one or more racks based on installation instructions and power on order; and assigning IP addresses to the plurality of servers based on the physical locations.

Abstract: The invention relates to a user interface device (1) coupleable to a control unit (2) via a connection cable (3) comprising at least one optical fiber for transporting light. The user interface device (1) comprises a light inlet opening (21) configured to receive light from a region outside a housing (9) of the device (1) and to couple the received light into the first optical fiber (8a) for transmitting the light to the control unit (2) when the user interface device (2) is switched off. Moreover, the invention relates to a control unit (2) coupleable to the user interface device (1) via the connection cable (3). The control unit (2) is configured to detect changes of the light received via the first optical fiber (8a) and to activate power supply to the user interface device (1) to switch on the user interface device (1) based upon the detected changes.

Abstract: Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

Abstract: A system includes a memory device and a power disable circuit coupled to a bus connector and to power circuitry adapted to power on and off the memory device. A processing device is coupled to the bus connector, to the power disable circuit, and to the memory device. The processing device is to monitor a state of a power disable (PWDIS) signal of the bus connector while the PWDIS signal is at a first voltage level, and in response to the PWDIS signal transitioning to a second voltage level, determine whether a length of time for which the PWDIS signal has been at the second voltage level satisfies a threshold criterion. In response to the length of time for which the PWDIS signal has been at the second voltage level satisfying the threshold criterion, the processing device is to enable the power disable circuit with a general purpose input/output signal.

Abstract: A power management system includes connection interfaces, a system power supply, and a power management circuit. Each connection interface is connected to one power consumption device. The system power supply includes power supply units (PSUs). The system power supply supplies electricity power to each power consumption device via one connection interface. The power management circuit is connected to each power consumption device via the connection interfaces. The power management circuit obtains a current total load of PSUs, determines a target load of each PSU, and determines whether each connection interface is connected to one power consumption device. The power management circuit turns off power supply to the connection interface that is not connected to the power consumption devices. According to the current total load and the target load, the power management circuit determines an enabled number of the PSUs, thereby turning on or turning off each PSU accordingly.

Abstract: An apparatus including (i) a processor including a plurality of main buffer on board (BOB) memory controllers (MCs) and a secure engine, (ii) a plurality of simple BOB MCs, (iii) a secure delegator, and (iv) a plurality of memory modules. The secure delegator coupled to a first main BOB MC and a first simple BOB MC creates a secure channel. A second main BOB MC coupled to a second simple BOB MC creates a non-secure channel. The plurality of main BOB MCs, the secure engine and the secure delegator are provided within a trusted computing base (TCB) of the apparatus and the plurality of simple BOB MCs and the plurality of memory modules are provided outside the TCB. The secure delegator is configured to: (i) secure communication between the first main BOB MC and the secure delegator, and (ii) perform Path ORAM accesses to the plurality of memory modules.

Abstract: A method for protecting operation of a server backboard is provided. The method includes: establishing an adaptive setting mechanism for an overcurrent protection point of the server backboard, where a backboard operation overcurrent protection unit is established on a server mainboard and is configured to acquire load information of a current backboard and adjust, based on the load information, an overcurrent protection point of a power supply path provided by the mainboard to the backboard; establishing an automatic current limiting mechanism applied in a case where the backboard is in an overcurrent state; and establishing a server backboard abnormality control unit.

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

Abstract: A power supply apparatus is connectable to a common communication line together with at least one other apparatus. The power supply apparatus includes a communication interface and a controller. The communication interface is configured to transmit a signal indicating the presence of the power supply apparatus to a first apparatus connected to the power supply apparatus among the at least one other apparatus and to receive a signal indicating the presence of a second apparatus from the second apparatus connected to the power supply apparatus among the at least one other apparatus. The controller is configured to determine whether the power supply apparatus is connected to an end portion of the common communication line, based on whether the communication interface has received the signal indicating the presence of the second apparatus.

Abstract: A method and apparatus that provides a solid state drive that analyzes connection performance during I/O operations and is configured to independently modify connection performance based upon user specified input parameters without the need for host computer management.

Abstract: A CPUs operate by predetermined power that is generated based on power supplied from a power source unit. A multiplexer (MUX) is supplied with power from the power source unit, and suspends connection between the CPUs and a second arithmetic-processing unit when the CPUs are connected to the second arithmetic-processing unit included in another system board, and connects the CPUs and the second arithmetic-processing unit after predetermined time passes.

Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

Abstract: Embodiments of a method and device are disclosed. In an embodiment a controller is disclosed. In an embodiment, the controller includes a pulse width modulation (PWM) module configured to generate a sequence of pulses each having a width that is modulated by a PWM value stored in a register of the PWM module, a memory having a table of PWM values configured to be written into the PWM module register, a direct memory access (DMA) module coupled to the PWM module and to the memory table and configured to write a PWM value from the memory table into the PWM register in response to a DMA trigger, and a core coupled to the DMA module and configured to write the PWM values into the memory table.

Abstract: The disclosed embodiments describe methods, devices, and computer-readable media for protecting the integrity of volatile memory devices. In one embodiment, a method is disclosed comprising detecting a power interrupt condition of a memory device; and executing at least one operation in response to detecting the power interrupt condition, the operation selected from the group of operations consisting of: placing the memory device in a pre-charge mode, pausing a self-refresh mode of the memory device, forcing the memory device into a reset mode, or rewriting data in the memory device.

Abstract: A method for storing data on a storage entity (SE) includes: computing a file identifier for a file to be stored on the SE; checking if the file has already been stored using the file identifier; generating a user-specific private and public identifier; updating or computing tags of the file by the client such that the updating or computing is homomorphic in the user-specific private identifier and in parts of the file; providing the user-specific public identifier, the updated tags and a proof of possession of the secret identifier to the SE; verifying the proof-of-possession; verifying validity of the tags; upon successful checking, storing a public identifier for the file incorporating the user-specific public identifier and the updated tags by the SE; and upon a case where it is determined that the file has not already been stored, storing the file.

Abstract: In one embodiment, a method includes determining a plurality of hardware components of a system. The method also includes power cycling a first hardware component of the plurality of hardware components of the system according to a dynamic schedule. A period of time in which power cycling of the first hardware component takes place is shortened as the age of the first hardware component approaches the expected lifespan of the first hardware component. Also, the method includes determining whether the first hardware component experienced a power-up failure resulting from the power cycling. Moreover, the method includes outputting an indication to replace and/or repair the first hardware component in response to a determination that the first hardware component experienced the power-up failure resulting from the power cycling. Other systems, methods, ad computer program products for preventing unexpected power-up failures of individual hardware components are described in accordance with more embodiments.

Abstract: A power distribution board for a modular chassis system, wherein the modular chassis system is configured to install a plurality of electrical devices, and the power distribution board comprises: a plurality of detecting pins, a microcontroller and a plurality of protecting circuits. The plurality of detecting pins electrically connects to the plurality of electrical devices respectively, and each detecting pins is configured to detect a modular type of a respective one of the electrical devices. The microcontroller electrically connects to the plurality of the detecting pins and selectively chooses one of a plurality of configurations according to the detected modular type. Each of the protecting circuits electrically connects to the microcontroller and corresponds to one of the electrical devices, each of the protecting circuits set a rated power value according to the chosen one of the configurations.

Abstract: A system for performing computing operations in a data center includes one or more sets of computer systems, one or more primary power systems, and a reserve power system. The primary power systems include at least one power distribution unit that supplies power to at least one of the sets of computer systems. The reserve power system automatically supplies power to at least one of the sets of computer systems if a condition is met (such as a failure of the primary power system).

Abstract: Compounds for use as photoredox catalysts and as redox shuttles in a rechargeable battery having a high-voltage cathode providing overcharge protection capabilities are provided, including a compound according to the formula: wherein R is selected from the group consisting of alkyl, aryl, alkylaryl, alkoxyaryl, alkylcarboxyl, aryl carbonyl, haloalkyl, perfluoroalkyl, glycols, haloaryl, a negative electrolyte, and a polymer.

Abstract: In various example embodiments, a battery-assisted PoE powered device is provided that includes a local battery pack for providing a burst of power to a device load in excess of the continuous power available via PoE. A charger/path controller charges the local battery pack during periods of time when the device load consumes less power than available via PoE (e.g., consumes less than the 71W of guaranteed continuous power under IEEE 802.3bt). During periods of time when the device load demands more power than available via PoE (e.g., when peak power is demanded by an audio speaker, when inrush occurs in a motor, or for various types of intermittent devices when they are activated) the charger/path controller discharges the battery pack, to drive the device load with a combination of PoE and battery power.

Abstract: Embodiments are described for performing an uninterrupted backup in a storage system in view of one or more abort events. A backup agent receives writes one or more data blocks to a write latch. A parent interrupt service routine (ISR) polls for abort events. In response to an abort event, an intermediate interrupt is generated that spawns a child processes for each process of the backup. The intermediate ISR logs each child ISR, the process it is responsible for, and the intermediate interrupt, for later restoration of the backup state. After a recovery of the above event, then each child ISR can be called to restore its state. After restoring the state, the backup agent resumes the backup from where the abort event was detected. The child ISRs are re-entrant. If another abort event is detected, the backup state can again be saved and later resumed from that state.

Abstract: A management device includes a processor that stores, in a second memory, power source information indicating first states of power sources of respective first electronic apparatuses included in an electronic apparatus group. The processor instructs, upon receiving a first instruction, the first electronic apparatuses identified by first apparatus information held in a first memory to transition the respective first states. The processor receives a second instruction to add a new electronic apparatus to the electronic apparatus group. The processor suppresses, in a case where any one of the first states is being transitioned, second apparatus information of the new electronic apparatus from being stored in the first memory. The processor stores the second apparatus information in the first memory in a case where transition of all the first states has been completed, and matches a second state of a power source of the new electronic apparatus with the first states.

Abstract: Machine logic (for example, software) for compressing the image of an instance of a VM/container during time period(s) when the VM/container instance is inactive. A proxy is used to handle requests made to the VM/container instance during periods when it is inactive. A dependency graph is used to determine that a related set of instances of VM/containers so that: (i) when one of the VM/container instances of the related set is deactivated, then the whole set of VM/container instances are deactivated together; and/or (ii) when one of the VM/container instances of the related set is reactivated, then the whole set of VM/container instances are reactivated together.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may monitor, in a first bandwidth part, of a plurality of bandwidth parts, associated with a first monitoring periodicity and in a downlink control channel, for a downlink control information (DCI) message. The user equipment may selectively transition, based at least in part on the DCI message, from the first bandwidth part to a second bandwidth part, of the plurality of bandwidth parts, associated with a second monitoring periodicity that is less than the first monitoring periodicity. Numerous other aspects are provided.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for determining that an update of the PSU firmware is received for a plurality of PSUs of a data center; determining that an update priority flag indicates unthrottled operation of the data center, and in response: determining that a number of PSUs of the data center is greater than a minimum number of PSUs for the unthrottled operation of the data center, and in response, applying the update to each of the PSUs; determining that the number of PSUs of the data center is less than the minimum number of PSUs for the unthrottled operation of the data center, and in response: adjusting a power capacity and maximum current state of the data center, and after adjusting the power capacity and the maximum current state of the data center, applying the update to each of the PSUs.

Abstract: In some embodiments, power may be temporarily removed from a first portion of a computer system (such as a display), and that power redirected to a second portion (such as a processor or System on a Chip), so that extra performance may be obtained from the second portion without exceeding the power budget for the system. If the first portion is a display, the time period of removed power may be short enough that the absence of luminance during that time period will not be noticeable to the human vision system. In a similar embodiment, power may be delivered to the first portion using pulse width modulation, using the time between pulses to redirect power to the other portion.

Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.

Abstract: A method for shutting down a virtual system including several virtual machines hosted by one or more physical servers includes the steps of: receiving a shutdown command for the virtual system or detecting an event that triggers a process for shutting down of the virtual system; sending a request for data about dependencies in the virtual system; retrieving the requested data; generating a sequence of shutdown actions depending on the retrieved requested data, the sequence including a shutting down of all applications executed by the virtual machines, the shutting down of all virtual machines, and then the shutting down of all virtual machine managers; and executing shutdown actions in the generated sequence in order to shut down the virtual system.

Abstract: When a transition control unit stochastically determines whether to accept one of a plurality of state transitions, using a temperature, an energy change, and a random number, depending on a relative relationship between the energy change and thermal excitation energy, the transition control unit adds an offset to the energy change, controls the offset so as to be larger at a local minimum, at which the energy is locally minimized, than at a solution at which the energy is not minimized, and resets the offset to zero when the energy change value is larger than a threshold.

Abstract: An industrial asset management system includes a data acquisition system configured to receive asset data associated with at least one industrial asset and to modify the data acquisition system to enable the continued receipt of asset data associated with the at least one industrial asset in response to a detection of an internal change at the data acquisition system by the data acquisition system and a data processing system communicatively coupled to the data acquisition system and configured to process the asset data received from the data acquisition system and to modify the data processing system for the continued processing of the asset data in response to a detection by the data processing system of an internal change at the data processing system or the data acquisition system.

Abstract: When stochastically deciding, based on a change in energy and a random number relating to thermal excitation, whether to accept any of a plurality of state transitions according to the relative relationship between the change in energy and thermal excitation energy, a transition control unit adds an offset to the change in energy, performs control so that the offset at a local minimum where energy is locally minimized is larger than an offset when the energy is not minimized, holds transition information (a transition number) indicating a previous state transition, and prohibits, based on a decoding result for the held transition information, a first state transition out of the present state transition candidates.

Abstract: Improved apparatus and system for the backup and recovery of a computer system with minimized key strokes and steps for a user. The improved apparatus and system includes an external hard drive, power controls, keyboard controller, and flash drive, all of which are referred to as the present invention DittoDrive™, to allow a user to copy the contents of a computer hard drive to a second hard drive and then allow the user to operate the computer from either the first hard drive or the second hard drive.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: Systems and methods for managing the operation of Power Supply Units (PSUs) are described. In some embodiments, a method may include: identifying a mismatch between a first Power Supply Unit (PSU) and a second PSU in an Information Handling System (IHS), disabling the first PSU, determining that a voltage at an input line of the first PSU follows a predetermined pattern while the first PSU receives a secondary bias from the second PSU, and enabling the first PSU.

Abstract: Disclosed is an organic light-emitting display device including: a display panel; a drive IC configured to supply a driving signal to the display panel; and a controller configured to operate in one of a first driving scheme, in which, when turned on, a sensing period of sensing characteristics of the display panel is executed, after which a display period of displaying an image on the display panel is executed, and a second driving scheme, in which, when turned on, the display period of displaying the image on the display panel is executed, the controller operating in the second driving scheme when turned on within a preset time after having been turned off.

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

Abstract: A simulation environment benchmarks processors to determine processor performance. A benchmark program is instrumented with a microarchitecture instruction. A first clock cycle indicative of a processor before executing the benchmark program is captured. The benchmark program is executed and a processor return related to the microarchitecture instruction is intercepted. In response to the processor return, a second clock cycle indicative of the processor after executing the benchmark program is captured. The simulation environment determines the performance of the processor from the first clock cycle and the second clock cycle.

Abstract: A measurement and control system comprises a housing and an electrical power distribution sub-system. The housing includes a plurality of addressable and programmable modules, a module rack that is expandable and having a length, and a main controller configured to communicate with the plurality of addressable and programmable modules. Each of the addressable and programmable module is installed on the module rack in a sequential configuration and is addressable based on a specific physical location of it across the length of the module rack. The main controller communicates with the plurality of addressable and programmable modules by addressing through a communication network. The electrical power distribution sub-system is configured to monitor inputs and signals from the each addressable and programmable module.

Abstract: A control device includes a processor. The processor is configured to receive a write request to write content data. The processor is configured to divide the content data into leading first data and subsequent second data. The processor is configured to write the first data to a first storage resource in a first storage group among a plurality of storage groups having operating rates different from each other. The first storage group has a first operating rate higher than operating rates of any other storage groups. The processor is configured to write the second data to a second storage resource in a second storage group. The second storage group has a second operating rate lower than the first operating rate. The processor is configured to activate, in parallel with the writing of the first data, the second storage resource when the second storage resource is in a non-operating state.