Abstract: Power sourcing equipment starts power supply after outputting a detection signal to a transmission line and detecting that a powered device is connected with the transmission line. The powered device includes a power storage unit configured to store power obtained from the detection signal output from the power sourcing equipment, and a correction unit configured to correct an impedance unbalance in the transmission line. The power storage unit provides the stored power to the correction unit.

Abstract: Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.

Abstract: A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.

Abstract: Techniques for securely updating a boot image without knowledge of a secure key used to encrypt the boot image.

Abstract: The disclosed embodiments provide a system that performs power management on a computer system. The system includes an embedded controller and an operating system. During the execution of a sleep sequence by the operating system, the embedded controller latches events associated with use of the computer system. After the sleep sequence has completed, the embedded controller compares the latched events with a set of enabled wake events for the computer system and a current state of the computer system. If the latched events indicate that the current state corresponds to one of the enabled wake events, the embedded controller triggers a wake sequence on the computer system.

Abstract: A demand based power re-allocation system includes one or more subsystems to assign a power allocation level to a plurality of servers, wherein the power allocation level is assigned by priority of the server. The system may throttle power for one or more of the plurality of servers approaching the power allocation level, wherein throttling includes limiting performance of a processor, track server power throttling for the plurality of servers. The method compares power throttling for a first server with power throttling for remaining servers in the plurality of servers and adjusts throttling of the plurality of servers, wherein throttled servers receive excess power from unthrottled servers.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.

Abstract: A card interface direction detection system includes a card. A power pin is mounted to the card and connected to a power source. A ground pin is mounted to the card and connected to a ground. A direction pin is mounted to the card. A controller is coupled to an information handling system (IHS) and that includes an in node and an out node that are each connected to the direction pin. The in node is directly connected to the direction pin and a resistor is located between the out node and the direction pin such that a signal sent through out node results in a signal received through the in node that allows the controller to detect whether the mode of operation of the card is supported by the IHS.

Abstract: The disclosed embodiments provide a system that enables a portable computing device to receive power through multiple bus interfaces at the same time. When the system senses that a first power source is plugged into a first bus interface in the portable computing device, the system determines whether the first power source is a host or a power adapter. Next, based upon whether the first power source is a host or a power adapter, the system uses a first power manager coupled to the first bus interface to limit a first input current received from the first power source to power the computing device. The system also provides the maximum charging current to a rechargeable battery for the portable computing device by chaining together a second bus interface whether power is present on the second bus interface or not.

Abstract: A power management method of a computer system is provided. The method includes the following steps. Health states of a plurality of power supplies are detected to generate a detection signal. Output powers provided by the power supplies are received to calculate a total maximum output power of the power supplies. An interrupt is generated by triggering a configuration management program according to the total maximum output power or the detection signal. The interrupt is processed by an interrupt handler to adjust a power consumption of a central processing unit (CPU).

Abstract: A power supply control apparatus that includes an instruction component, an execution component and a power supply control component is provided. The power supply control component is equipped with at least two measurement functions that have different measurement durations for cases in which the duration until interrupting the power supply to device(s) is measured, wherein measurement is activated with a first measurement function of relatively long measurement duration at a completion time of prior image processing, and measurement is activated with a second measurement function of relatively short measurement duration for device(s) to which power is being supplied at the time of completion of the prior image processing but which are not required in later image processing.

Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

Abstract: An electrical apparatus includes a main unit which consumes electrical power; a power supply unit which supplies electrical power from a commercial power source to the main unit; a secondary battery to be charged with electrical power supplied from the power supply unit; and a power source control unit. In a state where a power source of the main unit is the power supply unit, when power consumption of the main unit exceeds a first threshold, the power source control unit changes the state to another state where the power source of the main unit is the power supply unit and secondary battery.

Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

Abstract: A system and method for extending the USB VBUS power signal. A system for extending the USB VBUS power signal includes at least one PCA board. The system includes a USB host. The USB host outputs a new power signal compliant with USB VBUS power signal requirements. The VBUS signal may be connected to a voltage converter to change the voltage level to a desired enable signal for the voltage supply at the receiving end of the system. The VBUS signal may be connected to logic to change the polarity of the enable signal. The enable signal is routed across traces on the one or more PCA boards. A voltage supply is located on a PCA board and receives the enable signal. The enable signal causes the voltage supply to output a new power signal that is compliant with USB VBUS power signal requirements.

Abstract: Methods and apparatuses are provided for controlling power consumption in a processor (or computational unit thereof). The method comprises monitoring power consumption in a processor (or computational unit) and determining that the power consumption of the processor (or computational unit) exceeds a threshold. Thereafter, instruction issuance if modified (such as by slowing or ceasing instruction issuance) within the processor (or computational unit) until the power consumption is below the threshold. The apparatus comprises a power consumption monitor for determining when power consumption within the processor exceeds a threshold. Upon that determination, a scheduler begins modify instruction issuance to one or more execution units until the power consumption is below the threshold. The modification of instruction issuance can be to slow instruction issuance or cease instruction issuance for a time period or until the power consumption is below the threshold.

Abstract: In one aspect, a multi-port interface circuit applied to a playback apparatus which is able to switch among a plurality of input ports coupled to a plurality of source devices for playing back. Each input port has a receiver, the receiver including a front-end for receiving and processing a data stream from the source device and providing a data enable signal, and further including a content protection circuit for performing content protection according to the data enable signal. Each receiver records data enable information associated with the data enable signal of the data stream in an initial status. When one input port is selected, receivers of the other input ports operate in a power saving mode, the front-end circuits stop receiving the data stream, and the content protection circuit maintains operation according to a regenerated enable signal, which is regenerated according to the data enable information.

Abstract: A heat dissipating device is provided. The heat dissipating device includes at least one fan, a temperature detecting unit, a fan control unit, and a power consumption control unit. The temperature detecting unit detects a temperature inside the host. The fan control unit controls the rotating speed of the fan. The power consumption control unit calculates the total power consumption of the host, and outputs a control signal to the fan control unit according to the temperature inside the host and the total power consumption of the host, so as to adjust the rotating speed of the fan.

Abstract: Based on bounds of a period of reduced operation for a base device, a base device generates a power management message for transmission to a peripheral device. In the power management message, the base device inserts bounds of a period of reduced operation for the peripheral device. As a result, the periods of reduced operation conserve battery power in both devices and the two devices may reestablish a communications channel upon reaching the end of the period of reduced operation and resuming normal operations.

Abstract: An electronic apparatus is provided. A management hoard includes: a control section; a real-time clock that outputs data indicating current date and time to the control section; a memory that stores fiscal data including the data indicating the current date and time and fiscal information under the control of the control section; and a power source that supplies power to the real-time clock through a power supply path. A housing box includes a box main body and a cover. The housing box that houses the management board. When the cover is in a closed state, the power supply path is formed and the power is supplied to the real-time clock. When the cover is placed in an open state, the power supply path is shut off and the power supplied to the real-time clock is shut off.

Abstract: A power control method of a Central Processing Unit (CPU) in a multi-core system. The power control method includes acquiring current usage information of the CPU and system information, estimating a CPU usage of a next time interval based on the acquired current usage information, calibrating the estimated CPU usage of the next time interval based on the acquired system information, and determining a power control mode based on at least one of the acquired system information and the calibrated CPU usage of the next time interval.

Abstract: One embodiment disclosed relates to a system for power distribution to network devices. The system includes a plurality of network switches each having an internal power supply and a plurality of ports for connecting to the network devices and an external power supply having a plurality of output ports for connecting to the network switches. The external power supply communicates power available to the network switches. Each network switch determines amounts and priority levels of power for the network devices connected thereto, sums together the amounts at each priority level, determines additional amounts and priority levels of power required beyond the internal power supply capability, and sends a power request to the external power supply. The external power supply allocates power to the network switches depending on the power requests received.

Abstract: A method and system for managing a plug network based on appliance identification. In a basic implementation, when a new appliance is activated on the plug network, a power usage profile for the new appliance is computed based on current and voltage measurements. The new appliance is classified into an appliance class based on the power usage profile. A power management action message respecting the new appliance is generated based on the class and is outputted. By judiciously configuring the power management actions applicable to different appliance classes, a business can monitor which types of appliances are attached by employees to power outlets and/or set the terms and conditions under which such appliances operate.

Abstract: Embodiments of the present disclosure are directed to, among other things, managing power of one or more data storage devices. In some examples, a storage service may obtain a schedule associated with enabling different storage devices at different times. The storage service may also identify a request of a batch of requests for accessing the storage devices. In some cases, the storage service may also determine which storage device to activate based at least in part on the schedule and/or the request. Further, the storage service may manage power of a storage device based at least in part on the determination of which storage device to activate.

Abstract: A printing apparatus includes a first processor which is connected to a first memory and converts print data into an image data format based on a page description language, a second processor which is connected to a second memory and performs image processing for print data of the image data format to generate data of a format interpretable by a printing unit, and a communication control unit which externally receives print data and transfers the received print data to either the first memory or second memory based on a descriptor. The second processor determines the format of received print data. When the print data has the page description language format, the first memory is set as the transfer destination in the descriptor. When the print data has the image data format, the second memory is set as the transfer destination in the descriptor.

Abstract: The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.

Abstract: In one embodiment, a system for controlling an apparatus driven by a battery, the system operating by the battery, includes a computer to control the apparatus, a control signal circuit to send a signal from the computer to the apparatus so as to control the apparatus, and a nonvolatile memory circuit to store an operating state of the computer. The operating state includes a first operating state and a second operating state, the computer sets the apparatus to a low load state in accordance with the operating state and controls the apparatus when the computer is reset for shutdown due to a decrease of the residual quantity of the battery and is restarted for power-on.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: Methods and systems for digital control utilizing oversampling.

Abstract: An integrated circuit comprises logic circuitry, organized in a multi-level hierarchy of modules. The integrated circuit comprises multiple sensing circuits. In operation, each sensing circuit senses an instantaneous current consumption IC of a respective one of the modules that draws current entirely through that sensing circuit. The integrated circuit comprises a concealing circuit for each of the sensing circuits. In operation, the concealing circuit receives as input a voltage VC corresponding to the sensed instantaneous current consumption IC of its respective module, and the concealing circuit dissipates an instantaneous power PL such that an instantaneous power sum PTOTAL of the instantaneous power PL and the instantaneous power PC to be dissipated by its respective module is substantially independent of activity of its respective module.

Abstract: Power gating control and related circuitry for integrated circuits is described herein. A centralized power gating control circuit uses trigger circuits to control the on/off switching of power gating circuits distributed at different points in a chip, integrated circuit, module or block (collectively “IC”). The power gating circuits may include power gates partitioned for sleep and shutdown modes. The shutdown mode power gates may employ multi-level power gate architecture to minimize inrush current during power-up of the IC. Each level may be associated with or tied to a trigger circuit and activated based on a voltage level reaching the voltage threshold of the trigger circuit. The power gating control and related circuitry may be embedded in the IC.

Abstract: Embodiments of an apparatus, system and method are described for input/output (I/O) device assisted platform power management. An apparatus may comprise, for example, power management logic operative to receive idle duration information from one or more input/output (I/O) devices and to modify a power state for one or more components based on the idle information. Other embodiments are described and claimed.

Abstract: External jolts, such as those occurring during shipment, may inadvertently activate an electronic device. Such inadvertent activations may result in the electronic device entering an active mode during shipment, draining battery power. This document describes a power cut off mode that prevents inadvertent device activations and minimizes current consumption during shipment or storage of a device. This conserves battery power for operational use by the user.

Abstract: A motherboard includes an I/O chip, a south bridge chip, and a delay circuit. The I/O chip detects a standby voltage on the motherboard and outputs an indicating signal that indicates whether the standby voltage is at high level. The south bridge chip is connected to the I/O chip to receive the indicating signal. The delay circuit is connected to the I/O chip and the south bridge chip. The delay circuit delays the indicating signal before sending the indicating signal to the south bridge chip.

Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.

Abstract: Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.

Abstract: An image forming system includes uninterruptible power supply apparatuses; image processing apparatuses each connected to a corresponding one of the uninterruptible power supply apparatuses; and a management apparatus that issues, when a fault has occurred in one of the uninterruptible power supply apparatuses, a stop instruction to an image processing apparatus connected to the uninterruptible power supply apparatus. The image processing apparatuses include a first image processing apparatus that develops print information into image information, stores the developed image information, and outputs the stored image information to an image forming apparatus, and a second image processing apparatus that develops the print information into image information and outputs the developed image information to the first image processing apparatus.

Abstract: A hardware countermeasure for a cryptographic hardware module of a computing device is provided. The hardware countermeasure may include a noise-sample generator and a distributed buffer network co-located with the cryptographic module. The noise-sample generator may take as input data samples to be processed by the cryptographic hardware module and generate as output a non-Gaussian noise-sample for each of the input data samples. The distributed buffer network may take as input the non-Gaussian noise-samples and generate a non-Gaussian noise output corresponding to each of the non-Gaussian noise-samples.

Abstract: A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Abstract: Embodiments in accordance with the present invention provide devices and methods for operating two memory cards. In one embodiment, an electronic device includes a host controller, a first socket in communication with the host controller, for receiving a first memory card and a second socket, and a second socket in communication with the host controller, for receiving a second memory card. The physical pin arrangement of the second socket is in an order reversed from the physical pin arrangement of the first socket. The host controller transmits power to the first memory card and cuts off power to the second memory card during a first time period, and cuts off power to the first memory card and transmits power to the second memory card during a second time period. The first socket and the second socket transmit and receive same set of data signals.

Abstract: A microprocessor includes two or more processing cores each configured to determine, at each of succeeding instances in time, an amount of energy consumed by the microprocessor during a period preceding the instance in time. The period is predetermined. Each core also operates at a frequency above a predetermined frequency in response to determining the amount of energy consumed is less than a predetermined amount of energy. All of the cores may operate above the predetermined frequency simultaneously until one of the cores determines the microprocessor has consumed more than the predetermined amount of energy during the period preceding the instance in time. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined period without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the cores to operate.

Abstract: A host device of dual power supply includes a chassis, a motherboard disposed in the chassis, at least one storage unit electrically coupled to the motherboard, two power supplies electrically coupled to the motherboard and the storage unit for supplying power to the motherboard and the storage unit, and a control unit electrically coupled to the motherboard, the storage unit and the power supply. When a boot signal is received by the control unit, one of the power supplies provides a voltage required by the storage unit at the moment of booting and during operations that follow, and the other power supply is driven to provide a voltage required by the motherboard at the moment of booting and during operations that follow.

Abstract: There is provided an electric power supply device including an electric power supply portion that continuously supplies, to another device with which an agreement about electric power supply has been made, electric power agreed with the other device until one of a time at which the agreement becomes unnecessary and a time determined in advance, the electric power being supplied via a bus line formed by a pair of conductors, and an information communication portion that transmits and receives an information signal indicating information to and from the other device to which the electric power supply portion supplies the electric power, such that the information signal is superimposed on the electric power supplied from the electric power supply portion. The electric power supply portion determines whether to change the electric power to be supplied, in accordance with one of connection of a new device to the bus line and disconnection of the new device from the bus line.

Abstract: A printing system has a printer device including a communication control portion and a print engine carrying out a print processing, and an information processing device connected to the printer device as external equipment via a USB interface, the printer device being connected to external equipment by the communication function of the communication control portion via a USB interface, and inputting the electric power of the print engine by a print request from the external equipment to perform the print processing in a printer standby state in which the electric power of the print engine is reduced while maintaining the communication function of the communication control portion.

Abstract: Various embodiments of methods and systems for controlling and/or managing thermal energy generation on a portable computing device are disclosed. Data discarded from one or more processing core registers may be monitored and analyzed to deduce individual workloads that have been processed by each of the cores over a unit of time. From the deduced workloads, the power consumed by each of the cores over the unit of time in order to process the workload can be calculated. Subsequently, a time dependent power density map can be created which reflects a historical and near real time power consumption for each core. Advantageously, because power consumption can be correlated to thermal energy generation, the TDPD map can be leveraged to identify thermal aggressors for targeted, fine grained application of thermal mitigation techniques. In some embodiments, workloads may be reallocated from the identified thermal aggressors to the identified underutilized processing components.

Abstract: Disclosed is a storage system architecture. An Environmental service module (ESM) is coupled to one or more array controllers. The ESM is configured with a central processing unit and one or more assist functions. The assist functions may include nonvolatile memory. This nonvolatile memory may be used for write caching, mirroring data, and/or configuration data. The assist functions, or the ESM, may be controlled by the array controllers using SCSI or RDMA commands.

Abstract: A readily scalable modular progammable integrated circuit (IC) with improved power management is provided. An IC is described that contains one master controller module and a multiplicity of slave modules that include power-supplying functions, battery management functions, and analog and digital input-output functions. The master controller module configures the slave modules by writing data to the slave modules' configuration registers through the communication network. Each module contains a multiplicity of configuration registers that determine the module's operational and parametric characteristics. Programmability is achieved by configuring the modules to respond to appropriate signals on the configurable interconnection network.

Abstract: A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.

Abstract: An automatic banking machine operates responsive to data read from data bearing records corresponding to authorized user or financial account data. The machine includes a card reader for reading data from user cards. The automated banking machine causes financial transfers related to financial accounts that correspond to data read from user cards. The automated banking machine also includes devices that control the supply of power to included devices to avoid exceeding power supply capacity.