Multiple Or Variable Intervals Or Frequencies Patents (Class 713/501)
  • Patent number: 11011116
    Abstract: A display device comprises a display panel and a timing controller. The timing controller supplies gate timing signals to a gate driver as a sequence of clock pulses that sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and for receiving a sensing signal during the vertical blanking intervals. The clock pulses have a first timing during the vertical active periods and the clock pulses have a second timing during the vertical blanking intervals in which the second timing is different than the first timing.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 18, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Changho An, Byungil Kim
  • Patent number: 10998905
    Abstract: A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Soo Young Jang, Geun Il Lee
  • Patent number: 10915154
    Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 9, 2021
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: George Elias, Ido Bourstein, Lior Abramovsky, Lavi Koch
  • Patent number: 10846252
    Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: November 24, 2020
    Assignee: RAMBUS, INC.
    Inventors: Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright
  • Patent number: 10811057
    Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more command-and-address (CA) input signals. The memory device also includes a memory cell region for storing information in a plurality of memory cells. A centralized CA interface region including two or more CA input circuits operably coupled to the two or more CA input signals. The centralized CA interface region is positioned between the bonding pad region and the memory cell region in a layout arrangement with the two or more CA input circuits neighboring each other in a compact region such that clock routing to the two or more CA input circuits is substantially reduced.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kazuhiro Yoshida, Kumiko Ishii
  • Patent number: 10778234
    Abstract: A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 15, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hua Li, Yan Gao, Sheng Ma
  • Patent number: 10732689
    Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy David Anderson, Duc Quang Bui
  • Patent number: 10725509
    Abstract: A method includes executing an initialization routine upon startup of a processor. The method includes executing a benchmark program during the initialization routine after the startup. The method further includes comparing an amount of time for execution of the benchmark program to a reference time to determine if the processor has slowed due to thermal degradation of heat removal components for the processor.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: July 28, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chin-Yu Wang, Sheng-Lung Liao
  • Patent number: 10659020
    Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jean Nicolai, Albert Martinez
  • Patent number: 10492842
    Abstract: A method of using a cryotherapeutic system in accordance with a particular embodiment includes advancing an elongate shaft of a catheter toward a treatment location within a body lumen of a human patient and directing a flow of refrigerant toward a cryotherapeutic element at a distal end portion of the shaft. The directed refrigerant is expanded to cause cooling within a balloon of the cryotherapeutic element. The pressure within the balloon is monitored and its rate of change calculated. The rate of change is then processed using different feedback loops during different monitoring windows of a treatment cycle. The individual feedback loops include an upper and a lower threshold and are configured to cause the flow of refrigerant to the cryotherapeutic element to stop if the rate of change falls outside a range between the upper and the lower threshold.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 3, 2019
    Assignee: MEDTRONIC ARDIAN LUXEMBOURG S.A.R.L.
    Inventors: Micheal Moriarty, Brian Kelly
  • Patent number: 10429909
    Abstract: An apparatus and method thermally manage a high performance computing system having a plurality of nodes with microprocessors. To that end, the apparatus and method monitor the temperature of at least one of a) the environment of the high performance computing system and b) at least a portion of the high performance computing system. In response, the apparatus and method control the processing speed of at least one of the microprocessors on at least one of the plurality of nodes as a function of at least one of the monitored temperatures.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 1, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Eng Lim Goh, Patrick Donlin, Andrew Warner
  • Patent number: 10419198
    Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: September 17, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Paul Rowland
  • Patent number: 10331194
    Abstract: A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 25, 2019
    Assignee: PACT XPP Schweiz AG
    Inventors: Martin Vorbach, Volker Baumgarte
  • Patent number: 10331195
    Abstract: In some aspects, a method for adjusting an operating frequency of a memory controller is provided, wherein a graphics processing unit (GPU) accesses a memory via the memory controller. The method includes monitoring activity of the GPU to determine an active time of the GPU, comparing the determined active time with an active threshold, and, if the determined active time is greater than the active threshold, increasing the operating frequency of the memory controller.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Milena Vratonjic, Harmander Singh, Gautam Kumar, Mohamed Roumi, Kenneth Marvin Gainey, Ashish Bajaj
  • Patent number: 10320393
    Abstract: Methods and systems for timing analysis and closure during logic synthesis of synchronous digital circuitry are provided, which may be used to prevent timing conflicts in logic designs that may have data transfers between regions with substantial clock skew. In programmable logic devices having hardened circuitry and programmable fabric, data transfers between memory elements in hardened circuitry and programmable fabric may be subject to substantial clock skews and unknown latencies. Embodiments may employ pre-calculated latencies that may be stored in a file and/or a database, and dynamically retrieved during timing synthesis to determine multicycle constraints to mitigate latencies. Embodiments may employ destination multicycle constraints, which use as reference the clock waveforms delayed due to latency.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 11, 2019
    Assignee: INTEL CORPORATION
    Inventors: Navid Azizi, Aditi Kumaraswamy, Emily Alexandra Ng
  • Patent number: 10317976
    Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Russell J. Fenger
  • Patent number: 10303204
    Abstract: A clock diagnostic apparatus repeatedly acquires clock values at constant intervals by software. A clock diagnostic unit (103) selects, from among the clock values which are acquired by the software, two clock values having a gap between acquisition timings, the gap being a predetermined time period which is sufficiently large compared to jitter which occurs at a time of acquiring a clock value by the software. The clock diagnostic unit (103) calculates a difference between the two clock values selected.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 28, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Ryoya Ichioka
  • Patent number: 10304517
    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: May 28, 2019
    Assignee: Rambus, Inc.
    Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
  • Patent number: 10296069
    Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 21, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Stewart, Dexter Chun
  • Patent number: 10254814
    Abstract: Techniques for reducing power consumption of a storage controller are provided. An example method includes determining a back-end bandwidth of a storage system, wherein the back-end of the storage system includes a storage drive communicatively coupled to a storage controller. The method also includes determining a front-end bandwidth of the storage system, wherein the front-end of the storage system includes a front-end bus coupling the storage controller to a host. The method also includes computing a target back-end memory bandwidth based on the back-end bandwidth and computing a target front-end memory bandwidth based on the front-end bandwidth. The method also includes reducing power consumption of the storage controller by reducing a clock frequency of a memory device of the storage controller based on the greater of the target back-end memory bandwidth and the target front-end memory bandwidth.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 9, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: James Alexander Fuxa, Michelle Geppert, Yovita Iskandar
  • Patent number: 10243568
    Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromichi Yamada, Akihiro Yamate, Hitoshi Suzuki, Yoichi Yuyama, Teppei Hirotsu
  • Patent number: 10234920
    Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Jorge P. Rodriguez
  • Patent number: 10198063
    Abstract: A power regulation system for a read channel of a data storage assembly includes a first voltage regulator for supplying power to the front-end decoder and a second voltage regulator for supplying power to the back-end codec. The second voltage regulator may conserve power reduce supply voltage to the back-end codec when the codec operates at a lower sampling frequency. The second voltage regulator may additionally increase supply voltage to the back-end codec in conjunction with an increase in sampling frequency. The system may additionally include a third voltage regulator for supplying a memory structure of the read channel with only the minimum required operating voltage to prevent leakage power.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 5, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Shaohua Yang, Kapil Gaba
  • Patent number: 10173418
    Abstract: A transfer data generator creates transfer data that suppresses an increase in radiation noise generated when the transfer data is transferred to an ink head. The transfer data generator creates transfer data including transfer printing image data to be transferred to the ink head, and a transfer clock signal. The transfer data generator includes a clock signal creation processor that generates a pulse period of at least one pulse of a plurality of pulses of the reference clock signal different from each of pulse periods of the other pulses to generate the transfer clock signal from the reference clock signal, and a printing image data creation processor that adjusts the reference printing image data so as to correspond to the transfer clock signal to generate transfer printing image data.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 8, 2019
    Assignee: ROLAND DG CORPORATION
    Inventor: Hiro Hagimori
  • Patent number: 10120408
    Abstract: A system and method for controlling clock generation. A system includes a processor configured to execute instructions retrieved from memory, and a clock generation system coupled to the processor. The clock generation system is configured to generate a clock signal that the processor applies to execute the instructions. The clock generation system includes a plurality of configuration registers and selection circuitry. Each of the configuration registers includes fields that control a frequency of the clock signal. The selection circuitry selects which of the plurality of configuration registers determines the frequency at a given time.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: November 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joerg Harald Hans Jochen Schreiner, Marcus Herzog
  • Patent number: 10101795
    Abstract: The present disclosure relates to a method for dynamically optimizing power consumption in a System-on-Chip (SoC). The method comprises receiving at least one interrupt signal from a peripheral controller. The method further comprises switching clock frequency of the peripheral controller to a lower clock frequency than a normal operating clock frequency upon receiving the at least one interrupt. The method further comprises providing the lower clock frequency than the normal operating clock frequency to the peripheral controller for dynamically optimizing the power consumption of the SoC.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 16, 2018
    Assignee: Wipro Limited
    Inventor: Radha Krishna Moorthy Sadhu
  • Patent number: 10083084
    Abstract: A method of error detection during a booting process of a computer system includes: for each of setting variables of a BIOS program, determining whether or not a respective one of stored values corresponding to the setting variable is in a respective one of value ranges corresponding to the setting variable according to a variable range comparison table; and when it is determined that for at least one of the setting variables, the stored value corresponding thereto is not in the respective one of the value ranges, updating, according to a variable definition file, the at least one of the setting variables using one of preset default values corresponding to the at least one of the setting variables.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 25, 2018
    Assignee: Mitac Computing Technology Corporation
    Inventor: Ming-Hao Chang
  • Patent number: 10074115
    Abstract: A subscription management service utilizes a timer service to maintain timers corresponding to subscription events. The subscription management service exposes an interface through which clients can define new subscriptions that are then created and managed by the subscription management service. The subscription management service can charge subscribers on an appropriate billing period, and cancel or automatically renew subscriptions at the end of a contract period. The subscription management service can also provide notifications to clients, to subscribers, and/or to other components. The subscription management service might also perform other types of actions with regard to the subscriptions on behalf of the clients. The timer service receives payloads from clients, such as the subscription management service, and provides the payloads back to the clients at a specified time. The timer service might also utilize a jitter threshold to compute the time at which payloads should be provided to clients.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: September 11, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeremy Stephen Hynoski, Eugene Chang, Andygibb Halim, Hector Cura
  • Patent number: 10042401
    Abstract: A system and method for thermal management of a memory device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached. The thermal control module may then begin tracking memory thermals or initiate thermal management operations based on the signal and history of memory device temperatures over time.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: August 7, 2018
    Assignee: INTEL CORPORATION
    Inventor: David A. Wyatt
  • Patent number: 10013371
    Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 3, 2018
    Assignee: Google LLC
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Patent number: 9996102
    Abstract: This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: June 12, 2018
    Assignee: NXP USA, Inc.
    Inventor: Martin Mienkina
  • Patent number: 9952650
    Abstract: A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: April 24, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Wei Chen, Tongzeng Yang, Anthony Mazzola
  • Patent number: 9918147
    Abstract: A transmission apparatus includes: a plurality of first devices; and a second device configured to output a data signal shared by the plurality of first devices and respective first clock signals to each of the plurality of first devices, and to control the plurality of first devices individually based on the respective first clock signals.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: March 13, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Shota Shinohara
  • Patent number: 9910808
    Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 6, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Blaine D. Gaither, Robert J. Brooks, Benjamin D. Osecky, Kathryn A. Evertson, Andrew R. Wheeler, David Fisk
  • Patent number: 9912763
    Abstract: An improved system and method for communicating Presence Information. According to various embodiments, the sequence of actions undertaken in established Presence procedures are changed, and enhancements are also provided for Watcher 5 information notifications. Upon the initiation of a Presence Service, the Presence Source starts publishing Presence Information about a Presentity using a soft-state approach. Instead of having publication occur first, the Presence Source makes a subscription for the Watcher information first or simply waits until the Presence Server contacts the Presence Source. As a result, publication occurs only when there is a demand therefor.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: March 6, 2018
    Assignee: Nokia Technologies Oy
    Inventors: Krisztian Kiss, Miraj Mostafa
  • Patent number: 9911478
    Abstract: In some aspects, a calibration method includes performing a write/read test for each one of multiple combinations of write/read delay settings, wherein each one of the multiple combinations of write/read delay settings includes one of a plurality of write delay settings of a first delay device and one of a plurality of read delay settings of a second delay device. The method also includes obtaining test results for the write/read tests, determining a pass region based on the test results, determining a center of the pass region, and selecting one of the multiple combinations of write/read settings based on the center of the pass region.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 6, 2018
    Assignee: Ikanos Communications, Inc.
    Inventors: Subash Babu Peddu, Venkatramana Kamasani, Vijay Shikhamani Kalakotla, Daniel Cunza
  • Patent number: 9904582
    Abstract: An apparatus includes a calculation processing unit configured to perform a calculation in the electronic device, a device manager configured to controls a speed of the calculation processing unit and output load factor information, one or more user-level application programs with a respective load factor limit, configured to request for load factor limit information of the calculation processing unit and calculation of a load with a load factor limit, and a service quality manager configured to receive the load factor limit information and the load with the load factor limit from the user-level application programs with the load factor limit, receive load factor information of the calculation processing unit from the device manager, generate a calculation parameter so that a load factor of the calculation processing unit is within the load factor limit information, and output the load with the load factor limit and the generated calculation parameter.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Uison Yoon, Rakie Kim, Jijoong Moon, Cheolyong Jeon
  • Patent number: 9905262
    Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 27, 2018
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jonathan Cottinet, Jean Claude Bini
  • Patent number: 9841804
    Abstract: A technique includes clocking a processor; and in response to the processor providing a signal indicating that the processor is transitioning between a first power state that is associated with a first power consumption and a second power state that is associated with a second power consumption different than the first power consumption, changing a frequency of the clocking.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: December 12, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Subrata Roy, Xiaohui Wang
  • Patent number: 9823673
    Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.
    Type: Grant
    Filed: May 18, 2014
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hee Jun Park, Young Hoon Kang, Ronald Frank Alton, Christopher Lee Medrano, Jon James Anderson
  • Patent number: 9804661
    Abstract: A power control method of an electronic device is provided. The electronic device transmits power change information containing a power control value of an application to another electronic device, and receives and stores power control information about the application transmitted from the another electronic device. If a power level of the electronic device is lower than a predetermined power change level when the application is executed, the electronic device executes the application with power control data of the application in the power control information stored in the electronic device.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sangwon Chae, Hyoungil Kim, Jungeun Lee
  • Patent number: 9729156
    Abstract: A device for supplying an electronic circuit with a clock signal having a dock frequency includes a frequency actuator that generates the clock signal in accordance with a frequency setting according to a regulation mechanism. A control module selectively applies to the frequency actuator a first frequency setting or a second frequency setting that is higher than the first setting. An adaptation module modifies the regulation mechanism in accordance with the applied setting.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 8, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Diego Puschini Pascual, Suzanne Lesecq
  • Patent number: 9720486
    Abstract: A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 1, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Angel E. Socarras, Fei Guo
  • Patent number: 9678807
    Abstract: Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Lihu Rappoport
  • Patent number: 9614703
    Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammed Mizanur Rahman, Thomas Clark Bryan, Jacob Stephen Schneider, LuVerne Ray Peterson, Tin Tin Wee, Alvin Leng Sun Loke
  • Patent number: 9568941
    Abstract: A memory controller includes a clock scaler, a bus component and a level monitor. The clock scaler is configured to receive a first clock signal and configured to generate a second clock signal based on the first clock signal, first and second frequency control signals. A frequency of the second clock signal may increase based on the first frequency control signal and decrease based on the second frequency control signal. The bus component may operate based on the second clock signal and generate a level signal corresponding to a current operating state of the bus component. The level monitor may generate the first and second frequency control signals based on the level signal, a first threshold value, a second threshold value, a first reference time, and a second reference time.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jin-Su Jung
  • Patent number: 9552047
    Abstract: A multiprocessor that that provides for adjusting the clock frequency for at least some data processing units at runtime and a voltage supply adapted to supply higher supply voltages for data processing at higher clock frequencies.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 24, 2017
    Assignee: PACT XPP TECHNOLOGIES AG
    Inventors: Martin Vorbach, Volker Baumgarte
  • Patent number: 9548666
    Abstract: A circuit for use in a switched mode power supply comprising includes an integrated circuit, a transformer, a capacitor, a low voltage circuit and a current limiting resistor. The IC jitters the switching frequency of the switch based on a bias voltage of the integrated circuit. The IC also includes a current source configured to supply current for operation of the switching regulator when insufficient current is available from the bias input pin. The transformer includes primary, secondary and auxiliary windings. The primary winding receives a rectified line voltage and is coupled to the switch. The capacitor is coupled between the bias input pin and ground. The low voltage circuit is coupled to the auxiliary winding, and provides current to the bias input pin. The current limiting resistor limits current produced by the low voltage circuit to less than that required for operation of the IC.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: January 17, 2017
    Assignee: Landis+Gyr Inc.
    Inventors: Thomas G. Block, Matt E. Kraus
  • Patent number: 9490003
    Abstract: A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventor: Kenneth D. Shoemaker
  • Patent number: 9471088
    Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, Larisa Novakovsky, George Leifman, Lev Makovsky, Ariel Sabba, Niv Tokman