Abstract: In one embodiment, the present invention includes a method for determining a scaling factor between a frequency of a first processor and a frequency of a second processor after a guest software is migrated from first processor to the second processor, and executing the guest software on the second processor using a virtual counter based on a physical counter of the second processor and the scaling factor. Other embodiments are described and claimed.

Abstract: Disclosed is an image processing apparatus, which can differently set a clock ratio according to a use rate of a CPU, and a control method thereof. The image processing apparatus may include a receiver to receive a print command from a user terminal, and a controller to differently set a clock ratio according to a use rate of the CPU based on the print command.

Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).

Abstract: Each of a plurality of master devices outputs a speed grade signal indicating a data transfer speed with a data transfer request. An arbiter arbitrates transfer requests and speed grade signals from the plurality of master devices. A clock enable generation circuit generates a clock enable signal with a varying ratio of a valid level according to the speed grade signal arbitrated by the arbiter. A slave device operates upon receiving a clock signal when the clock enable signal is at the valid level, and transfers data according to the transfer request arbitrated by the arbiter. Accordingly, the frequency of the clock signal which causes the slave device to operate may be changed for each transfer request, and a fine control of the power of the slave device may be easily performed. As a result, power consumption of the data processing system may be finely controlled.

Abstract: A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.

Abstract: Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.

Abstract: A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses.

Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.

Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

Abstract: An electronic apparatus input and/or output a signal from and/or an external apparatus. The electronic apparatus includes: a clock section in which a frequency is set and which gives a clock signal having the set frequency; an input-output section which inputs and/or outputs the signal according to the clock signal given from the clock section; a frequency detecting section which detects a frequency of a signal given from the external apparatus; and a frequency setting section which determines the frequency of the clock signal based on the frequency detected by the frequency detecting section, and sets the frequency in the clock section. Since the frequency of the clock signal is automatically set based on the frequency given from the external apparatus, it is possible to diminish a cumbersome maintenance work or reduce the cost.

Abstract: The present invention discloses a single-wire transmission interface, and a method of transmission through single-wire. The method comprises: providing a single-wire signal through a single-wire; and transmitting information only in a transmission period defined by a fixed first time period starting from one of a rising or a falling edge of the single-wire signal.

Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.

Abstract: Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.

Abstract: A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.

Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.

Abstract: Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to calculating a clock rate for one or more of the processor cores in the multi-core processor. One example method may include determining a first estimated workload for a first processor core and a second estimated workload for a second processor core within a scheduling interval in a periodic scheduling environment. In addition, a first clock rate for the first processor core may be calculated based on one or more of the first estimated workload, a maximum clock rate supported by the multi-core processor and/or the scheduling interval. Similarly, a second clock rate for the second processor core may also be calculated based on one or more of the second estimated workload, the maximum clock rate, and/or the scheduling interval.

Abstract: An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer clock; and a second semiconductor device having data input terminals which receive the transfer data, a clock input terminal adapted to receive the transfer clock, second data storage sections associated with the data input terminals respectively to store input data, and selection sections associated with the second data storage sections respectively to select either the transfer data or data shifted and output to the associated second data storage section in a first series circuit which is formed by connecting the second data storage sections in series, the selection sections supplying the selected data to the associated second data storage section.

Abstract: Disclosed is a dark current cutoff system and method for a vehicle junction. In particular, a controller is configured to monitor signal input through a CAN communication module to determine when other modules in the vehicle are in a sleep mode, cut off battery power to a load device by turning off a switching element when the controller determines that the other modules in the vehicle are in sleep mode, and forcibly maintains an off state of the switching element for a set period time after the power has been cut, regardless of signal input through the CAN communication module.

Abstract: Techniques are generally described related to management of power consumption for a processor. One example method may include identifying a target operating constraint and a first operating parameter; determining a second operating parameter based on the target operating constraint and the first operating parameter; estimating an actual operating constraint; comparing the target operating constraint and the actual operating constraint; and setting up the first operating parameter and the second operating parameter of the processor based on a comparison of the target operating constraint and the actual operating constraint, wherein the target operating constraint is not a worst-case operating constraint. Other examples of methods, systems, and computer programs related to managing power consumption for a processor are also contemplated.

Abstract: A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.

Abstract: An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal.

Abstract: An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.

Abstract: Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Abstract: An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval.

Abstract: A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms.

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract: A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals.

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract: A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock source. In one version, a memory controller configures a masking circuit to either allow a clock signal to the clock input or to mask the clock input from a bidirectional clock bus. The masking circuit may comprise a storage element and a gate, as an example.

Abstract: An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service. An associated method for performing timer management regarding a system timer scheduler service is also provided, and can be applied to the apparatus. In particular, the apparatus and the method can give considerations to both run-time power consumption and sleep mode power consumption. For example, the hardware-based OS timer can support an event-based OS timer scheduler to save the run-time power consumption. In another example, the hardware-based OS timer can support timer alignment in accordance with modulator/demodulator (modem) activities to minimize the sleep mode power consumption.

Abstract: A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit.

Abstract: Multi-level encoded data transfer is disclosed. 2n bits may be encoded in a data signal each half clock cycle. For example, four bits may be transferred each clock cycle. Prior to data transfer, each data line may have two bits ready to be encoded. The two bits may be encoded to one of four different data states. The clock may be divided into four intervals for each half clock cycle, with each interval corresponding to one of the four data states. The two bits may be encoded into the data signal based on the interval that corresponds to the data state. As one example, the data signal could transition during the interval that corresponds to the data state for the two bits. This encoding may be repeated for two other bits for the other half of the clock cycle. Thus, QDR or some other data rate may be achieved.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may be used to pass data between the two clock domains. In one embodiment, a set of storage devices is connected in a circular buffer arrangement. A first subset of the storage devices is clocked by a signal from a first clock domain and a second subset of the flip flops is clocked by a signal taken from a second clock domain. Respective output circuits generate enable signals to be used for transferring data between domains. In some implementations, a pulse is stored and registered by at least two of the storage devices in the first domain before being passed to the devices in the second domain. In other embodiments, the output circuits may include a pair of D flip flops, each clocked by a respective one of the first or second domain signals.

Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract: A processor includes a plurality of processing units. A plurality of first arbitration units each arbitrate request signals output from at least two of the processing units to generate a first arbitration signal. A second arbitration unit arbitrates first arbitration signals output from the first arbitration units to generate a second arbitration signal. A plurality of clock controllers, arranged in correspondence with the first arbitration units, each generate a clock signal supplied to a corresponding first arbitration unit and the processing units coupled to the corresponding first arbitration unit. A control unit determines whether or not to operate each processing unit in accordance with an operation state of the processor and generates control information according to the determination result. Each of the clock controllers supplies or stops the clock signal or changes a frequency of the clock signal in accordance with the control information.

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The skipped cycle clock signals may be changed by the computing system during operation of the system by altering masks applied to a global clock signal. However, the flexibility to alter various skipped cycle clock signals may introduce noise or signal disruptions within the system. Thus, the present disclosure may also involve an apparatus and/or method for managing the altering of the clock cycle skipping masks to manage the voltage noise introduced into the system by the adjustment of the operating frequency of the portions of the system. In one embodiment, the method includes prioritizing or otherwise ordering the bits of the masks applied to the global clock signal to attempt to prevent similar bits from being altered simultaneously.

Abstract: A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: The invention relates to an improved backplane communication system. In one embodiment this is accomplished by a central data processing card including at least one master central card and a plurality of slave central card, wherein each master central card and the slave central card having a first SerDes (serializer-deserializer), a first clock and a first faster local clock, a line card including a second SerDes (serializer-deserializer), a clock selection module and a second faster local clock and a serial communication channel coupling the central data processing card and the line card, wherein the master central card uses the first faster local clock to transmits the data at a rate higher than actually required, wherein the transmitted data includes a stuff data to adjust to the link data rate between the central data processing card and line card.

Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.

Abstract: An image sensing apparatus, having an image sensor for sensing an image of an object and an analog-digital converter which operates at a predetermined frequency and converts an analog signal read from the image sensor to a digital signal, controls the relationship between a phase of the analog signal read from the image sensor and a phase of a timing signal for operating the analog-digital converter in accordance with the peripheral condition.