Clock, Pulse, Or Timing Signal Generation Or Analysis Patents (Class 713/500)
  • Patent number: 10810114
    Abstract: A method for testing autonomous reconfiguration logic for an electromechanical actuator includes executing a plurality of test cases against a computer model configured and operable to implement autonomous reconfiguration logic for an electromechanical actuator including a plurality of electromechanical motors to generate a first set of test results. The method further includes executing the plurality of test cases against a programmable logic device configured and operable to implement the autonomous reconfiguration logic for the electromechanical actuator to generate a second set of test results and comparing the first set of test results to the second set of test results.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Hamilton Sundstrand Corporation
    Inventors: David F. Dickie, Steven A. Avritch, Peter E. Gardow
  • Patent number: 10802534
    Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Patent number: 10771231
    Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Rambus Inc.
    Inventors: Bret G. Stott, Craig E. Hampel, Frederick A. Ware
  • Patent number: 10769038
    Abstract: Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal, the slave counter circuitry having associated fault detection circuitry; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry, the master counter circuitry being configured to provide via the synchronisation connection: initialisation data at an initialisation operation; and fault detection data at a fault detection operation; the initialisation data and subsequent fault detection data each representing respective indications of a state of the master count signal; the slave counter circuitry being configured, during an initialisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the initialisation data provided by the master counter circuitry; an
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventors: Peter Uttley, Kar Lik Kasim Wong
  • Patent number: 10762947
    Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Keon Lee, Kyung-Soo Ha, Hyong-Ryol Hwang
  • Patent number: 10732699
    Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert Milstrey, Amit K. Srivastava
  • Patent number: 10734043
    Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Ju Kim, Dong-Seok Kang, Hye Jung Kwon, Byungchul Kim, Seungjun Bae
  • Patent number: 10707853
    Abstract: An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jinn-Yeh Chien
  • Patent number: 10705990
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 7, 2020
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • Patent number: 10705557
    Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: ZhenQi Chen, Jianguo Yao, Scott Davenport, Helena Deirdre O'Shea, Reza Mohammadpourrad
  • Patent number: 10686605
    Abstract: Technologies for providing shared immutable code among untrusting domains are provided. The untrusting domains may be cryptographically separated within a cloud computing service or environment. The shared immutable code may be a shared virtual machine monitor (sVMM) that is setup by system software to indicate that the sVMM code pages need integrity alone and should be protected with an integrity key associated with individual domains. This indication may be stored in page tables and carried over the memory bus to a cryptographic engine. The cryptographic engine may use this indication to protect the integrity of data before storing the data to memory. In order to ensure cryptographic isolation, integrity values may be generated using a domain-specific key ensuring that an attempt to modify the code by one domain is detected by a different domain. Other embodiments are described herein and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, David M. Durham
  • Patent number: 10642861
    Abstract: A method, apparatus, and system for multi-instance redo apply is provided for standby databases. A multi-instance primary database generates a plurality of redo records, which are received and applied by a physical standby running a multi-instance standby database. Each standby instance runs a set of processes that utilize non-blocking, single-task threads for high parallelism. At each standby instance for the multi-instance redo, the plurality of redo records are merged into a stream from one or more redo strands in logical time order, distributed to standby instances according to determined apply slave processes using an intelligent workload distribution function, remerged after receiving updates from remote instances, and applied in logical time order by the apply slave processes. Redo apply progress is tracked at each instance locally and also globally, allowing a consistent query logical time to be maintained and published to service database read query requests concurrently with the redo apply.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 5, 2020
    Assignee: Oracle International Corporation
    Inventors: Amrish Srivastava, Yunrui Li, Mahesh Baburao Girkar
  • Patent number: 10630396
    Abstract: A mobile industry processor interface MIPI clock frequency configuration method and apparatus are provided. When a radio frequency band used by a device on which an MIPI is located changes, an MIPI clock frequency is determined according to radio frequency band information, where the radio frequency band information includes the radio frequency band currently used by the device, and the determined MIPI clock frequency causes no interference to the radio frequency band currently used by the device; and an MIPI clock frequency of the device is configured as the determined MIPI clock frequency. According to the technical solutions in the present invention, when a radio frequency band of a device changes, an MIPI clock frequency causes no interference to communication of the device, thereby improving communication quality and stability of the device.
    Type: Grant
    Filed: April 15, 2018
    Date of Patent: April 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xinglong Zhuang, Tao Ma, Zhimin Tang
  • Patent number: 10631047
    Abstract: A browser-based video editor is configured to allow a user to create a composition schema having multimedia layers, including video, audio, and graphic and text layers. The composition schema may be transmitted to a remote service that employs a rendering engine to play back the composition schema and align the clocks for each respective multimedia layer into a single video representation. A master clock object is employed to sync the clocks while also checking a series of properties with each multimedia layer to comport the multimedia layers with an interval-based master clock. The composition schema is recorded using FFmpeg (Fast Forward Moving Picture Experts Group) to create a video representation for user consumption, such as an MP4 (Motion Pictures Experts Group 4) formatted file.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 21, 2020
    Assignee: POND5 INC.
    Inventors: Mathieu Frederic Welche, Hugo Valentín Elías García, Taylor James McMonigle, Pier Stabilini, Nicola Onassis
  • Patent number: 10579390
    Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.
    Type: Grant
    Filed: December 3, 2017
    Date of Patent: March 3, 2020
    Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD.
    Inventors: Yoav Etsion, Dani Voitsechov
  • Patent number: 10579492
    Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan Combs, Jason Brandt
  • Patent number: 10565335
    Abstract: An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: February 18, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10564666
    Abstract: Clock-controlled circuitry organised into at least first and second clock domains, the first clock domain configured to operate based on a first clock signal and the second clock domain configured to operate based on a second clock signal, wherein: the first clock domain comprises a first signal generator operable to generate a first repetitive signal synchronised to the first clock signal; the second clock domain comprises a second signal generator operable to generate a second repetitive signal synchronised to the second clock signal; the first signal generator is operable, when operating in master mode, to output to the second signal generator a first synchronisation signal indicative of a phase of the first repetitive signal; and the second signal generator is operable, when operating in slave mode, to: set a timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is set to have a phase relationship with the
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 18, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Ross Morgan, Shantanu Shrikant Nalage
  • Patent number: 10552115
    Abstract: An audio/video (A/V) hub that calculates an estimated location is described. In particular, the A/V hub may calculate an estimated location of a listener relative to electronic devices (such as electronic devices that include speakers) in an environment that includes the A/V hub and the electronic devices based on: communication with another electronic device; sound measurements in the environment; and/or time-of-flight measurements. Then, the A/V hub may transmit, to the electronic devices, one or more frames that include audio content and playback timing information, which may specify playback times when the electronic devices are to playback the audio content based on the estimated location. Moreover, the playback times of the electronic devices may have a temporal relationship so that the playback of the audio content by the electronic devices is coordinated.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: February 4, 2020
    Assignee: Eva Automation, Inc.
    Inventors: Gaylord Yu, Steven Stupp
  • Patent number: 10541803
    Abstract: Aspects of the disclosed technology provide a method comprising executing different first and second instructions a first and second number of times, respectively, in repeated alternations. The method further comprises measuring spectra of signals emanating as a result of the processor executing the first and second instructions. The method also includes analyzing data indicative of the spectra of the signals to determine side-channel candidate side-band pairs that each have a lower and upper sideband at first and second frequencies, respectively, that are separated by approximately twice the respective alternation frequency. Finally, the method includes identifying a side-channel carrier frequency at a frequency approximately at a midpoint between a side-channel candidate side-band pair's first and second frequency.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 21, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Milos Prvulovic, Nina Basta, Robert Callan, Alenka Zajic
  • Patent number: 10534555
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10530375
    Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Yipeng Wang, Kee Hian Tan, Stanley Y. Chen, Yohan Frans
  • Patent number: 10505526
    Abstract: A high frequency multichannel pulse width modulation (PWM) control apparatus includes a pre-scaler configured to divide a frequency of a main clock signal to generate a first clock signal, and a multichannel PWM generator including first to n-th PWM generators, the PWM generators comprising corresponding periods and duties, configured to generate, respectively, first to n-th PWM signals, through first and second N/2-bit counting for the main clock signal, using the first clock signal, wherein each of the first to n-th PWM generators performs the first N/2-bit counting on the main clock signal based on the first clock signal, a corresponding coarse duty value, and a corresponding coarse period value to generate a fine clock signal, and performs the second N/2-bit counting on the fine clock signal based on a corresponding fine duty value and a corresponding fine period value to generate a corresponding PWM signal.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 10, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jin Yong Kang
  • Patent number: 10503238
    Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 10, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Mehmet Iyigun, Kai-Lun Hsu, Rahul Nair, Mark Allan Bellon, Arun U. Kishan, Tristan A. Brown
  • Patent number: 10498524
    Abstract: A timing method and a clock device are provided. The method includes: determining a timing point according to a timing duration of a clock device, where a clock period of the clock device is T, the timing duration is N times of a first time duration, and the first time duration is equal to Q2×T, where Q2=?Q1? or Q2=?Q1?, and Q1=C/T, N is a positive integer, Q1 is not an integer, and C is a constant (210); and performing one adjustment on timing time of the clock device each time P first time durations elapse, where an amount of time for each adjustment is one clock period T, P=1/|Q2?Q1| (220). Based on this method, accurate timing can still be effectively implemented when a ratio of a constant C (for example, 1.25 ms) to a clock period is not an integer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 3, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Tian Yin
  • Patent number: 10484519
    Abstract: In one example in accordance with the present disclosure, a system for auto-negotiation over extended backplane includes an enclosure and a switch external to the enclosure. The enclosure has a NIC (network interface controller) for a server in the enclosure and a DEM (downlink extension module). The DEM has a single DEM PHY connected to the NIC via a backplane and also connected to the switch via an external connection. The DEM PHY facilitates auto-negotiation between the switch and the NIC.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 19, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Guodong Zhang, Paul T. Vu, Michael Lee Witkowski, Robert R. Teisberg, John V. Butler
  • Patent number: 10483963
    Abstract: A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 19, 2019
    Assignee: RichWave Technology Corp.
    Inventor: Juang-Shiung Wu
  • Patent number: 10481067
    Abstract: A method and system includes acquiring a seismic dataset while fluids are injected into the subsurface with seismic data recorded at multiple sensor locations. Seismic travel times are computed between sensors and subsurface locations using a velocity model. Travel times and travel time delays between pairs of sensors may be used as input to determine a similarity coefficient associated with subsurface positions. The similarity coefficients are determined using cross correlation, semblance calculations or eigenstructure decomposition. The coefficient values are related to the acoustic response at each subsurface position and may be summed together for each position for comparison with other subsurface positions to determine the position of a fluid front moving through the subsurface. The values may be displayed to illustrate the position of fluids in the subsurface and displayed to show the time variance of the fluid position.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: November 19, 2019
    Assignee: Sigma Cubed Inc.
    Inventors: Brian Fuller, John Marcus Sterling, Les G. Engelbrecht
  • Patent number: 10476607
    Abstract: A payment terminal has a clock management unit for providing clock signals to components of the payment terminal. The payment terminal also has a wireless communication interface for communicating wireless signals. A processing unit of the payment terminal may monitor operation of a wireless communication interface of the payment terminal and, when the payment terminal is communicating wirelessly, modify an initial clock signal provided to one or more components of the payment terminal that emit RF noise to modify a frequency at which the RF noise occurs. When the payment terminal is no longer transmitting, the processing unit may provide the initial clock signal to the RF noise source.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: November 12, 2019
    Assignee: Square, Inc.
    Inventors: Jeremy Wade, Afshin Rezayee
  • Patent number: 10453504
    Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seok Kang, Seungjun Bae
  • Patent number: 10453072
    Abstract: A disassemble monitoring device of an electronic device includes a detecting unit, a one time programmable register, a storage, and a processor. The detecting unit is configured to detect whether the electronic device has been disassembled, and upon detecting that the electronic device has been disassembled, generate a detection signal. The one time programmable register is electrically coupled to the detecting unit and is configured to change a storage value of the one time programmable register in response to the detection signal. The storage value can only be changed once. The processor retrieves the storage value from the one time programmable register in response to a user operation and determines whether the storage value has been changed. Upon determining that the storage value has been changed, the processor confirms a result of determination that the electronic device has been disassembled and outputs the result of determination.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 22, 2019
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Cheng-Xiang Liu
  • Patent number: 10446094
    Abstract: The present disclosure provides a gate driver on array (GOA) circuit, where the GOA circuit includes a GOA driving chip, a GOA driving signal line, an array substrate test chip, a test signal line, and a GOA protecting circuit. The GOA driving chip is used to generate a scan driving signal. The GOA driving signal line is used to transmit the scan driving signal to a corresponding scan line. The array substrate test chip is used to generate an array substrate test signal. The test signal line is used to transmit the array substrate test signal to the corresponding scan line. The GOA protecting circuit is arranged between the GOA driving signal line and the test signal line.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 15, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Guanghui Hong, Gui Chen, Qiang Gong
  • Patent number: 10447465
    Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 15, 2019
    Assignee: Rambus Inc.
    Inventors: Bret G. Stott, Craig E. Hampel, Frederick A. Ware
  • Patent number: 10416706
    Abstract: Disclosed is a calibration unit for calibrating an oscillator of a device comprises a counting and comparing unit and a control circuit. The counting and comparing unit is configured to determine a number of periods of a clock signal lying between a starting instance and an ending instance. Therein, the clock signal is generated by the oscillator. The counting and comparing unit is further configured to determine a deviation of the number of periods from a reference number. The control circuit is configured to adjust the oscillator depending on the deviation.
    Type: Grant
    Filed: July 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Synopsys, Inc.
    Inventors: Carlos Azeredo Leme, Adam Burns, Dino Toffolon
  • Patent number: 10386943
    Abstract: According to various embodiments, provided are an electronic device and a control method therefor, the electronic device comprising: a main body comprising at least one electronic component; a rotating body rotatably provided in a manner such that the rotating body encompasses at least a part of a region of the main body; a rotation detection means for detecting a rotation parameter of the rotating body; and at least one processor for performing a corresponding function of the electronic device on the basis of the detected rotation parameter.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongyi Kim, Junhui Lee
  • Patent number: 10387360
    Abstract: An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 20, 2019
    Assignee: M31 Technology Corporation
    Inventors: Pin-Hao Feng, Yueh-Chuan Lu, Ching-Hsiang Chang
  • Patent number: 10382090
    Abstract: Provided is a technique that can generate a spread spectrum clock signal in all of an upper-spread mode, a down-spread mode, and a center-spread mode. A spread spectrum clock generator (2) spreads a spectrum of a signal with a predetermined carrier frequency to generate a spread spectrum clock signal under the control of a control unit (13). The control unit includes carrier frequency correction control means (13b). The carrier frequency correction control means shifts the predetermined carrier frequency to generate, from one spread mode, a spread spectrum clock signal of another pseudo spread mode.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 13, 2019
    Assignee: ANRITSU CORPORATION
    Inventors: Ittetsu Kaji, Kazuhiro Yamane
  • Patent number: 10374811
    Abstract: The systems, methods and apparatuses described herein provide a computing environment that includes secure time management. An apparatus according to the present disclosure may comprise a non-volatile storage to store a synchronization time and a processor. The processor may be configured to generate a request for a current time, transmit the request to a trusted timekeeper, receive a digitally signed response containing a current, real-world time from the trusted timekeeper, verify the digital signature of the response, verify that the response is received within a predefined time, compare a nonce in the request to a nonce in the response, determine that the current, real-world time received from the trusted timekeeper is within a range of a current time calculated at the apparatus and update the synchronization time with the current, real-world time in the response.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 6, 2019
    Assignee: OLogN Technologies AG
    Inventors: Sergey Ignatchenko, Dmytro Ivanchykhin
  • Patent number: 10338978
    Abstract: An electronic device test system and method detects a memory serial number of an electronic device. The electronic device test system includes a Macintosh system computer, configured to execute a serial number detection program to detect the memory serial number of the electronic device; and a Windows system computer, configured to execute a serial number comparison program to compare whether the memory serial number of the electronic device satisfies a coding rule. The Macintosh system computer transmits the memory serial number to the Windows system computer by means of an RS232 interface for printing.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: July 2, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Pei-Ming Chang, Shih-Chieh Hsu
  • Patent number: 10339036
    Abstract: A device may receive information identifying a first set of instructions. The first set of instructions may identify an action to perform to test a first program. The device may identify a second set of instructions, related to testing a second program, that can be used in association with the first set of instructions. The first test may be similar to the second test. The device may identify multiple steps, of the first set of instructions, that can be combined to form a third set of instructions. The third set of instructions may be used to test the first program or a third program. The device may generate program code in a first programming language to perform the action. The first programming language may be different than a second programming language used to write the first set of instructions. The device may perform the action.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 2, 2019
    Assignee: Accenture Global Solutions Limited
    Inventors: Anurag Dwarakanath, Dipin Era, Subani Basha Nure, Neville Dubash, Sanjay Podder, Aditya Priyadarshi, Bargav Jayaraman
  • Patent number: 10310580
    Abstract: An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 4, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Steve Xiaofeng Chi, Ekram Hossain Bhuiyan
  • Patent number: 10275010
    Abstract: A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: April 30, 2019
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Hugh Thomas Mair, Sumanth Katte Gururajarao, Gordon Gammie, Alice Wang, Uming Ko, Rolf Lagerquist
  • Patent number: 10275001
    Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Timothy Y. Kam, Sandeep Ahuja, Rajat Agarwal, Avinash Sodani, Jinho Suh, Meenakshisundaram Chinthamani
  • Patent number: 10262704
    Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Homare Sato, Chiaki Dono, Chikara Kondo
  • Patent number: 10237484
    Abstract: An image capturing apparatus is configured to have an interchangeable lens detachably mounted thereto, and is provided with an image capturing unit configured to obtain a captured image, a synchronous signal generation unit configured to generate a synchronous signal for reading out the captured image continuously from the image capturing unit, a communication unit configured to transmit the synchronous signal to the interchangeable lens, and a measurement unit configured to measure a delay time from a timing at which the synchronous signal is generated until a timing at which the communication unit transmits the synchronous signal to the interchangeable lens, the delay time being transmitted to the interchangeable lens by the communication unit together with the synchronous signal.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 19, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Atsushi Sugita
  • Patent number: 10235862
    Abstract: An electronic apparatus includes a motherboard, a random access memory, a motherboard battery and a processing unit. The random access memory is disposed on the motherboard. The motherboard battery is disposed on the motherboard and electrically coupled to the random access memory to supply electrical power to the random access memory. The processing unit is disposed on the motherboard and electrically coupled to the random access memory. The processing unit is configured to write a test value into an idle address register of the random access memory and further to check whether the idle address register maintains the test value. When the idle address register maintains the test value, the processing unit determines that the motherboard battery functions normally. When the idle address register reverts to an initial value, the processing unit determines that the motherboard battery malfunctions.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: March 19, 2019
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Sheng-Han Chiang, Feng-Shan Chen
  • Patent number: 10228420
    Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
  • Patent number: 10218363
    Abstract: A circuit includes a reference clock terminal configured to receive a signal indicative of a reference clock, multiple low power oscillators (LPOs) and a controller. Each LPO is operable in at least one of three states including a sleep state in which the LPO is powered off, a calibration state in which the LPO undergoes calibration and an active mode in which the LPO is configured to provide a real-time clock based on the reference clock. The controller controls operation of the LPOs such that at most a single LPO is in the active state at any given time.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 26, 2019
    Assignee: Verily Life Sciences LLC
    Inventor: Amirpouya Kavousian
  • Patent number: 10204667
    Abstract: A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 12, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Aaron P. Boehm
  • Patent number: 10197628
    Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 5, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel