Abstract: A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

Abstract: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

Abstract: A Real-Time Clock (RTC) block configured to output a current time as part of an ASIC configuration that guarantees that the RTC can never be rolled back beyond a checkpointed date and time. A checkpoint memory block is coupled to the RTC block and configured to include a stored active date/time checkpoint, and a set RTC logic block is coupled to the checkpoint memory block and to the RTC block and configured to permit setting the RTC block to an asserted new time request only when the asserted new time is in the future relative to the stored active date/time checkpoint. The active date/time checkpoint is stored in a non-volatile, single-write memory location such as in a one-time programmable (OTP) memory or in a bank of fuses so that the stored active date/time checkpoint is maintained whether or not power is interrupted to the checkpoint memory block.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: Programming time delay data in an oversampled sensor includes determining whether to enter Programming Mode based on a value of a system parameter received by the oversampled sensor. Programming Mode is entered when the value of the system parameter corresponds to Programming Mode. The time delay data is programmed in the oversampled sensor during Programming Mode. The oversampled sensor uses the time delay data to time delay its output in an oversampled domain. Programming Mode is exited after a predetermined time has expired relative to when Programming Mode was entered. The system parameter can be a frequency of a sampling clock signal.

Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

Abstract: Two or more modules communicate over a common control network including receiving by a message packet having data defined by a signal level at defined bit quanta of a bit, the defined bit quanta being less than every bit quanta of a bit, and the communication device samples bit quanta other than the defined bit quanta. The module receives signal disturbances and decodes the signal disturbances as having a value different from an expected value of the certain bit. In another form, the module uses a first counter based on a clock local to the communication device and a second counter having a higher sampling rate than the first counter. Here, the module receives over the control network a synchronizing portion of a message and counts clock ticks of the second counter over a portion of the message to determine a clock rate for a module that transmitted the message.

Abstract: A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.

Abstract: A convolutional operation device for performing convolutional neural network processing includes an input sharing network including first and second input feature map registers configured to shift each input feature map, which is inputted in row units, in a row or column direction and output the shifted input feature map and arranged in rows and columns, a first MAC array connected to the first input feature map registers, an input feature map switching network configured to select one of the first and second input feature map registers, a second MAC array connected to one selected by the input feature map switching network among the first and second input feature map registers, and an output shift network configured to shift the output feature map from the first MAC array and the second MAC array to transmit the shifted output feature map to an output memory.

Abstract: The invention relates to a method for providing a fault-tolerant global time and for the fault-tolerant transport of time-controlled messages in a distributed real-time computer system which comprises external computers and a fault-tolerant message distribution unit, FTMDU. The FTMDU comprises at least four components which supply the global time to the external computers by means of periodic external synchronization messages, wherein the external computers each set their local clock to the received global time, wherein each external sender of a time-controlled message transmits two message copies of the message to be sent via two different communication channels to two different components of the FTMDU at periodic sending times defined a priori in timetables, wherein these two message copies are delivered within the FTMDU via two independent communication paths to those two components of the FTMDU which are connected to an external receiver of the message via communication channels.

Abstract: Systems and methods for maintaining synchronization of repeater networks with Global Positioning System (GPS) signals using phase locked loops (PLLs) and based on generation of predicted control words for controlling local oscillator frequencies is described. The predicted control words can be generated based on performing a linear fit of control words generated over a predetermined duration of time. Phase locked loops with additional false GPS pulse identification and GPS signal loss compensation circuitry can enforce a false pulse count threshold and/or an error threshold. The additional circuitry and prediction of control words can overcome errors in GPS receiver outputs and maintain accuracy of signal timings across single frequency networks using inexpensive local oscillators.

Abstract: A method, implemented by a computer system comprising a trusted execution environment (TEE) and a rich execution environment (REE) includes creating, by the TEE, a plurality of sub-threads preparing to implement sub-functions of a trusted application (TA), for each sub-thread, triggering, by the TEE, the REE to generate a shadow thread, where running of the shadow thread will cause a core on which the shadow thread runs to enter the TEE, and scheduling the created sub-thread to the entered core for execution.

Abstract: A processing circuit includes a random access memory (RAM) configured to look up a first next state based on a first address simultaneously with looking up a second next state based on a second address. The first address is formed of a first current state and an input data and the second address is formed of a second current state and the input data. The processing circuit includes a state control circuit that receives the first and second next states, the first current state, and the second current state, and a first-in-first-out (FIFO) memory that stores selected ones of the first and second next states, the first current state, and the second current state. The processing circuit includes a multiplexer configured to selectively pass two states from the FIFO memory or two states from the state control circuit as a third current state and a fourth current state.

Abstract: A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

Abstract: The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.

Abstract: A method for providing an anti-rollback secure timer service includes determining, at a device which includes a processor providing a trusted execution environment (TEE), a trusted memory, and a real time clock (RTC) accessible through an operating system of the device, an initial reference time value, by a secure timer application running in the TEE, the initial reference time value determined based on an initial value of the RTC obtained during booting of the device and a time delta value. The method further includes determining an updated reference time value based on the initial reference time value, a second value of the RTC, and a previously stored old reference time value, determining an updated time delta value based on the second value of the RTC and the updated reference time value, and storing the updated time delta value and the updated reference time value in the trusted memory.

Abstract: An all-digital closed-loop fine-grained control of voltage and frequency for running conditions of a compute machine such as graphic processor unit (GPU), central processing unit (CPU), or any other processing unit. The scheme optimizes the voltage margin and frequency on the fly according to desired programmable performance metrics. A mitigation response to droops is naturally built into the system and is equal to the cause rather than being excessive. The scheme is scalable and can be instantiated in different clusters for best results.

Abstract: Examples disclosed herein relate to power management in a blade enclosure. An intrusion detection mode is initiated by a baseboard management controller. Responsive to determining a power shortage in the blade enclosure, a stop clock pin is operated to control power consumption of a server in the blade enclosure. After a predefined time of determining the power shortage, a model specific register (MSR) associated with power settings of a Central processing unit (CPU) of the server is reconfigured. Reconfiguring the MSR comprises, identifying a power profile based on available power in the blade enclosure and modifying register states in the MSR based on the power profile via a baseboard management manager (BMC) of the server. Subsequently, operation of the stop clock pin is stopped.

Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Abstract: Clock skew may be increased along a critical path of a systolic array. Pipelined registers may be added between a bus that provides input data signals to a systolic array and between a bus that receives output data signals from the systolic array. Skew circuitry for the pipelined registers may be implemented to delay a clock signal to the pipelined registries to allow a clock skew accumulated along a critical path of the systolic array to exceed a single clock cycle.

Abstract: A method may include initializing operation of a baseboard management controller at an information handling system. The baseboard management controller includes a real time clock. The method further includes receiving clock information from a real time clock circuit included at a field programmable gate array. The clock information at the real time clock at the baseboard management controller can be updated with the clock information received from the real time clock circuit included at the field programmable gate array.

Abstract: The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.

Abstract: A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

Abstract: An information processing apparatus includes a first controller that operates while receiving first power and executes device-independent control; a second controller that operates while receiving second power and controls a device on a basis of a command from the first controller; a clock management unit that operates while receiving continuous power, and limits supply of a first clock signal to the first controller until the first power is supplied and limits supply of a second clock signal to the second controller until the second power is supplied; and a reset cancellation management unit that operates while receiving continuous power, limits supply of a first reset cancellation signal to the first controller until operation using the first clock signal starts and limits supply of a second reset cancellation signal to the second controller until operation using the second clock signal starts.

Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.

Abstract: Data is synchronized when transmitted from a circuit operated at first frequency to another circuit operated at second frequency. A synchronization method includes storing data write pointers in a line, storing data input from a source at first frequency at a location in a data buffer designated by the write pointer at one end of the line, taking out the write pointer at the one end from the line to store it in the synchronization buffer, synchronizing a validation signal input from the input source at first frequency to second frequency, reading out the write pointer stored in the synchronization buffer when the validation signal is synchronized, adding completion information that indicates completion of synchronization to the data stored at the location in the data buffer designated by the read out write pointer, and reading out, from the data buffer, the data to which the completion information is added.

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

Abstract: Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.

Abstract: The present disclosure relates to a security device, a system, and a method for securing a control apparatus. The security device includes a data security unit which is configured to secure data, data communication and information, and includes a first security component inside the data security unit to operate in a first operating mode, and at least one first monitoring unit to operate in a high-availability mode which, said first monitoring unit being configured to detect a fault present in the first security component. The high-availability mode is different from the first operating mode. The security device further includes a second security component which is configured to operate in the high-availability mode and to output a first response signal if a fault is detected by the first monitoring, where the high-availability mode is available independently from the first operating mode.

Abstract: Systems, devices, and methods are provided for the management of multiple sensor control devices and/or multiple reader devices in an in vivo analyte monitoring environment, and also for resolving conflicts when merging data collected by different reader devices.

Abstract: A method is described for switching off a communication between at least two bus subscribers, which are connected to one another via a data bus and which transmit during the communication respectively one transmission clock signal in addition to a data signal, at least one of the bus subscribers generating its transmission clock signal and its data signal based on a reference clock signal, as well as a corresponding communication system. In the case of a fault, the reference clock signal is switched off so that the at least one affected bus subscriber no longer transmits a transmission clock signal and no longer transmits a data signal, and the faulty communication is switched off.

Abstract: In an embodiment, a data path circuit includes: a plurality of pipeline stages coupled between an input of the data path circuit and an output of the data path circuit; and a first selection circuit coupled between a first pipeline stage and a second pipeline stage, the first selection circuit having a first input to receive an input to the first pipeline stage and a second input to receive an output of the first pipeline stage and controllable to output one of the input to the first pipeline stage and the output of the first pipeline stage. A bypass controller coupled to the data path circuit may control the first selection circuit based at least in part on an operating frequency of the data path circuit. Other embodiments are described and claimed.

Abstract: In one example in accordance with the present disclosure, a system for auto-negotiation over extended backplane includes an enclosure and a switch external to the enclosure. The enclosure has a NIC (network interface controller) for a server in the enclosure and a DEM (downlink extension module). The DEM has a single DEM PHY connected to the NIC via a backplane and also connected to the switch via an external connection. The DEM PHY facilitates auto-negotiation between the switch and the NIC.

Abstract: A signal transmitting circuit providing compatibility and stability in signal transmissions across domains with different clock frequencies includes an edge detection circuit, a flip circuit, a synchronization circuit, and an edge extraction circuit. The edge detection circuit detects an edge of an initial interrupt signal and generates an event trigger signal in a faster clock domain. The flip circuit converts the event trigger signal into an edge signal. The synchronization circuit synchronizes the edge signal under a slower clock domain and generates a synchronization signal. The edge extraction circuit generates a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. A method and an electronic apparatus related to the signal transmitting circuit are also disclosed.

Abstract: Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.

Abstract: A browser-based video editor is configured to allow a user to create a composition schema having multimedia layers, including video, audio, and graphic and text layers. The composition schema may be transmitted to a remote service that employs a rendering engine to play back the composition schema and align the clocks for each respective multimedia layer into a single video representation. A master clock object is employed to sync the clocks while also checking a series of properties with each multimedia layer to comport the multimedia layers with an interval-based master clock. The composition schema is recorded using FFmpeg (Fast Forward Moving Picture Experts Group) to create a video representation for user consumption, such as an MP4 (Motion Pictures Experts Group 4) formatted file.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: To precisely synchronize system clocks, medium clocks, or the like of apparatuses with each other. A wireless apparatus includes a main control unit and a wireless control unit. Information regarding a correspondence between a clock that manages a time of the main control unit and a clock that manages a time of the wireless control unit is wirelessly sent to another wireless apparatus by the wireless control unit. This information regarding the correspondence includes information regarding a difference between the two clocks, information regarding a granularity ratio of the two clocks, and the like. For example, the wireless control unit sends the information regarding the correspondence as a part of a frame for measuring the time of the wireless control unit with respect to the other wireless apparatus or a part of a frame for connecting to the other wireless apparatus.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.

Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: A small form-factor pluggable (SFP) time signal adapter module includes a printed circuit board, a cable connector mounted to the printed circuit board, and a differential receiver coupled to the cable connector, one or more of the plurality of wire traces, and an SFP edge connector. The printed circuit board has a plurality of wire traces and a plurality of pads of the SFP edge connector is at least coupled to two of the plurality of wire traces. The cable connector is coupled to at least one or more of the plurality of wire traces. The cable connector coupes to a connector of a cable to receive a differential time reference signal. The differential receiver receives and differentiates the differential time input signal to generate a single ended time reference signal that is coupled to a pad of the SFP edge connector.

Abstract: A switching device includes two connection lands, a measurement device for measuring a first quantity of a current flowing between the two lands, a power supply system and a trigger module, the latter including a first driver module for detecting an electrical fault according to first values stored in a first memory and controlling a switching member; a communication module for receiving and storing second values in a second, non-volatile memory; and a second driver module for replacing the first values with the second values in the first memory. The first driver module compares a second quantity of the first supply current with a threshold and controls the supply of power to the second driver module if the second value is higher than or equal to the threshold.

Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.

Abstract: We disclose herein an electronic device comprising: a state machine for receiving an output signal from a sensor; a comparator operatively coupled with the state machine; and a first processor operatively coupled with the comparator. The state machine is configured to receive the output signal from the at least one sensor to obtain sensor measurement data and configured to pass the obtained sensor measurement data to the comparator. The comparator is configured to process the obtained sensor measurement data into first processed sensor data, and configured to compare the first processed sensor data with a first predetermined threshold limit. The comparator is configured to inform the first processor about the obtained sensor measurement data if the first processed sensor data exceed the first predetermined threshold limit.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.