Clock, Pulse, Or Timing Signal Generation Or Analysis Patents (Class 713/500)
  • Patent number: 11327522
    Abstract: An information processing apparatus includes a first controller that operates while receiving first power and executes device-independent control; a second controller that operates while receiving second power and controls a device on a basis of a command from the first controller; a clock management unit that operates while receiving continuous power, and limits supply of a first clock signal to the first controller until the first power is supplied and limits supply of a second clock signal to the second controller until the second power is supplied; and a reset cancellation management unit that operates while receiving continuous power, limits supply of a first reset cancellation signal to the first controller until operation using the first clock signal starts and limits supply of a second reset cancellation signal to the second controller until operation using the second clock signal starts.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 10, 2022
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Masahiro Kobata, Kenji Imamura, Shinho Ikeda, Kazuhiko Abe, Yuji Murata, Takanori Fukuoka
  • Patent number: 11329669
    Abstract: A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 10, 2022
    Assignee: THINE ELECTRONICS. INC.
    Inventors: Satoshi Miura, Yusuke Fujita
  • Patent number: 11314277
    Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 26, 2022
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Gourav Modi, Azarudin Abdulla, Chee Chong Chan
  • Patent number: 11302370
    Abstract: Data is synchronized when transmitted from a circuit operated at first frequency to another circuit operated at second frequency. A synchronization method includes storing data write pointers in a line, storing data input from a source at first frequency at a location in a data buffer designated by the write pointer at one end of the line, taking out the write pointer at the one end from the line to store it in the synchronization buffer, synchronizing a validation signal input from the input source at first frequency to second frequency, reading out the write pointer stored in the synchronization buffer when the validation signal is synchronized, adding completion information that indicates completion of synchronization to the data stored at the location in the data buffer designated by the read out write pointer, and reading out, from the data buffer, the data to which the completion information is added.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: April 12, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Shinichi Iwasaki
  • Patent number: 11281604
    Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David Andrew Roberts, Joseph Thomas Pawlowski, Elliott Cooper-Balis
  • Patent number: 11249536
    Abstract: Reducing power consumption of communication interfaces by clock frequency scaling and adaptive interleaving of polling is disclosed. In a first aspect, a control system controls transmission of a command via a serial interface at a higher clock frequency. After transmission, the control system and the interface are operated at a lower clock frequency to save power during command execution. In this aspect, a reduction in polling corresponds to the reduction in clock signal frequency. When the command is complete, the interface is operated at the higher frequency to send another command. In a second aspect, after the control system sends a command to the receiving device, polling is suspended and an execution time of the command is tracked. Polling begins when the tracked execution time almost equals an expected completion time. Both aspects disclosed above may be implemented to reduce power consumption in exchange for a small increase in latency.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 15, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Sandeep Kumar, Suman Kumar, Deven Balani
  • Patent number: 11227072
    Abstract: The present disclosure relates to a security device, a system, and a method for securing a control apparatus. The security device includes a data security unit which is configured to secure data, data communication and information, and includes a first security component inside the data security unit to operate in a first operating mode, and at least one first monitoring unit to operate in a high-availability mode which, said first monitoring unit being configured to detect a fault present in the first security component. The high-availability mode is different from the first operating mode. The security device further includes a second security component which is configured to operate in the high-availability mode and to output a first response signal if a fault is detected by the first monitoring, where the high-availability mode is available independently from the first operating mode.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 18, 2022
    Inventors: Avni Bildhaiya, Viola Rieger, Frank Hellwig, Alexander Zeh
  • Patent number: 11159621
    Abstract: Systems, devices, and methods are provided for the management of multiple sensor control devices and/or multiple reader devices in an in vivo analyte monitoring environment, and also for resolving conflicts when merging data collected by different reader devices.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 26, 2021
    Assignee: ABBOTT DIABETES CARE INC.
    Inventors: Mark Sloan, Nathan C. Crouther, Glenn Berman, Gil Porat, Michael R. Love
  • Patent number: 11140002
    Abstract: A method is described for switching off a communication between at least two bus subscribers, which are connected to one another via a data bus and which transmit during the communication respectively one transmission clock signal in addition to a data signal, at least one of the bus subscribers generating its transmission clock signal and its data signal based on a reference clock signal, as well as a corresponding communication system. In the case of a fault, the reference clock signal is switched off so that the at least one affected bus subscriber no longer transmits a transmission clock signal and no longer transmits a data signal, and the faulty communication is switched off.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 5, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Guenter Weiss, Kevin Haist
  • Patent number: 11132201
    Abstract: In an embodiment, a data path circuit includes: a plurality of pipeline stages coupled between an input of the data path circuit and an output of the data path circuit; and a first selection circuit coupled between a first pipeline stage and a second pipeline stage, the first selection circuit having a first input to receive an input to the first pipeline stage and a second input to receive an output of the first pipeline stage and controllable to output one of the input to the first pipeline stage and the output of the first pipeline stage. A bypass controller coupled to the data path circuit may control the first selection circuit based at least in part on an operating frequency of the data path circuit. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Ryan Carlson, Jianwei Dai
  • Patent number: 11128741
    Abstract: In one example in accordance with the present disclosure, a system for auto-negotiation over extended backplane includes an enclosure and a switch external to the enclosure. The enclosure has a NIC (network interface controller) for a server in the enclosure and a DEM (downlink extension module). The DEM has a single DEM PHY connected to the NIC via a backplane and also connected to the switch via an external connection. The DEM PHY facilitates auto-negotiation between the switch and the NIC.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 21, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Guodong Zhang, Paul T. Vu, Michael Lee Witkowski, Robert R. Teisberg, John V. Butler
  • Patent number: 11112820
    Abstract: A signal transmitting circuit providing compatibility and stability in signal transmissions across domains with different clock frequencies includes an edge detection circuit, a flip circuit, a synchronization circuit, and an edge extraction circuit. The edge detection circuit detects an edge of an initial interrupt signal and generates an event trigger signal in a faster clock domain. The flip circuit converts the event trigger signal into an edge signal. The synchronization circuit synchronizes the edge signal under a slower clock domain and generates a synchronization signal. The edge extraction circuit generates a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. A method and an electronic apparatus related to the signal transmitting circuit are also disclosed.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 7, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yi-Lang Kao
  • Patent number: 11101802
    Abstract: Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jung-Hwa Choi
  • Patent number: 11095938
    Abstract: A browser-based video editor is configured to allow a user to create a composition schema having multimedia layers, including video, audio, and graphic and text layers. The composition schema may be transmitted to a remote service that employs a rendering engine to play back the composition schema and align the clocks for each respective multimedia layer into a single video representation. A master clock object is employed to sync the clocks while also checking a series of properties with each multimedia layer to comport the multimedia layers with an interval-based master clock. The composition schema is recorded using FFmpeg (Fast Forward Moving Picture Experts Group) to create a video representation for user consumption, such as an MP4 (Motion Pictures Experts Group 4) formatted file.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 17, 2021
    Assignee: POND5 INC.
    Inventors: Mathieu Frederic Welche, Hugo Valentín Elías García, Taylor James McMonigle, Pier Stabilini, Nicola Onassis
  • Patent number: 11068017
    Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 20, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 11064452
    Abstract: To precisely synchronize system clocks, medium clocks, or the like of apparatuses with each other. A wireless apparatus includes a main control unit and a wireless control unit. Information regarding a correspondence between a clock that manages a time of the main control unit and a clock that manages a time of the wireless control unit is wirelessly sent to another wireless apparatus by the wireless control unit. This information regarding the correspondence includes information regarding a difference between the two clocks, information regarding a granularity ratio of the two clocks, and the like. For example, the wireless control unit sends the information regarding the correspondence as a part of a frame for measuring the time of the wireless control unit with respect to the other wireless apparatus or a part of a frame for connecting to the other wireless apparatus.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 13, 2021
    Assignee: SONY CORPORATION
    Inventors: Takeshi Itagaki, Junji Kato, Hideyuki Suzuki
  • Patent number: 11042349
    Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 22, 2021
    Assignee: B&W Group Ltd.
    Inventors: Leo Lay, Adrian Harold Chadd, Haisong Wang, Shiwei Zhao, Li Li, Gaylord Yu
  • Patent number: 10997353
    Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 4, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: I-Ching Tsai, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 10996723
    Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 4, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Quang Nguyen, Duc Dang, Raju Joshi, David Abada, Akash Sharma, Zhanhe Shi
  • Patent number: 10992403
    Abstract: A small form-factor pluggable (SFP) time signal adapter module includes a printed circuit board, a cable connector mounted to the printed circuit board, and a differential receiver coupled to the cable connector, one or more of the plurality of wire traces, and an SFP edge connector. The printed circuit board has a plurality of wire traces and a plurality of pads of the SFP edge connector is at least coupled to two of the plurality of wire traces. The cable connector is coupled to at least one or more of the plurality of wire traces. The cable connector coupes to a connector of a cable to receive a differential time reference signal. The differential receiver receives and differentiates the differential time input signal to generate a single ended time reference signal that is coupled to a pad of the SFP edge connector.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 27, 2021
    Assignee: Endace Technology Limited
    Inventors: David Earl, Stuart Wilson
  • Patent number: 10985545
    Abstract: A switching device includes two connection lands, a measurement device for measuring a first quantity of a current flowing between the two lands, a power supply system and a trigger module, the latter including a first driver module for detecting an electrical fault according to first values stored in a first memory and controlling a switching member; a communication module for receiving and storing second values in a second, non-volatile memory; and a second driver module for replacing the first values with the second values in the first memory. The first driver module compares a second quantity of the first supply current with a threshold and controls the supply of power to the second driver module if the second value is higher than or equal to the threshold.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 20, 2021
    Assignee: Schneider Electric Industries SAS
    Inventor: Fabien Odille
  • Patent number: 10928372
    Abstract: We disclose herein an electronic device comprising: a state machine for receiving an output signal from a sensor; a comparator operatively coupled with the state machine; and a first processor operatively coupled with the comparator. The state machine is configured to receive the output signal from the at least one sensor to obtain sensor measurement data and configured to pass the obtained sensor measurement data to the comparator. The comparator is configured to process the obtained sensor measurement data into first processed sensor data, and configured to compare the first processed sensor data with a first predetermined threshold limit. The comparator is configured to inform the first processor about the obtained sensor measurement data if the first processed sensor data exceed the first predetermined threshold limit.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 23, 2021
    Assignee: AMS SENSORS UK LIMITED
    Inventors: Douglas James McMillan, Clinton Sean Dixon, Simon Jonathan Stacey
  • Patent number: 10931305
    Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 23, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Hong Seok Choi, Jeongho Hwang, Hyungrok Do, Deog-Kyoon Jeong
  • Patent number: 10901485
    Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 26, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
  • Patent number: 10825082
    Abstract: A recycling kiosk for recycling and financial remuneration for submission of a mobile telephone is disclosed herein. The recycling kiosk includes an inspection area with a plurality of white walls in order to perform a visual analysis of the mobile telephone for determination of a value of the mobile telephone. The visual analysis inspects the LCD screen of the mobile phone to determine if the LCD screen is damaged. The recycling kiosk also includes a processor, a display and a user interface.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 3, 2020
    Assignee: ecoATM, LLC
    Inventors: Michael Librizzi, Mark Vincent Bowles, Ahron Duben
  • Patent number: 10810114
    Abstract: A method for testing autonomous reconfiguration logic for an electromechanical actuator includes executing a plurality of test cases against a computer model configured and operable to implement autonomous reconfiguration logic for an electromechanical actuator including a plurality of electromechanical motors to generate a first set of test results. The method further includes executing the plurality of test cases against a programmable logic device configured and operable to implement the autonomous reconfiguration logic for the electromechanical actuator to generate a second set of test results and comparing the first set of test results to the second set of test results.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Hamilton Sundstrand Corporation
    Inventors: David F. Dickie, Steven A. Avritch, Peter E. Gardow
  • Patent number: 10802534
    Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Patent number: 10769038
    Abstract: Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal, the slave counter circuitry having associated fault detection circuitry; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry, the master counter circuitry being configured to provide via the synchronisation connection: initialisation data at an initialisation operation; and fault detection data at a fault detection operation; the initialisation data and subsequent fault detection data each representing respective indications of a state of the master count signal; the slave counter circuitry being configured, during an initialisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the initialisation data provided by the master counter circuitry; an
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventors: Peter Uttley, Kar Lik Kasim Wong
  • Patent number: 10771231
    Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Rambus Inc.
    Inventors: Bret G. Stott, Craig E. Hampel, Frederick A. Ware
  • Patent number: 10762947
    Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Keon Lee, Kyung-Soo Ha, Hyong-Ryol Hwang
  • Patent number: 10732699
    Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert Milstrey, Amit K. Srivastava
  • Patent number: 10734043
    Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Ju Kim, Dong-Seok Kang, Hye Jung Kwon, Byungchul Kim, Seungjun Bae
  • Patent number: 10705990
    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 7, 2020
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Ian P. Shaeffer, John Eble
  • Patent number: 10707853
    Abstract: An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jinn-Yeh Chien
  • Patent number: 10705557
    Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: ZhenQi Chen, Jianguo Yao, Scott Davenport, Helena Deirdre O'Shea, Reza Mohammadpourrad
  • Patent number: 10686605
    Abstract: Technologies for providing shared immutable code among untrusting domains are provided. The untrusting domains may be cryptographically separated within a cloud computing service or environment. The shared immutable code may be a shared virtual machine monitor (sVMM) that is setup by system software to indicate that the sVMM code pages need integrity alone and should be protected with an integrity key associated with individual domains. This indication may be stored in page tables and carried over the memory bus to a cryptographic engine. The cryptographic engine may use this indication to protect the integrity of data before storing the data to memory. In order to ensure cryptographic isolation, integrity values may be generated using a domain-specific key ensuring that an attempt to modify the code by one domain is detected by a different domain. Other embodiments are described herein and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, David M. Durham
  • Patent number: 10642861
    Abstract: A method, apparatus, and system for multi-instance redo apply is provided for standby databases. A multi-instance primary database generates a plurality of redo records, which are received and applied by a physical standby running a multi-instance standby database. Each standby instance runs a set of processes that utilize non-blocking, single-task threads for high parallelism. At each standby instance for the multi-instance redo, the plurality of redo records are merged into a stream from one or more redo strands in logical time order, distributed to standby instances according to determined apply slave processes using an intelligent workload distribution function, remerged after receiving updates from remote instances, and applied in logical time order by the apply slave processes. Redo apply progress is tracked at each instance locally and also globally, allowing a consistent query logical time to be maintained and published to service database read query requests concurrently with the redo apply.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 5, 2020
    Assignee: Oracle International Corporation
    Inventors: Amrish Srivastava, Yunrui Li, Mahesh Baburao Girkar
  • Patent number: 10631047
    Abstract: A browser-based video editor is configured to allow a user to create a composition schema having multimedia layers, including video, audio, and graphic and text layers. The composition schema may be transmitted to a remote service that employs a rendering engine to play back the composition schema and align the clocks for each respective multimedia layer into a single video representation. A master clock object is employed to sync the clocks while also checking a series of properties with each multimedia layer to comport the multimedia layers with an interval-based master clock. The composition schema is recorded using FFmpeg (Fast Forward Moving Picture Experts Group) to create a video representation for user consumption, such as an MP4 (Motion Pictures Experts Group 4) formatted file.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 21, 2020
    Assignee: POND5 INC.
    Inventors: Mathieu Frederic Welche, Hugo Valentín Elías García, Taylor James McMonigle, Pier Stabilini, Nicola Onassis
  • Patent number: 10630396
    Abstract: A mobile industry processor interface MIPI clock frequency configuration method and apparatus are provided. When a radio frequency band used by a device on which an MIPI is located changes, an MIPI clock frequency is determined according to radio frequency band information, where the radio frequency band information includes the radio frequency band currently used by the device, and the determined MIPI clock frequency causes no interference to the radio frequency band currently used by the device; and an MIPI clock frequency of the device is configured as the determined MIPI clock frequency. According to the technical solutions in the present invention, when a radio frequency band of a device changes, an MIPI clock frequency causes no interference to communication of the device, thereby improving communication quality and stability of the device.
    Type: Grant
    Filed: April 15, 2018
    Date of Patent: April 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xinglong Zhuang, Tao Ma, Zhimin Tang
  • Patent number: 10579492
    Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan Combs, Jason Brandt
  • Patent number: 10579390
    Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.
    Type: Grant
    Filed: December 3, 2017
    Date of Patent: March 3, 2020
    Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD.
    Inventors: Yoav Etsion, Dani Voitsechov
  • Patent number: 10564666
    Abstract: Clock-controlled circuitry organised into at least first and second clock domains, the first clock domain configured to operate based on a first clock signal and the second clock domain configured to operate based on a second clock signal, wherein: the first clock domain comprises a first signal generator operable to generate a first repetitive signal synchronised to the first clock signal; the second clock domain comprises a second signal generator operable to generate a second repetitive signal synchronised to the second clock signal; the first signal generator is operable, when operating in master mode, to output to the second signal generator a first synchronisation signal indicative of a phase of the first repetitive signal; and the second signal generator is operable, when operating in slave mode, to: set a timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is set to have a phase relationship with the
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 18, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Ross Morgan, Shantanu Shrikant Nalage
  • Patent number: 10565335
    Abstract: An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: February 18, 2020
    Assignee: Montana Systems Inc.
    Inventors: Vivian Chou, Sherman Lee
  • Patent number: 10552115
    Abstract: An audio/video (A/V) hub that calculates an estimated location is described. In particular, the A/V hub may calculate an estimated location of a listener relative to electronic devices (such as electronic devices that include speakers) in an environment that includes the A/V hub and the electronic devices based on: communication with another electronic device; sound measurements in the environment; and/or time-of-flight measurements. Then, the A/V hub may transmit, to the electronic devices, one or more frames that include audio content and playback timing information, which may specify playback times when the electronic devices are to playback the audio content based on the estimated location. Moreover, the playback times of the electronic devices may have a temporal relationship so that the playback of the audio content by the electronic devices is coordinated.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: February 4, 2020
    Assignee: Eva Automation, Inc.
    Inventors: Gaylord Yu, Steven Stupp
  • Patent number: 10541803
    Abstract: Aspects of the disclosed technology provide a method comprising executing different first and second instructions a first and second number of times, respectively, in repeated alternations. The method further comprises measuring spectra of signals emanating as a result of the processor executing the first and second instructions. The method also includes analyzing data indicative of the spectra of the signals to determine side-channel candidate side-band pairs that each have a lower and upper sideband at first and second frequencies, respectively, that are separated by approximately twice the respective alternation frequency. Finally, the method includes identifying a side-channel carrier frequency at a frequency approximately at a midpoint between a side-channel candidate side-band pair's first and second frequency.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 21, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Milos Prvulovic, Nina Basta, Robert Callan, Alenka Zajic
  • Patent number: 10534555
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10530375
    Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Yipeng Wang, Kee Hian Tan, Stanley Y. Chen, Yohan Frans
  • Patent number: 10505526
    Abstract: A high frequency multichannel pulse width modulation (PWM) control apparatus includes a pre-scaler configured to divide a frequency of a main clock signal to generate a first clock signal, and a multichannel PWM generator including first to n-th PWM generators, the PWM generators comprising corresponding periods and duties, configured to generate, respectively, first to n-th PWM signals, through first and second N/2-bit counting for the main clock signal, using the first clock signal, wherein each of the first to n-th PWM generators performs the first N/2-bit counting on the main clock signal based on the first clock signal, a corresponding coarse duty value, and a corresponding coarse period value to generate a fine clock signal, and performs the second N/2-bit counting on the fine clock signal based on a corresponding fine duty value and a corresponding fine period value to generate a corresponding PWM signal.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 10, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jin Yong Kang
  • Patent number: 10503238
    Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 10, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Mehmet Iyigun, Kai-Lun Hsu, Rahul Nair, Mark Allan Bellon, Arun U. Kishan, Tristan A. Brown
  • Patent number: 10498524
    Abstract: A timing method and a clock device are provided. The method includes: determining a timing point according to a timing duration of a clock device, where a clock period of the clock device is T, the timing duration is N times of a first time duration, and the first time duration is equal to Q2×T, where Q2=?Q1? or Q2=?Q1?, and Q1=C/T, N is a positive integer, Q1 is not an integer, and C is a constant (210); and performing one adjustment on timing time of the clock device each time P first time durations elapse, where an amount of time for each adjustment is one clock period T, P=1/|Q2?Q1| (220). Based on this method, accurate timing can still be effectively implemented when a ratio of a constant C (for example, 1.25 ms) to a clock period is not an integer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 3, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Tian Yin