Abstract: A bus utilization detection circuit and method. An input is configured to be coupled to a bus to detect bus events. A circuit coupled to the input determines a number of bus events during a first sample period to indicate a percent bus utilization. If the number of bus events during the first sample period meets a first predetermined threshold value, then an activity event is generated. In another embodiment, an activity event is generated only if during a second sample period, the number of first sample periods for which the percent bus utilization meets the first threshold value meets a second threshold value.

Abstract: In a telecommunication network, a method of determining the accuracy of the real time clocks associated with each element of the network is disclosed. The method comprises sending a marker signal at a predetermined reference time along with the traffic signals to one or more elements in the network, and arranging the element to record the time of the arrival of the marker signal using its clock. The recorded time is then compared with the reference time at the network management center so as to determine the accuracy. In order to correct an inaccurate clock, a message signal is sent, so as to cause the clock to be adjusted by the difference between the reference and its recorded time.

Abstract: A method and apparatus for inserting an event into a simulation time queue, wherein the simulation time queue is represented by a tree structure having a top node which represents the total number of "time slices" to be simulated, intermediate nodes representing subsets of time slices within the total number of time slices to be simulated, and event locations representing events to be simulated. A time slice is defined to represent a minimum resolvable time period within the simulation. The method includes the steps of choosing a starting node within the tree structure, designating it as the current location, determining whether the current location is an intermediate node representing a range of time slices of which the time slice of the event to be inserted is a subset, determining, if the current location is such an intermediate node, if any existing child nodes of said current location are event locations, and if so, adding the event to the proper event location of said current location.

Abstract: An option setting device and method is provided for use on a computer mother-board for providing various user-defined settings to the motherboard. The motherboard includes a CPU, a chip set coupled to the CPU, a clock generator coupled to the chip set, a delay circuit coupled to the chip set, a first latching circuit coupled to the chip set, and a reset circuit coupled to the delay circuit. After the motherboard is power on, the CPU transfers a first setting via the chip set to the first latching circuit so as to allow the first setting to be latched in the first latching circuit, and meanwhile triggers the delay circuit to start counting time. The delay circuit outputs a trigger signal to the reset circuit after a preset time, causing the reset circuit to restart the motherboard. After the motherboard is restarted, the chip set fetches the first setting from the first latching circuit so as to be set accordingly.

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.

Abstract: Modules of a data processing system are configured by providing a configuration file that includes configuration file blocks, a respective one of which contains configuration information for a respective one of the modules. A configuration file interface is also provided for each of the modules. A configuration file interface identifies the configuration file block that contains configuration information for the associated module and consumes the configuration block so identified. A pipe serially passes a configuration file block to the configuration file interfaces, until one of the configuration file interfaces identifies a configuration file block. Configuration file blocks continue to be passed until all of the configuration file blocks have been passed to the appropriate configuration file interface.

Abstract: An inadvertent invocation of power management is avoided by having an application program set a storage location to a predetermined value. The application program then calls a BIOS software interrupt from the application program. The BIOS software interrupt routine determines if the storage location contains the predetermined value and if so, resets the power management timers, thus preventing power management from being inadvertently invoked.

Abstract: A system and method for managing a time stamp wherein a table of time stamps is maintained. Each time stamp corresponds to the age of a block of data. The age of the data is determined from the value of the time stamp in the table. When a block of data is written, the time stamp corresponding to the data is individually reset by writing a zero to the stamped value. Each stamp is aged by updating the time stamps at predetermined time intervals. Aging a time stamp includes reading the time stamp, determining whether to advance the time stamp, and advancing the time stamp. A random number is generated for each time stamp. The random number is compared to an increment threshold value. If the random number matches the increment threshold value, the time stamp is incremented.

Abstract: A method and system for estimating the time to completion of a task being executed on a multitasking workstation potentially subject to the commencement or termination of one or more other tasks. Value arises where the task subject to estimation requires upon its completion the intervention of the workstation user, such as by the physical act of switching diskettes. When the task to be completed is relatively time consuming, such as occurs with the transfer of compressed data from a diskette to a hard disk, the calculation of a complex spreadsheet, the compilation of a lengthy program, or the generation of elaborate graphics, the user of the workstation is particularly interested in knowing about when the task will be completed. With the advent of multitasking workstations and operating systems, a singular static estimation is substantially meaningless. The estimate determination must recognize and compensate for the fact that the central processing unit is a resource which is shared by multiple tasks.

Abstract: In a data bus environment where a host device and a plurality of other devices are connected to the bus, the time required for the first and the last device to respond to a host request is measured. Once the time required between the first and the last response is known, then a read/write window time can be minimized thereby increasing the speed of communication over the data bus.

Abstract: A timeout monitoring system including plural timeout value setting mechanisms, each of which sets a timeout value as a result of the start-up. Also included is plural timeout monitoring mechanisms, each of which do not start the timeout value setting mechanism at the following stage but stop it, when the timeout value set by the timeout value setting mechanism at the preceding stage is not set again even after a specific time has elapsed. A watchdog timer outputs an abnormality notice, when the timeout value set by the timeout value setting mechanism at the last stage is not set again even after a specific time has elapsed. Hierarchizing the software of the watchdog timer makes it possible to set a suitable timeout value in the watchdog timer for a higher-speed sensing of timeout and monitor the timeouts of plural systems at plural levels, which improves the monitoring capability.

Abstract: A processor having multiple functional units. The processor is capable of executing multiple instructions concurrently. An instruction issuing unit is connected to a mechanism for handling an interrupt of the processor. The interrupt handler has an instruction window (IW), which includes a vector element number (VEN) field that indicates the uncompleted elements to be executed. Upon termination of the interrupt, normal processing of the instruction issuing unit continues.

Abstract: A timer counter with multiple timers in a pipelined architecture in which the multiple timers are serviced in the pipeline. The timer counter includes a control unit having a first control section and a second control section for sequencing the servicing of each of the multiple timers in a pipeline. The first and second control sections provide a pipeline sequence of the total required service of the timer counter. The pipeline architecture allows the multiple timers to be serviced in a pipeline without increasing the overall number of clocks.

Abstract: A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.

Abstract: A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists.

Abstract: For certain classes of software pipelined loops, prologue and epilogue portions of adjacent inner loops in a nested loop can be overlapped. In this way, outer loop code, as well as inner loop code, can be software pipelined. Architectural support for software pipelined nested loops is provided by a set of loop parameter and status registers and by an implementation of loop state dependent, multiway control transfers. For loop body code compatible with two simple constraints, the present invention does not require additional code elements for disabling garbage operations during prologue and epilogue loop periods of adjacent inner loops. Nested loop control allows overlap between the epilogue period of a prior inner loop and the prologue period of a next inner loop. As a result, nested loop code can be more efficiently scheduled by a compiler for execution on a processor such as VLIW processor which provides architectural support for software pipelined nested loops, thereby providing improved loop performance.

Abstract: An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands.

Abstract: An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands.

Abstract: A difference capture circuit for determining the duration of a digital signal pulse. The difference circuit includes a branch couplable to a standard counter for activating the counter to count as a function of a system clock pulse, and a triggering circuit couplable to a standard capture register for fetching the count from the counter. The difference capture circuit may be incorporated into standard timer unit circuitry and is designed to calculate the difference between either the rise and fall times for an incoming signal, or the rise to rise time of that signal. Adding the difference capture circuit to a timing unit eliminates the need to use RAM, and minimizes processor resources, in obtaining the timing associated with a signal change.

Abstract: A method for contention-free access and management of shared timers in a multiprocessing environment allocates at least two timers, which are used by all subject threads in a "ping-pong" manner. Each thread uses a local variable to determine which of the two timers to use for blocking. At initialization, the first timer tracks a first specified time duration and the second timer tracks a second specified time duration after the first specified time duration. When the first timer expires, it is reset by the master thread to expire at a third specified time duration after the second specified time duration. Similarly, when the second timer expires, it is reset by the master thread to expire at a fourth specified time duration after the third specified time duration. This process repeats itself, so that a timer is always active in the system.