Abstract: Implementing distributed reference counters in a multiprocessor computer ensures a fair allocation of memory to each of the CPUs and quads in the system. The distributed reference counter tracks the limits of the value in each CPU, each quad, a global value and the maximum cache count allowed while mitigating a cache overflow error. The cache count is dynamically varied based upon a desired level of cache value in a node and a CPU. By modifying the fields of the data structure of the distributed reference counter to accept 64 bit integers, both the cache and target values of the data structure may be combined into one 64 bit integer. The upper 32 bits represent the cache value and the lower 32 bits represent the target value. This modified data structure now allows for both the target and cache values to be atomically manipulated as a single quantity, thereby reducing the possibility of a cache overflow situation.

Abstract: Disclosed is a Software Sanity Monitor for automatically detecting and remedying software lock-up conditions without user intervention. Users often refer to these conditions as “hangs” or “forever loops”. Although the Software Sanity Monitor uses the operating software's information, it is designed to execute independent of the operating system software; thereby, eliminating reliance on a “sane” operating system. If a “hang” condition is detected, the Software Sanity Monitor will automatically restart the system after logging the failure and, optionally, notify the user or host system.

Abstract: A method and structure for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex, which processor complex has at least one processor which processes multiple groups of data in a multiplicity of ways, is provided. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event.

Abstract: A timer processing section 10 instructs a transmission processing section 11 to control load in accordance with a time schedule stored in a program storage section 12. The transmission processing section 11 is connected to a two-wire signal line and gives a load control instruction to each terminal to which load is connected according to a time-division multiplex transmission system. The time schedule stored in a program storage section 12 is a set of the address related to the load to be controlled and the control contents and the control time of the load. Therefore, when the time set according to the time schedule is reached, the load specified by the address is controlled.

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

Abstract: A timeout mechanism that can accommodate an improved accuracy in determining the timeout of a pending transaction while conserving the amount of processing circuitry is herein disclosed. A fetch state machine is associated with each cache line. When the cache line is fetched from memory, the fetch state machine tracks the number of timeout periods that lapse before the cache line is retrieved. If a predetermined number of timeout periods lapses before the cache line is retrieved, a timeout occurs and processed accordingly.

Abstract: A system and method using a timer management module for managing a circular queue having fixed timer entries and temporary new timer entries to enable location of specified new timer entries which can then be deleted at the appropriate time in timer management operations.

Abstract: A method and system of compensating for reference frequency drift utilizes time stamps from a networked reference clock to adjust a local crystal oscillator of a communications device. In an example embodiment, a microprocessor arrangement of the communications device obtains a synchronization time stamp from a networked clock arrangement and synchronizes the local oscillator clock and a clock circuit of the microprocessor with the time stamp. After a predetermined time duration has transpired, a calibration time stamp is obtained from the network clock and the difference between the calibration time stamp and the current time of the clock circuit is extracted. The clock circuit and the networked clock arrangement are then synchronized and the local crystal oscillator is adjusted for crystal aging as a function of the difference between the calibration time stamp and the current time of the clock circuit.

Abstract: In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter in main memory is updated using the cache memory counter value. This arrangement economizes on the use of main memory access bandwidth.

Abstract: A circuit for synchronizing an internal time signal to an external time signal includes a first timer, a second timer, and a comparator. The first timer repetitively increments and outputs a first time signal. The second timer repetitively outputs a second time signal. The comparator drives an active comparator signal if the first time signal is greater than the second time signal, or otherwise an inactive signal. The first timer saves the second time signal as the first time signal in response to a control signal derived from the inactive comparator signal and repetitively increments and outputs the first time signal. Alternatively, the first timer freezes, i.e., preventing the repetitive incrementing, of the first time signal in response to a control signal derived from the active comparator signal. The second timer repetitively increments and outputs the second time signal in response to a control signal derived from the active comparator signal.

Abstract: A circuit has at least one data input, an enable input, a clock input, and an output. In one embodiment, the circuit is configured to perform a pre-charge function before an evaluate function in response to the enable input.

Abstract: Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means for receiving data at different rates. Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, include multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.

Abstract: A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits.

Abstract: An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an input/output (I/O) interface of the system. Clock signals are provided from a clock source of the data processing system to the PLL. In addition to the PLL, the initialization/reset logic circuit comprises a counter, a first timer circuit and a second watchdog timer.

Abstract: In a master unit, clock signals from a clock are counted by a counter, and clock data is generated. This clock data is outputted to a slave unit by a driver, and stored in clock data storage memory. The slave unit stores clock data received by a receiver in the clock data storage memory. A processor for a program controller of the master and slave units starts up, and executes the synchronized operation of an operating program of axes that are synchronized on the basis of clock data stored in the clock data storage memory. It is also possible to commence operation of an axis under other conditions without relying on clock data. If override is applied to clock data, override will apply only to an axis that is synchronized and operated in accordance with clock data.

Abstract: A method and apparatus for determining a computer system usage profile, and transmitting the computer system usage profile to a server which targets content to the computer system in response to the usage profile is described. A basic input output system (BIOS) module and/or an operating system module obtain computer system usage profile information by tracking events such as the frequency of re-boots, the time required to boot-up and shut-down the operating system on the computer system, the amount of time the computer system is “used”, and the frequency and amount of time the computer system is connected to the Internet. This data is collected and communicated to a profile server. The profile server targets content such as messages with graphics or informational material, etc. to the computer system based upon the computer system usage profile. In one embodiment, the content is displayed during boot-up and shut-down of the operating system.

Abstract: A method of operating a RAM memory having a plurality of memory addresses for storing data, the method being performed with a timing based on clock signals spaced by clock periods and comprising the steps of: receiving an address and a function signal specifying a function to be performed on data associated with that address; determining whether the same address has been received during a predefined number of preceding clock periods; generating a first data item representing data associated with the received address; modifying the first item according to the function signal to generate a second data item associated with the address, and writing the second data item to the address in the RAM and retaining a separate record of the last n second data items, the step of generating a first data item being performed by: (i) if the result of the determination is negative, generating the first data item to be equal to data stored by the RAM in the address, and (ii) if the result of the determination is positive, gene

Abstract: There is disclosed a process for monitoring a plurality of software timers, each having a predetermined time-out value. Each timer is assigned to one of a plurality of timer bins, wherein each timer bin has an assigned maximum and a minimum value defining the bin time range, such that the plurality of timer bin ranges contiguously subdivide the interval from zero seconds to the maximum time-out value of the plurality of timers. Each timer is assigned to that timer bin having a bin time range including the time-out value. Since a timer cannot time out before its time-out value, each timer within a timer bin is checked no less frequently than the lower time range value for the bin. As a timer approaches its time-out value, the timer is moved to lower level bins such that the time-out value is always within the timer bin range. For those timers that are reset, they are moved to a higher timer bin, again such that the time-out value falls within the timer bin range. Timers time out only from the lowest bin.

Abstract: Synchronization “states” of programmable length imposed on processing nodes are disclosed, the last of which contains an event requiring action by fully synchronized nodes. The nodes are shifted between the states using a shared timing source to ensure synchronization for the event. The first state is a “non-impending event” state where the nodes continue their routine processing; the second state is an “impending event state” closer to the event, and within which nodes “wait” for the event by suspending their routine processing. In the third state, immediately preceding the final, event state, any non-waiting nodes are interrupted for the impending event. The present invention therefore allows some node autonomy during the first state within which the nodes poll at their leisure, and during the second, “wait” state, but during the third, interrupt state, any nodes not yet arriving by polling are interrupted.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Abstract: A small-scale timer assembly includes a PWM signal generator including a selector for selecting one of a plurality of clock sources, a timer for counting based on the selected clock source to deliver an overflow signal, a comparator for comparing the count in the timer against a setting to deliver a coincidence signal, and a signal processor for generating a PWM signal based on the overflow signal and the coincidence signal, and a count controller for counting the number of overflow signals to allow the selector to select another of the clock sources. The PWM signal is used for generating a sinusoidal signal.

Abstract: Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit.

Abstract: A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node.

Abstract: A system and method are provided for counting a number of clock cycles. In one embodiment, the system comprises a cascaded series of write latches and a cascaded series of erase latches. The output of each of the write latches is electrically coupled to a respective diverting multiplexer configured to divert a counting signal from the cascaded series of write latches to the cascaded series of erase latches. In order to count a specific number of cycles of the clock, one of the diverting multiplexers is set so as to divert a logical “1” advancing along the write latches into the erase latches. A specific number of clock cycles is counted by forcing a logical “1” to advance through a predetermined number of write and erase latches. Generally, the number of write and erase latches used to count a given number of clock cycles is even. Consequently, the present invention also includes an odd latch to enable the counting of an odd number of clock cycles.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The counter counts the number of clock cycles since the previous store operation, and if enabled by the user, provides a binary signal to the memory that indicates the number of clock cycles since the previous store operation, which the memory stores with the state data. If the counter overflows before a store operation is requested, the timestamp logic may force a store operation so that the time between stores can be determined.

Abstract: A system and method for generating timing signals is disclosed. The memory mapped timer system provides the ability to easily and efficiently program a timer to generate a periodic interrupt signal to a processing unit or a one-shot interrupt signal after a defined time delay. The system also provides the ability to set a programmable rollover value for a counter to define the time between interrupts. A high-resolution counter provides the ability to generate a periodic interrupt every one hundred nanoseconds.

Abstract: A method and apparatus for controlling the flow of data through director elements of a disk drive controller are responsive to external clock signals to synchronize the internal clock timing of each director. The external clock signals are available over either a first master bus or a secondary master bus, each of the buses being connected to the director element. Each director element has circuitry which monitors the occurrence of clock pulses over the buses as well as circuitry for switching, upon the occurrence of a failure of clock pulses on the master bus, from the master bus to the secondary bus for the receipt and resynchronization of clock pulses.

Abstract: An arbitration method and circuit for control of double data rate (“DDR”) dynamic random access memory (“DRAM”) device first-in, first-out (“FIFO”) registers which allows the data path of the device to be functional over a wider range of system clock and delay locked loop (“DLL”) clock signal skews. By comparing the system and DLL clocks, the circuit and method of the present invention determines whether the DLL clock should be considered “faster” than the system clock, or “slower.” Functionally, it then attempts to force all cases into the “fast” condition until a determination is made that the amount of advance is now so fast, that data corruption in the pipeline might occur. Only in this case will it force the result to be “slow,” adding 1 cycle to the output control path, and thereby correcting the data flow.

Abstract: A method and device for measuring the response time of a circuit are described in which clocking pulses are applied to the circuit at input pads, the input pads being connected to the circuit by circuitry having substantially the same delays. By adjusting the timing of the later clock pulse relative to the earlier clock pulse until a valid output is just achieved, the response time of the circuit can be measured using a register circuit.

Abstract: A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for processing the vertex data received from the vertex input. The processor is responsive to wide word instructions.

Abstract: An output drive circuit of an output buffer circuit has a signal output line and first, second and third switching circuits connected to the signal output line at different locations thereof. Each of the first, second and third switching circuits includes one of first switching devices connected between a power source line and the signal output line, and one of second switching devices connected between the signal output line and a ground line. Each of the first, second and third switching circuits includes one of first control signal lines that turn on and off the first switching devices, respectively, and one of second control signal lines that turn on and off the second switching devices, respectively. Drivabilities of the first and/or the second switching devices in the switching circuits are set to gradually increase in a specified order.

Abstract: A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysterisis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system.

Abstract: A dual-timer process control system (10) includes a process control timer (28) used to limit the number of iterations of a procedure whose duration is controlled by an iteration timer (22). At system (10) startup, the iteration timer (22), process control timer (28) and procedure are started. The iteration timer (22) times out after a first predetermined amount of time and provides an iteration stop signal to stop the procedure. The iteration timer (22) and procedure are started again if the process control timer (28) has not timed out. If the iteration timer (22) and the process control timer (28) have timed out, the process is performed n−1 additional times, where n is the minimum number of iterations of the procedure.

Abstract: A method and apparatus are disclosed for calculating and validating the differential time between the broadcasting of an event and the time at which a user responds. The event may include, for example, the announcement of an auction or a contest on a television program. The differential time for each end-user response is calculated by each end-user device. The user response can be reported back to the service provider in a secure and reliable off-line or real-time manner. Each end-user device can include a secure time-keeping device having a secure clock/calendar feature for calculating the differential time between presentation of the event and the user response. A user is prevented from recording a particular event and thereafter replaying the recorded event and responding to the replayed event, to thereby alter the effective response time. Local and global presentation time information are compared to ensure that each user responds to the initial, real-time event and not a replay.

Abstract: Image signals of a progressive scan image are formed by arranging the image signals in each field in a normal order, even when the image signals in an interlace system are input, while a phase difference between a vertical synchronization signal and a horizontal synchronization signal is not constant. A switch sequentially selects a field memory in a field memory unit every time a vertical synchronization signal Vsync is input. In the selected field memory, a timer value of a timer, which is from an input of the vertical synchronization signal to an input of each horizontal synchronization signal, is written together with an image signal subsequent to each horizontal scanning signal. A sort processing unit reads image signals from two field memories in which the timer values and the image signals were recently written, arranges the image signals in order of the timer values corresponding to the image signals, and writes the image signals in a frame memory.

Abstract: The present invention relates to a system and method for practically measuring cycle by cycle repeatable system behavior. A set of system parameters is selected for tracking by a group of counters which preferably operate to condense the system state trajectory into a manageable set of counter values thereby forming a counter state. Preferably, repeatability of the counter state practically assures repeatability of the system state trajectory. System repeatability is helpful for debugging purposes since definite identification of a system defect is made easier when a test program failure caused by exercising a defect is repeatable. A test program may be varied for successive runs on a computer system by employing a different randomly or pseudo-randomly generated seed for each run and preferably exercising as many features of the computer system as possible in order to search for defects in the computer system.

Abstract: A memory mapped programmable output generator, capable of producing events such as creating complex waveforms, triggering analog to digital and digital to analog conversions, and generating processor interrupts is disclosed. These events are considered high speed since they are timed relative to a high-speed clock and require minimal processor over head. The event generator may be embodied as either a peripheral to a microcontroller or as a separate circuit. In its preferred embodiment, the output generator is a peripheral device on a microcontroller and uses a dedicated programmable, reloadable timer which is inaccessible to other blocks. Events are loaded in a serial format, where only one event is active at a given time. These events are sequenced through address pointers associated with each event. Once a given event is completed, the output generator loads the next event from a next address pointer.

Abstract: A method and apparatus for a propagation delay and time calibration. The apparatus includes a ring oscillator having a first set of elements. The apparatus also includes delay units. The ring oscillator is used to generate a clock signal used to measure the delay in signals received at the delay blocks. In the depicted examples, the clock signal generated by the ring oscillator is used to run a counter that counts the delay between a transition in a data signal and a reference signal. Each of the delay units includes a second set of elements matching those of the first set of elements in the ring oscillator. The elements in the set of elements are selected such that they track the period of the ring oscillator signal generated by the ring oscillator. The delay units are used to implement the desired delay.

Abstract: For triggering actions synchronous with a system clock in an electronic system comprising a management processor, a program memory and peripheral units, the sequencer comprises: an instruction register including a date field for containing an instruction execution date, an instruction code field and a data field, means for loading the instruction register from the program memory via a DMA channel, a comparator receiving a current date obtained from the system clock and the execution date contained in the date field of the instruction register, and a control logic unit for decoding the contents of the instruction code and data fields of the instruction register and triggering actions deduced from such decoding at the time the comparator shows that the current date has reached the execution date in the peripheral units and without intervention by the management processor.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: In a data processing system a method and apparatus is provided for discriminating between digital signals of a plurality of different rates by monitoring the pulse width and repetition rate of such signals. The digital signals are continuously monitored to determine whether a single pulse or multiple pulses have been detected within a preselected time period. If only a single pulse or a portion thereof has been detected within the preselected time period a first type of control signal is generated. If multiple pulses or portions of multiple pulses have been detected within the preselected time period a second type of control signal is generated.

Abstract: A synchronizing device and a synchronizing method whose constitution is simple and whose operation is easy to be stabilized are provided. A subtracter subtracts a value of a read pointer which calculates number of data read-out from a memory device from a value of a write pointer which calculates number of data written in the memory device to obtain subtraction value, thus causing the subtraction value to be given to a judging unit as detection data remaining quantity. The judging unit outputs comparison result signal while comparing detection data remaining quantity with reference value. A number of data increasing/decreasing unit receives data from a decoder for decoding data of the memory device. The number of data increasing/decreasing unit causes remaining quantity of data of the memory device to be prescribed value with data reading-out speed of the memory device controlled in such a way that it controls quantity of data outputted, while replying to comparison result signal from the judging unit.

Abstract: A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting the rising edge of the input signal and one for detecting its falling edge. The input signal is typically assumed to have some known nominal clock rate, but its exact frequency and phase (timing of transitions) are not known. Each of the two metastability resolvers comprises two branches of cascaded flip flops, each clocked off the rising edge and falling edge of a fast clock. Each metastability resolver functions to output an edge event signal and a clock phase signal indicating which edge of the fast clock the rising (or falling) edge of the data signal was closer to. The edge event signals are used to start and stop a counter clocked off the fast clock. The clock phase is used to correct (i.e. compensate) the counter value depending on which half cycle of the fast clock the rising and falling edge of the data signal arrived in.

Abstract: The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an “initial state” of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an “initial state” of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer.

Abstract: Method for maintaining an execution interval for a task requestor to a DMA. A timer is provided with two counters, one (34) to maintain the execution interval and the second (32) to track the execution time of a task in the DMA. Each task has a predetermined execution time allowance. A task acknowledge (TACK) signal enables the tracking. A task request signal (TREQ) is generated during each execution interval until the execution time allowance is completed. The length of the second counter is less than the first counter. In one embodiment, if the first counter expires before the execution time allowance is completed, a task error signal (TERR) is illustrated.

Abstract: According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be “close”, “open”, “write” or “read”. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page.

Abstract: A method and apparatus to provide accurate and automated timing of firmware routines, such as initialization tasks at boot time, is provided. Since each task sends a progress indicator code to a display buffer when it starts to run, by saving processor time stamps at the time these codes change, it is possible to calculate and store the time duration for each routine. In the case of system initialization, these time durations can be an indication of problems if they are much longer than normal or an indication of excessive, inefficient, or ineffective processing that might be speed up in order to reduce the total boot time.

Abstract: In order to analyze the conditions leading to a stall or wait state in a digital signal processing unit, READY signals, that are typically applied to the execution unit of a central processing unit, are applied to external conductors. The external conductors are applied to input terminals of a logic “AND” gate. The output terminal of the logic “AND” gate is provides a logic “1” in a no-stall condition and logic “0” in a stall condition. The output signals o f the logic “AND” gate are stored in a memory unit and can be retrieved to determine when a stall condition occurred. The external conductors also apply the READY signals to a stall analyzer unit. The stall analyzer unit identifies the specific condition causing the stall condition by which external conductor has the logic “0” signal applied thereto. An indicia of this stall condition is stored in the memory unit.

Abstract: Provided is a method and components of an apparatus for implementing a method for assisting with adjustment of the timing of user-inactivity-dependent changes of operational state of an apparatus, by identifying user interactions following a change of operational state, determining when the user's interactions or lack of interaction following the change of state suggest that a change to an inactivity time period is desirable, and either automatically changing the inactivity time period or prompting the user to change the time period.

Abstract: A method to intercept operating system messages in an informational processing device, the method comprising the steps of: waiting for an operating system message; determining if the message corresponds to a previously selected operating system message; and performing an operating system call that has been previously mapped to the selected operating system message.