Abstract: A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

Abstract: A method, system, and computer program product to aggregate code change requests for a continuous integration pipeline. The method may include receiving a plurality of code change requests (CCRs) for a software product that are to be processed by a continuous integration (CI) pipeline. The method may also include obtaining all functions of the software product tested by all testcases in a testcase set. The method may also include selecting a plurality of groups of testcases from the testcase set, each group of the plurality of groups of testcases corresponding to a CCR from the plurality of CCRs. The method may also include identifying at least two groups of testcases from the plurality of groups of testcases without overlapping code. The method may also include aggregating each CCR that corresponds to the at least two groups of testcases into a single CCR group.

Abstract: Technology described herein is generally directed towards an efficient process to selectively boot (e.g., initialize, re-boot, re-initialize and/or the like) one or more nodes of a server node system based on contextual information that can be automatically acquired. In an embodiment, a system can comprise a processor, and a memory that stores executable instructions that, when executed by the processor, can facilitate performance of operations. The operations can comprise monitoring operational activity of a node of a software-defined object storage system. The operations can comprise, in response to occurrence of a negative activity event determined based on a result of the monitoring, determining whether a node reboot of the node is to be implemented. The operations can comprise, based on the operational activity analyzed, setting a reboot flag indicating that the node reboot is to comprise a reboot of less than all components of the node.

Abstract: An error information processing method includes, in response to a memory error triggering an interrupt, collecting error information of the memory error that includes a first memory area where the memory error occurs, obtaining a second memory area for writing log information, determining whether the second memory area contains the first memory area, and, in response to determining that the second memory area contains the first memory area, skipping a process of writing the log information into the second memory area.

Abstract: Media stream monitoring includes initiating, by a processing device, a media-stream-monitoring-application configured to monitor a plurality of media streams including packetized media content. A plurality of media stream records associated with the plurality of media streams are obtained. The media stream records include addresses used to connect to the plurality of media streams The media-stream-monitoring-application attempts to connect to a first media stream associated with a first media stream record, wherein connecting to the first media stream includes requesting a sample packet from the address associated with the first media stream. An error associated with the sample packet is identified. At least in part based on identifying the error associated with the sample packet: disconnecting from first media stream; generating an error report; and discarding the first media stream record.

Abstract: An example system includes a plurality of scriptable devices, each of which exposes an interface. The system may also comprise a medium storing data indicating, for each of a mapped plurality of device operations, one or more inputs to provide to a corresponding device from the plurality of scriptable devices and a conversion between that device operation and a corresponding application command. In such a system, the medium may also store a plurality of scripts, each of which may have a corresponding scriptable device from the plurality of scriptable devices and may comprise a set of device operations. The system may also comprise a computer to repeatedly preform an operation cycle comprising determining whether an application command should be executed and, when it should, generating a globally unique identifier corresponding to that command and adding that globally unique identifier and a device operation corresponding to that command to a log.

Abstract: Systems, methods, and non-transitory computer readable media are provided for facilitating improved defect resolution. Defect information and defect criteria information may be obtained. The defect information may identify defects of software and/or hardware in development. The defect criteria information may define one or more criteria for measuring the defects. The defects may be measured based on the one or more criteria. A defect analysis interface may be provided. The defect analysis interface may list a limited number of the defects based on the measurements of the defects. The defect analysis interface may provide costs (e.g., computing resources, time, personnel) of solving the defects.

Abstract: A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.

Abstract: The techniques described herein may provide techniques for precise and fully-automatic on-site software failure diagnosis that overcomes issues of existing systems and general challenges of in-production software failure diagnosis. Embodiments of the present systems and methods may provide a tool capable of automatically pinpointing a fault propagation chain of program failures, with explicit symptoms. The combination of binary analysis, in-situ/identical replay, and debugging registers may be used together to simulate the debugging procedures of a programmer automatically. Overhead, privacy, transparency, convenience, and completeness challenges of in-production failure analysis are improved, making it suitable for deployment uses.

Abstract: A data stream monitor including a processor and associated memory initiates a data stream monitoring application. The data stream monitoring application is configured to test a plurality of data streams, and obtains a plurality of data stream records associated with the plurality of data streams to be tested. The data stream monitor writes a lastRecord indicator to a file. The lastRecord indicator identifies a last data stream to have been tested. The data streams are tested, and the lastRecord indicator is updated each time a subsequent data stream is tested. The data stream monitor determines whether a value of the lastRecord indicator has changed from a previous value. In response to determining that the value of the lastRecord indicator has not changed, testing of the plurality of data streams is restarted.

Abstract: Disclosed embodiments include a processing device having a debug controller that issues a context-sensitive debug request. The context-sensitive debug request includes at least one conditional criteria. A processing core receives the debug request, determines whether all of the at least one conditional criteria are true, and services the debug request when all of the at least one conditional criteria are true by accessing a data location indicated in the debug request. The servicing of the debug request may be performed in real-time mode without suspending the processing device, and the accessing can be a read or a write operation depending on the type of access indicated in the debug request. The conditional criteria may include one or more of a processor mode condition, a virtual machine identifier condition, and a debug context condition.

Abstract: A computer receives a log file, where the log file comprises records associated with the instructions in a source code. The computer loads, using a debugger, the log file and the source code. The computer receives a loading address from the log file. The computer updates a debugging data format (DWARF) with the one or more records of the log file, where the DWARF is accessed using the loading address and comprises one or more data structure entries. The computer identifies a calling address from the log file and identifies the one or more data structure entries associated with the calling address.

Abstract: Disclosed herein are techniques for visualizing and configuring controller function sequences.

Abstract: A stream monitor can request a streaming media server to send stream records associated with streams currently being served. The stream monitor uses the stream records to test streams being served by the streaming media server. The stream monitor can concurrently test multiple streams for connection errors, silence errors, metadata errors, and other errors. The stream monitor initiates a data stream monitoring application, initiates a heartbeat timer to produce a periodic heartbeat signal and delivers, to a host webpage, a last data stream record to be tested in conjunction with the heartbeat signal. When a periodic heartbeat signal is not received in a timely manner the monitor restarts the stream testing application at the last data record tested.

Abstract: A capability-based data processing architecture (100) integrating an attesting module (120) are disclosed, together with subroutines for: securing the booting phase of a replicated or unreplicated subsystem (150) of computing units (130, 140) in the architecture and attesting to same; for adding and removing computing units (140) to and from booted systems 150; for relabelling authentication tokens when the booted subsystem (150) comprises computing units; for sealing and unsealing a memory storing data structures that are processed by the other subroutines described herein; and for recovering a booted subsystem (150) beset by faults.

Abstract: The present disclosure covers systems and methods for collecting and analyzing analytics data for a plurality of online user interactions and aggregating the analytics data to determine sentiment scores and generate a presentation of a path of interactions. For example, the systems and methods analyze the analytics data to identify attributes of the online user interactions and determine, based on the identified attributes, a sentiment score for each of the plurality of online user interactions. In addition, the systems and methods aggregate the plurality of online user online user interactions to identify an interaction path commonly experienced by the users of the interactions. Further, the systems and methods generate and provide an interactive presentation including a visualization of the interaction path and associated ranges of sentiment scores associated with types of online user interactions that make up the interaction path.

Abstract: Techniques are disclosed relating to the handling of exceptions generated by illegal instructions in a processor. In an embodiment, a processor may be configured to fetch instructions defined according to an instruction set architecture (ISA). The ISA may include a set of uncompressed instructions and a set of compressed instructions. The processor may further be configured to, upon detecting a given one of the set of compressed instructions, cause a copy of the given compressed instruction to be saved and convert the given compressed instruction to a corresponding given uncompressed instruction. The processor may also be configured to detect that the given uncompressed instruction is illegal and was converted from the given compressed instruction, and based at least in part on these, cause an illegal instruction exception to be generated using the copy of the given compressed instruction.

Abstract: Methods, systems, and computer program products are provided for detecting a browser hang condition and causing the browser to enter into a mitigation state. For instance, a window or tab of the browser executes via a first thread of the browser, and third-party code executes via a second thread of the browser. The first thread issues a hang resistance message to the second thread and waits for a response from the second thread. The second thread processes the hang resistance message after processing all other messages in its queue. Thus, if the first thread receives the response, the first thread determines that the second thread has not entered into a hang condition. However, if the first thread does not receive the response, the first thread determines that the second thread has entered into a hang condition and subsequently causes the browser to enter the mitigation state.

Abstract: Systems and methods are provided herein for preventing interruptions to a media viewing activity caused by operations performed in a household by network-connected devices. A media guidance application may determine that operations are being performed by an IoT device and may cause an interruption to media viewing. The media guidance application may prevent the interruption by delaying or otherwise handling the operation or by notifying another user of the interruption.

Abstract: A data storage device may be configured to direct access to at least a portion of a host memory of a host device. For example, the data storage device may store data at the host memory, such as data predicted to be subject to a read request from the host device. When the data storage device receives a read request from the host device to read the data, the data storage device may send an indication to the host device to enable the host device to read the data directly from the host memory.

Abstract: In a method of operating an image sensor, the image sensor includes a pixel array and a plurality of column driving circuits that are connected to a plurality of columns of the pixel array. A test operation is performed by applying a test pattern to the plurality of column driving circuits while changing a level of a well-bias voltage applied to a transistor included in the plurality of column driving circuits. A bias setting operation for setting the level of the well-bias voltage is performed based on a result of the test operation. An image capture operation for detecting incident light and generating a frame image is performed based on the pixel array, the plurality of column driving circuits and the well-bias voltage set by the bias setting operation.

Abstract: A stream monitor can request a streaming media server to send stream records associated with streams currently being served. The stream monitor uses the stream records to test streams being served by the streaming media server. The stream monitor can concurrently test multiple streams for connection errors, silence errors, metadata errors, and other errors.

Abstract: Reconfigurable processors and methods for collecting computer program instruction execution statistics are disclosed. According to an aspect, a method includes providing a reconfigurable processor configured to execute a set of central processing unit (CPU) instructions that each have a function. The method also includes modifying the function of one or more of the CPU instructions that identifies an instruction address and a destination address pair of the CPU instruction(s) based on a defined test case. Further, the method includes using the reconfigurable processor to execute the set of CPU instructions. The method also includes identifying an instruction address and destination address pair of the CPU instruction(s) having the modified function when the CPU instruction(s) having the modified function is executed during execution of the set of CPU instructions.

Abstract: In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.

Abstract: An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains.

Abstract: Systems and methods are disclosed for debug event handling. For example, methods may include receiving a request from a client device. Methods may include, responsive to receiving the request, identifying a set of instructions to be executed, wherein the set of instructions is associated with at least one breakpoint. Methods may include initiating execution of the set of instructions. Methods may include pausing execution of the set of instructions when an instruction of the set of instructions associated with a breakpoint is reached. Methods may include, after the breakpoint is reached and before a new request is received from the client device, transmitting, to the client device, a message that indicates that a breakpoint has been reached. Methods may include terminating execution of the set of instructions responsive to determining that a debugger interface on the client device is no longer available to control execution of the set of instructions.

Abstract: A stream monitor can request a streaming media server to send stream records associated with streams currently being served. The stream monitor uses the stream records to test streams being served by the streaming media server. The stream monitor can concurrently test multiple streams for connection errors, silence errors, metadata errors, and other errors.

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Abstract: According to an example, machine readable instructions backward compatibility may include determining changes between first and second sets of machine readable instructions, and generating a backward compatibility switch. The backward compatibility switch may be implemented in the second set of machine readable instructions to selectively revert functionality to functionality of the first set of machine readable instructions.

Abstract: A method receives start commands for starting end-to-end testing of a live multi-tenant system that hosts shared services for multiple tenants; executes multiple test scripts for generating controller commands in response to the start commands, the executing the test scripts generating respectively synthetic transaction inputs; provides the synthetic transaction inputs to the live multi-tenant system, the live multi-tenant system configured to use the synthetic transaction inputs to perform respectively multiple synthetic transactions involving multiple destinations in the live multi-tenant system, the live multi-tenant system configured to generate respectively multiple test results in response to the multiple synthetic transactions; receives and evaluates the test results generated by the live multi-tenant system to test end-to-end performance conditions of the multi-tenant system; and generates one or more alerts upon recognizing an alert trigger condition based upon the evaluating of the test results.

Abstract: Migrating interrupts from a source I/O adapter of a source computing system to a destination I/O adapter of a destination computing system, includes: collecting, by a source hypervisor of the source computing system, interrupt mapping information, were the source hypervisor supports operation of a logical partition executing on the source computing system and the logical partition is configured to receive interrupts from the source I/O adapter; configuring, by the destination hypervisor of the destination computing system, the destination computing system with the interrupt mapping information collected by the source hypervisor; placing, by a destination hypervisor of the destination computing system, the destination I/O adapter in an error state; migrating the logical partition from the source computing system to the destination computing system; and restarting the logical partition on the destination computing system, including recovering, by the logical partition, from the error state.

Abstract: An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

Abstract: An apparatus for providing an arrangement pattern includes an input unit configured to receive an input of group information of groups, the groups comprising a plurality of components having the same function and being classified based on a predetermined standard; an arrangement pattern calculation unit configured to determine an arrangement pattern for arranging the plurality of components on a printed circuit board (PCB) so that first components of a first group of the groups are dispersedly arranged amongst the plurality of components based on the group information of the groups; and an output unit configured to output the determined arrangement pattern.

Abstract: Disclosed herein are technologies for remote debugging in mobile web applications using a platform-independent debugging proxy server. Particularly, the debugging proxy server acts as an intermediary by fetching and performing instrumentation on a requested webpage by a target browser. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

Abstract: The present disclosure relates to a method and system for detecting root cause for software failure and hardware failure. The system comprises a debugging unit with one or more preconfigured communication protocols. The debugging unit identifies one or more debugging issues and performs protocol level transactions with the hardware, participating in the system integration, through a suitable communication protocol. The debugging unit also determines status of the protocol level data transaction based on whether a data read failure has occurred during this transaction. The status is unsuccessful when there is a data read failure in the data transaction and the status is successful otherwise. The root cause for the failure is detected to be one of the hardware components when the status is unsuccessful and the software application when the status is successful. Finally, the detected root causes are resolved using appropriate techniques.

Abstract: Embodiments of the present invention disclose an approach for inserting code into a running thread of execution. A computer sets a first set of bits to a first value, wherein the first value indicates that a first set of instructions should be inserted onto a stack. The computer executes a second set of instructions associated with a first safepoint, wherein the second set of instructions comprises one or more instructions to determine if the first set of bits is set to the first value. The computer determines that the first set of bits is set to the first value, and the computer inserts the first set of instructions onto the stack.

Abstract: Described are a system and method for performing an automated quality assessment on a software program under test. A test automation system executes a test on a software program Data related to the test is automatically collected. The data includes first information determined by the test automation system in response to executing the test. The data further includes second information related to the test and received from a source other than the test automation system. The first information is analyzed. A quality assessment of the software program is generated from the analyzed first information and from the second information.

Abstract: A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program including an exception-causing instruction based on a test template; executing a first instruction at a first operating state as the test program is executed; stopping the execution of the test program and performing a fixed instruction sequence included in the exception handler when the exception-causing instruction is executed during the execution of the test program; and resuming the test program from a second instruction at a second operating state set after the fixed instruction sequence is performed, the second instruction corresponding to an address adjacent to an address of the exception-causing instruction.

Abstract: A server system includes at least one server and a server cabinet. The at least one server includes a first connection port and a baseboard management controller which detects a connection state of the first connection port and according to the connection state, outputs a data signal or a warning signal. The server cabinet includes chambers for containing the at least one server, and the chamber includes a second connection port and a storage unit. The storage unit stores data. When the connection state specifies that the first connection port couples to the second connection port, the baseboard management controller reads the data stored in the storage unit, to output the data signal. When the connection state specifies that the first connection port does not couple to the second connection port, the baseboard management controller outputs the warning signal.

Abstract: Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by address. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by address. The method includes reading sample-point addresses from a sample-point address array, and comparing, by a processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor. The method further includes recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses. Run-time instrumentation information is obtained from the sample point. The method also includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group.

Abstract: A stream monitor can request a streaming media server to send stream records associated with streams currently being served. The stream monitor uses the stream records to test streams being served by the streaming media server. The stream monitor can concurrently test multiple streams for connection errors, silence errors, metadata errors, and other errors.

Abstract: Embodiments of the present invention disclose an approach for inserting code into a running thread of execution. A computer sets a first set of bits to a first value, wherein the first value indicates that a first set of instructions should be inserted onto a stack. The computer executes a second set of instructions associated with a first safepoint, wherein the second set of instructions comprises one or more instructions to determine if the first set of bits is set to the first value. The computer determines that the first set of bits is set to the first value, and the computer inserts the first set of instructions onto the stack.

Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

Abstract: The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.

Abstract: Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.

Abstract: A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.