Fault Locating (i.e., Diagnosis Or Testing) Patents (Class 714/25)
  • Patent number: 10353810
    Abstract: In one respect, there is provided a system that includes at least one processor and at least one memory. The memory may include program code that provides operations when executed by the at least one processor. The operations may include: identifying one or more functionalities of a software program that are invoked via a user interface; identifying a plurality of test cases for testing the one or more functionalities; generating a minimized test suite by at least eliminating, from the plurality of test cases, a redundant test case, wherein the redundant test case tests a same functionality as at least one other test case from the plurality of test cases; and testing, based at least on the minimized test suite, the software program. Related methods and articles of manufacture, including computer program products, are also provided.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 16, 2019
    Assignee: SAP SE
    Inventors: Anandh Varadarajan, Kushagra Jain, Rekha Kanakasabapathy, Mohan Rajarathinam
  • Patent number: 10348591
    Abstract: A method for detecting connectivity of user node interface in a virtual private network includes: acquiring a configuration parameter used for detecting connectivity of a user node interface between a source address and a destination address in the virtual private network; transmitting an Internet Control Message Protocol (ICMP) request packet from the source address to the destination address through the configuration parameter, and receiving an ICMP response packet responded by the destination address; and after receiving the ICMP response packet responded by the destination address, calculating a round-trip time value of a link between the source address and the destination address, and then collecting statistics on the connectivity of the user node interface between the source address and the destination address according to the round-trip time value obtained by calculation.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: July 9, 2019
    Assignee: ZTE CORPORATION
    Inventors: Yan Zhang, Rui Wu
  • Patent number: 10324923
    Abstract: Techniques are described for identifying changes in the structure or behavior of a data feed generated by a source process. The changes may be identified based on metadata that describes the structure or behavior of the data in the data feed. A baseline set of metadata may be determined and stored for the data feed, the baseline metadata describing the data feed during a first time period. A current set of metadata may then be determined for the data feed, the current metadata describing the data feed during a second time period subsequent to the first time period. Variations in the current metadata relative to the baseline metadata may be described in results information sent in a notification.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: June 18, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Paparao Chinthagunti
  • Patent number: 10317896
    Abstract: Methods and apparatus to use vibration data to determine a condition of a process control device are disclosed. An example apparatus includes a vibration monitoring circuit to: collect first vibration data associated with a process control device during calibration of the process control device; calculate an operating threshold of the process control device based on the first vibration data; collect usage information associated with the process control device, the usage information indicative of a remaining portion of useful life associated with the process control device; adjust the operating threshold based on the usage information, the adjusted operating threshold reflective of the remaining portion of useful life associated with the process control device; and determine a condition of the process control device if second vibration data associated with the process control device collected after the calibration exceeds the adjusted operating threshold.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 11, 2019
    Assignee: FISHER CONTROLS INTERNATIONAL LLC
    Inventors: Shawn William Anderson, Roger Anders, Ted Dennis Grabau
  • Patent number: 10320837
    Abstract: Managing denial-of-service attacks by intercepting a query by a client software executed by a computer to resolve at a DNS server a network address associated with a target computer system, determining if the DNS server is under denial-of-service attack, and providing to the client software, in response to the query, an alternate network address associated with the target computer system if the DNS server is under denial-of-service attack.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael Boodaei
  • Patent number: 10320504
    Abstract: A method and system for monitoring video assets provided by a multimedia content distribution network (MCDN) includes an expert test monitoring platform (ETMP) configured to emulate MCDN client systems at a facility of an MCDN service provider. The ETMP may be used to obtain remote control response metrics, along with internal performance data, for client systems in the ETMP. Historical metrics and historical data may be logged along with the release version for the client systems, which may then be used to correlate operational performance when analyzing client system characteristics.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: June 11, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Hung John Pham
  • Patent number: 10320936
    Abstract: Provided are a computer program product, system, and method for populating a secondary cache with unmodified tracks in a primary cache when redirecting host access from a primary server to a secondary server. Host access to tracks is redirected from the primary server to the secondary server. Prior to the redirecting, updates to tracks in the primary storage were replicated to the secondary server. After the redirecting host access to the secondary server, host access is directed to the secondary server and the secondary storage. A secondary cache at the secondary server is populated with unmodified tracks in a primary cache at the primary server when the host access was redirected to the secondary server to make available to the host access redirected to the secondary server.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
  • Patent number: 10310963
    Abstract: Facilitating recording a trace file of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, index bits for the cache line are set. Setting the index bits includes one of: (i) setting the bits to a reserved value when the operation is a write operation and tracing is disabled, (i) setting the bits to an index of the processing unit when the operation is a write operation and the bits are already set to a value other than the index of the processing unit, or (iii) setting the bits to the index of the processing unit when the operation is a read operation that is consumed by the processing unit and the bits are already set to a value other than the index of the processing unit.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola
  • Patent number: 10303488
    Abstract: Performance of a new system may be optimized to run a legacy application written for a legacy system. Performance information for the legacy application is recorded or derived while running the legacy application on the new system. Performance characteristics for the legacy application running on the new system are determined by analyzing the performance information. The performance characteristics include one or more key performance metrics and other performance information. The key performance metrics must be met when the legacy application is run on the new system. The other performance information is useful for adjusting one or more operating parameters of the new system when running the legacy application on the new system. The one or more operating parameters are adjusted so that the one or more key performance metrics are met.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 28, 2019
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventors: Mark Evan Cerny, David Simpson
  • Patent number: 10296449
    Abstract: Recording an application test can include creating a number of recordings that define a number of interactions with an application under test (AUT), wherein the number of recordings are created serially. Recording an application test can include replaying each of the number of recordings while the number of recordings are being created to determine an outcome of a test. Recording an application test can include analyzing and reporting the outcome of the test.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 21, 2019
    Assignee: ENTIT SOFTWARE LLC
    Inventors: Yehuda Sabag, Svetlana Aronov
  • Patent number: 10284450
    Abstract: A method receives start commands for starting end-to-end testing of a live multi-tenant system that hosts shared services for multiple tenants; executes multiple test scripts for generating controller commands in response to the start commands, the executing the test scripts generating respectively synthetic transaction inputs; provides the synthetic transaction inputs to the live multi-tenant system, the live multi-tenant system configured to use the synthetic transaction inputs to perform respectively multiple synthetic transactions involving multiple destinations in the live multi-tenant system, the live multi-tenant system configured to generate respectively multiple test results in response to the multiple synthetic transactions; receives and evaluates the test results generated by the live multi-tenant system to test end-to-end performance conditions of the multi-tenant system; and generates one or more alerts upon recognizing an alert trigger condition based upon the evaluating of the test results.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 7, 2019
    Assignee: Zuora, Inc.
    Inventors: Xuquan Lin, Tinglan Kung, Sahin Habesoglu
  • Patent number: 10282275
    Abstract: Management of an extensive code database having multiple user tenants building code is provided. A request to check-in code is received, and a build and validation to check-in the update to a user's code is performed. The validation results in indication of an error due to a bad state of the system that performed the build. The build machine is rebooted, and a second build is performed. Optionally, a user is prompted during a grace time period to cancel the corrective action of rebooting the build machine. Optionally, the validation error may be indicated as a product issue, a network issue, or a known limitation in the compiler. Optionally, other corrective actions such as preventing retrying the build and escalating the error may be taken. Optionally, the build may be prevented when the check-in includes code that produced an error on a previous build.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 7, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Carlo Rivera, Derek Ying Kit Leung, Barrett E. Amos
  • Patent number: 10267857
    Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar Goel, Abhishek Koneru, Tri Ngo, Yun-Han Lee
  • Patent number: 10268495
    Abstract: A computer device may include logic configured to receive, from a user device via a network, a manufacturer-independent request intended for a target device; identify a virtual device model instance associated with the target device; and identify a virtual device model associated with the identified virtual device model instance. The logic may be further configured to select a manufacturer adapter based on the identified virtual device model instance and the identified virtual device model; generate a manufacturer-specific request for the target device based on the received manufacturer-independent request and the selected manufacturer adapter; and send, via the network, the generated manufacturer-specific request to the target device.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 23, 2019
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Zhong Chen, Lin Zhu, Jianxiu Hao
  • Patent number: 10255173
    Abstract: A content variation experiment system for performing variation testing of web pages is disclosed. A content provider receives requests for a web page undergoing an experiment. The content provider determines a variation from a plurality of variations of the web page to provide to the user. The content provider makes the determination without sending a network request to an experiment definition system used to define the experiment thereby reducing network latency.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 9, 2019
    Assignee: Optimizely, Inc.
    Inventors: Vijay Jambu, John Provine, Rama Ranganath, Ali Abbas Rizvi
  • Patent number: 10241937
    Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Layne A. Berge, Benjamin A. Fox, Wesley D. Martin, George R. Zettles, IV
  • Patent number: 10242179
    Abstract: A high-integrity multi-core heterogeneous processing environment and methods for high integrity computing on multi-core heterogeneous processing environments are disclosed. A multi-core heterogeneous processing environment may include an application processor with one or more processing cores and an integrity tester for executing integrity kernels on the application processor. The multi-core heterogeneous processing environment may further include an integrity processor having a different architecture than the application processor and an integrity manager operating on the integrity processor. The integrity manager may dynamically generate integrity kernels to test the functionality of the application processor prior to and/or subsequent to the execution of critical programs on the application processor.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: March 26, 2019
    Assignee: Rockwell Collins, Inc.
    Inventors: Matthew P. Corbett, Jason R. Owen, Nicholas H. Bloom
  • Patent number: 10243779
    Abstract: A system is provided for clustering events. At least one engine is configured to receive message data from managed infrastructure that includes managed infrastructure physical hardware which supports the flow and processing of information. The at least one engine is configured to determine common characteristics of events and produce clusters of events relating to the failure of errors in the managed infrastructure. Membership in a cluster indicates a common factor of the events that is a failure or an actionable problem in the physical hardware managed infrastructure directed to supporting the flow and processing of information. The at least one engine is configured to create one or more situations that is a collection of one or more events or alerts representative of the actionable problem in the managed infrastructure. A situation room includes a collaborative interface (UI) for decomposing events from managed infrastructures.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 26, 2019
    Assignee: Moogsoft, Inc.
    Inventors: Philip Tee, Robert Duncan Harper, Charles Mike Silvey
  • Patent number: 10222420
    Abstract: Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
  • Patent number: 10209299
    Abstract: Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 19, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhen Xu, Yuqing Zhao, Xiaocheng Liu
  • Patent number: 10205486
    Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing system to cause the processing system to perform a method that includes sending a data testing signal through a data lead of a cable via a first interface, sending a power signal through a power lead of the cable via the first interface, receiving and analyzing the data testing signal from the data lead of the cable via a second interface, and receiving and analyzing the power signal passing through the power lead of the cable via the second interface.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emmanuel Barajas Gonzalez, Shaun E. Harrington, Benjamin K. Rawlins
  • Patent number: 10203370
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jyotirmoy Saikia, Rohit Kapur
  • Patent number: 10200536
    Abstract: Aspects of the subject disclosure may include, for example, determining a service request and facilitating a first service session whereby customer equipment accesses the first service session via a first contact mode. A first contact resource is associated with the first service session, participating in a communication exchange with the customer equipment via the first service session according to the first contact mode. A customer inquiry is determined via the first customer service session. The customer inquiry is analyzed and a second customer contact resource is associated with the first service session based on the analysis of the customer inquiry. The second contact resource participates in the communication exchange via the first service session and according to a second contact mode. Other embodiments are disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 5, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Reuben Klein, Mazin E. Gilbert
  • Patent number: 10191481
    Abstract: A numerical controller in the present invention includes a bus trace circuit configured to fetch a bus cycle satisfying preset conditions, an alarm history, an alarm data acquisition table in which whether to acquire trace data is recorded for each alarm, and a trace circuit setting table in which fetching conditions of the bus cycle of the bus trace circuit are recorded for each alarm, and identifies an alarm for which the trace data is to be fetched from the alarm history and the alarm data acquisition table, reads the fetching conditions of the bus cycle corresponding to the alarm from the trace circuit setting table, sets the fetching conditions to the bus trace circuit, and acquires the trace data of the bus cycle based on the fetching conditions that are set through the bus trace circuit.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: January 29, 2019
    Assignee: FANUC CORPORATION
    Inventor: Tomomasa Nakama
  • Patent number: 10192053
    Abstract: The present invention provides a method, apparatus, system, device and a computer storage medium for treating virus. A client reports a scan log to a cloud service platform, and/or reports virus family information to the cloud service platform after the virus family information is identified based on the scan log. The cloud service platform identifies the scan log to obtain virus family information, and/or issues the virus removal instruction corresponding to the virus family information to the client after receiving the virus family information from the client, for the client to execute the virus removal instruction. Compared with the method of simply performing the behavior analysis and deleting files by the client, it is more advantageous that the method of the present invention issues virus removal instructions regarding the virus family information from the cloud, the virus treating is more personalized and precise, and the security of the machine system is improved.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 29, 2019
    Assignee: Baidu Online Network Technology (Beijing) Co., Ltd.
    Inventors: Rongxin Zou, Yinming Mei, Zhu Xiang, Hanzhong Hu
  • Patent number: 10185644
    Abstract: A meta-debugger receives a first debugging command from a debugger client to set a breakpoint in a first service in a first language and sets the breakpoint in a first native debugger. After receiving a service message invoking the first service, the breakpoint is triggered and the meta-debugger provides to the debugger client a first graphical representation of the first native debugger. The meta-debugger receives a second debugging command from the debugger client, converts the second debugging command into a third debugging command to provide to the first native debugger. After invoking a second service in a second language, the meta-debugger provides to the debugger client a second graphical representation of the second native debugger. The meta-debugger receives a fourth debugging command from the debugger client, converts the fourth debugging command into a fifth debugging command to provide to the second native debugger.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: January 22, 2019
    Assignee: Red Hat, Inc.
    Inventors: Jiri Pechanec, Martin Vecera
  • Patent number: 10185650
    Abstract: The techniques described herein provide software testing of a candidate software system. In some examples, a testing service compares at least one candidate response to at least a first control response to obtain one or more candidate test differences. The testing service may compare at least a second control response of the plurality of control responses to at least one of the first control response of the plurality of control responses or a third control response of the plurality of control responses to obtain one or more control test differences. The testing service may then analyze the one or more candidate test differences based on the one or more control test differences to generate an evaluation of whether one or more of the candidate test differences are due to differences between the candidate software system and the control software system that generated the first control response.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: January 22, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Samuel Leonard Moniz, Keian Christopher, Andrew Ross Evenson
  • Patent number: 10176337
    Abstract: In accordance with embodiments, there are provided mechanisms and methods for allowing access to developed applications via a multi-tenant on-demand database service, in a controlled environment. These mechanisms and methods for providing such access can enable embodiments to provide additional control over the development process as well as the access of such developed applications. The ability of embodiments to provide such additional control may lead to an improved application development framework, etc.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 8, 2019
    Assignee: salesforce.com, inc.
    Inventor: Craig Weissman
  • Patent number: 10169181
    Abstract: A transactional memory test tests a transactional memory system on a computer processor. A test case with a transactional memory test is constructed such that the transactional memory test proceeds further in the transaction mode if the transaction is successful. In contrast, if there is a failure of the transaction, then the transactional memory test is executed in the non-transaction state. The transactional memory test stresses both transaction success and transaction failure cases of the processor for more efficient validation of the computer processor. Also, when checking the correctness of the test case the correct result remains the same whether the transaction passes or fails to simplify verification.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 10169133
    Abstract: The disclosed computer-implemented method for debugging network nodes may include (1) detecting a computing event that is indicative of a networking malfunction within a network node, (2) determining, based at least in part on the computing event, one or more potential causes of the networking malfunction, (3) identifying one or more debugging templates that each define debugging steps that, when performed by a computing system, enable the computing system to determine whether the networking malfunction resulted from any of the potential causes, (4) performing a set of debugging steps defined by one of the debugging templates that corresponds to one of the potential causes, and then (5) determining, based at least in part on the set of debugging steps defined by the debugging template, that the networking malfunction resulted from the potential cause. Various other methods, systems, and apparatuses are also disclosed.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 1, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Mukul Golash, Kushal Dhar, Saikat Sanyal
  • Patent number: 10172043
    Abstract: Managing handoffs between a plurality of mobile devices in a phone hosted microservices architecture in a same vicinity, with each of the mobile devices connected to a cognitive reliability engine. The cognitive reliability engine, for each of the plurality of mobile devices hosting a hosted microservice, determining a reliability score for a time period through context and activity recognition of a user owning the mobile device. Depending on the reliability score, different beacons with data packets indicating that the microservice will end, the microservice may end, or the microservice will continue with surety for a specific time period.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Vijay Ekambaram, Pooja Malik, Vikram Yadav
  • Patent number: 10162698
    Abstract: A system and method for extensible, protective, and verifiable automated issue remediation for information technology infrastructure comprises invoking an application programming interface to obtain at least one issue object corresponding to an alert generated by a monitoring system; matching the issue object to at least one diagnosis plugin of a plurality of diagnosis plugins; obtaining a prescription object from the diagnosis plugin, the prescription object comprising a remedy; and invoking the remedy after verifying the remedy is authorized to proceed.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: December 25, 2018
    Assignee: Dropbox, Inc.
    Inventors: David Mah, Scott MacFiggen, John Watson
  • Patent number: 10162612
    Abstract: A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises runtime metadata associated with the application, converting, using the runtime metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by simulating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: December 25, 2018
    Assignee: Syntel, Inc.
    Inventors: Abhijit Apte, Abhishek Negi, Vivek Rao, Amit Pundeer, Sagar Kulkarni, Prashant Ladha, Shashank Moghe, Vedavyas Rallabandi, Ravi Shankar, Lopamudra Dhal, Prabhat Parey, Abhishek Agarwal, Rahul Mehra
  • Patent number: 10162693
    Abstract: A method of troubleshooting a mobile device receiving at a diagnostic server an initial snapshot of characteristics from a mobile device, wherein the initial snapshot includes metrics that will identify the mobile device, elements that will expose a performance issue related to the mobile device, and metrics that enable determination of a corrective action for remedying the performance issues, determining with a diagnostic processor the performance issue based on the initial snapshot, receiving at an evaluating server an after-care snapshot of the characteristics from the mobile device after a corrective action has been performed on the mobile device, and determining with an evaluating processor whether the corrective action remedied the performance issue based on the after-care snapshot.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: December 25, 2018
    Assignee: Sprint Communications Company L.P.
    Inventors: Jeffrey Ronald Contino, Jason R. Delker, Jason Salge, M. Jeffrey Stone, Robert L. Waldrop
  • Patent number: 10162747
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes: compressing data to generate first data; determining whether a data length of the first data meets a predetermined condition. The method also includes: if the data length of the first data meets the predetermined condition, writing the first data into a first physical erasing unit among a plurality of physical erasing units; if the data length of the first data does not meet the predetermined condition, generating dummy data according to a predetermined rule, padding the first data with the dummy data to generate second data and writing the second data into the first physical erasing unit. A data length of the second data meets the predetermined condition.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: December 25, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10127100
    Abstract: A method, system, and/or computer program product corrects a data error that has been caused by a break in a conductor link in a memory. A memory controller detects a line malfunction in a data bit transmission line between a first bit node and a second bit node in a memory, and then identifies a constant voltage state at the second bit node that is caused by the line malfunction. In response to determining that the constant voltage state is non-representative of the bit value intended to be transmitted from the first bit node to the second bit node, an inversion logic inverts bit values for all bits in an original bit array to create an inverted bit array, which is stored in the array of memory cells for future retrieval and re-inversion, in order to reconstruct the original bit array.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Briana E. Foxworth, Andre A. Marin, Kevin M. McIlvain, Lucas W. Mulkey, Anuwat Saetow
  • Patent number: 10127148
    Abstract: A method for testing an updated version of an existing software application is provided. The method may comprise analyzing a user interface screen of the updated version of the existing software application to identify previously existing controls and updated controls and then associating a plurality of testing actions with the previously existing controls and the updated controls, thereby generating a plurality of test steps. The method may further comprise generating an updated test component comprised of the plurality of test steps, identifying one or more previously existing test components that should be replaced by the updated test component in a test asset repository, and automatically updating each of the one or more previously existing test components with the updated test component at the same time.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: November 13, 2018
    Assignee: TurnKey Solutions Corp.
    Inventors: Dale H. Ellis, Ryan C. Jacques
  • Patent number: 10122381
    Abstract: A method for defining an erasure code for system having a predetermined number of data disks is disclosed. The method includes selecting step, constructing step, determining step and repeating step. The selecting step includes selecting a predetermined acceptable number of failures for the system. The constructing step includes constructing a first Tanner graph for two failures acceptable system having predetermined number of data disks. The determining step includes determining erasure code from the first Tanner graph. The repeating step includes repeating the constructing step and the determining step by increasing the acceptable number of failures by one and constructing another Tanner graph in response to the increased acceptable number of failures by increasing number of parity nodes until the predetermined number of failures for the system is reached.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 6, 2018
    Assignee: Agency for Science, Technology and Research
    Inventors: Chao Jin, Weiya Xi, Khai Leong Yong, Shibin Chen
  • Patent number: 10096379
    Abstract: A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: October 9, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Patent number: 10095504
    Abstract: A method, computer program product, and computing system for receiving telemetry data from a remote storage system. The telemetry data is analyzed to identify one or more issues with the remote storage system. One or more solutions are provided to the remote storage system based, at least in part, upon the one or more issues.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 9, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Muzhar Khokhar, Charles S. Langley, Brian Tetreault, Matthew Jean
  • Patent number: 10095813
    Abstract: A safety-analysis system for a complex system such as an aircraft includes a system modeler and model-analysis system. The system modeler is configured to receive component fault-based models of respective components of which a system is composed, such as from a library of component fault-based models in storage. The component fault-based models include transfer functions expressed as fault trees each of which describes behavior of a respective component in an event of a failure of the respective component or of an input to the component. The system modeler is also configured to assemble the component fault-based models into a system fault-based model of the system, with the system fault-based model including a transfer function expressed as an assembly of the fault trees of the component fault-based models. The model-analysis system, then, is configured to perform a safety analysis using the system fault-based model.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 9, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Anapathur V. Ramesh, David W. Twigg
  • Patent number: 10095708
    Abstract: A transactional block storage system is provided which is capable of supporting a single-phase commit for data writes specifying a protected storage unit. The storage system includes a data storage map that logically links the protected data storage unit to two or more block storage units associated with a layer of the protected data storage unit. The storage system also includes an address abstraction layer which translates write requests to the block storage units and resolves whether those write requests are atomically committed to the storage system in a single phase transaction. The address abstraction layer is further configured to detected when a block storage unit becomes unavailable during a transaction and create a cleaning kit for that block in order to prevent data loss. Additionally, the address abstraction layer facilitates moving, copying, and merging of block storage units without global locking in the storage system.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 9, 2018
    Assignee: Qumulo, Inc.
    Inventors: Aaron Passey, Neal Fachan, Peter Godman
  • Patent number: 10089213
    Abstract: Technologies are described herein for use in identifying and resolving software issues. One or more corrective actions may be identified and taken that are based upon the similarity between an unresolved issue and one or more resolved issues and/or upon the similarity between code changes made to resolve similar previously resolved issues. A version control graph might also be utilized to determine if a change made to resolve an issue in one branch of a software component is applicable to another branch of the software component. The version control graph might also be utilized to compute the relevance of an entry in an issue tracking system for an issue at a point in time after the entry is created in the issue tracking system.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 2, 2018
    Inventors: Matthew Roy Noble, Nicholas Alexander Allen, Andrew Thomas Troutman, Joshua William McFarlane
  • Patent number: 10091672
    Abstract: Embodiments of the present invention provide a fault handling method, apparatus and system, and relate to the field of communications, where the method includes: detecting, by a lower-layer fault management system, a fault alarm status in a lower-layer service; obtaining, by means of query by the lower-layer fault management system, according to the fault alarm status and a service dependence relationship table stored in a system, an affected higher-layer service; sending, by the lower-layer fault management system, a fault notification message to a higher-layer fault management system corresponding to the affected higher-layer service; and determining, by the higher-layer fault management system, according to the fault notification message whether a higher-layer service in which a fault occurs needs to be handled.
    Type: Grant
    Filed: December 27, 2015
    Date of Patent: October 2, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Ming Yu
  • Patent number: 10088523
    Abstract: An integrated circuit chip comprising system circuitry and debugging circuitry. The system circuitry comprises a peripheral circuit. The debugging circuitry comprises a debug unit and a debug adapter. The debug unit is connected to the peripheral circuit. The debug adapter interfaces between the debug unit and a debug controller. The debug adapter is configured to receive a sequence of debug commands from the debug controller, each debug command instructing the debug unit to perform an action other than responding to a poll. In respect of each debug command, the debug adapter sends the debug command to the debug unit, and polls the debug unit to query whether the debug unit has performed the action instructed in that debug command.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: October 2, 2018
    Assignee: UltraSoC Technologies Limited
    Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
  • Patent number: 10082533
    Abstract: A system and method for improving production yield of an article with cloud based processing by storing process information in cloud; transferring functional results to cloud, with functional results having identifying information of articles that have failed a functional test and identifying information of articles that have passed functional test; generating a probable cause list from process information in cloud, wherein probable cause list is a shortlisted version of said process information in said cloud; and generating a root cause list from probable cause list in cloud, wherein root cause list comprises process information responsible for failure in failed articles, whereby root causes of failures are analytically determined with processing power, memory, and storage that are scalable, reliable, and upgradable on demand.
    Type: Grant
    Filed: October 29, 2016
    Date of Patent: September 25, 2018
    Assignee: Exnodes Inc.
    Inventor: Sri Rama Prasanna Pavani
  • Patent number: 10078565
    Abstract: Methods and circuits are disclosed for error recovery in redundant processing systems. Respective instances of a software program are executed in lockstep on redundant processing circuits. Using a control circuit, in response to detecting a non-fatal error, an interrupt is generated and non-functioning ones of the processing circuits are disabled. The interrupt is serviced using the functional processing circuits operating in lockstep. In servicing the interrupt, a processing state of the processing circuits is stored and a reset of the processing circuits is triggered. Following the reset, the processing circuits are configured to operate in lockstep. The state of the processing circuits is restored to the stored processing state and a return from the interrupt is signaled. In response to the signaled return from interrupt, execution of the software program is resumed on the processing circuits in lockstep at a point at which the non-fatal error was detected.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 18, 2018
    Assignee: XILINX, INC.
    Inventor: Leif Roland Petersson
  • Patent number: 10073912
    Abstract: Some embodiments include a system. The system comprises an input device, an output device, one or more processing modules, and one or more non-transitory memory storage modules storing computer instructions. The computer instructions are configured to run on the processing module(s) and perform the acts of: identifying at least one test web page; and analyzing a first test web page of the at least one test web page. The analyzing the first test web page of the at least one test web page comprises crawling the first test web page to detect a first adverse performance condition of the first test web page, and the first adverse performance condition can impact a first search rank assigned to the first test web page when present. Other embodiments of related systems and methods are also provided.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 11, 2018
    Assignee: SEARCHMETRIC GMBH
    Inventors: Marcus Tober, Paul Schütte, Jens Ulrich, Christian Lange
  • Patent number: 10068215
    Abstract: A payment processing system for mobile point-of-sale transactions from a mobile point of sale terminal including a payment card reader having a card interface configured to read data from a payment card, the payment processing system includes an automated support system for proactively generating and presenting support messages for merchants using a mobile point-of-sale terminal. The automated support system generates the support message using a current account context for the merchant account and a plurality of rules that indicate a problem with the merchant account. The automated support system is further configured to generate a plurality of rules for detecting merchant account problems using a knowledge database of support tickets that include a human generated response to a merchant account problem and a corresponding merchant account context at the time of the human generated response.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: September 4, 2018
    Assignee: Square, Inc.
    Inventors: Nathan Rosenthal, Tyler Kovacs, Michael Smith
  • Patent number: RE47500
    Abstract: A method of handling internal operations of a storage device includes in response to information derived from one or more commands received from a host device when the storage device is coupled to the host device, determining whether a sequence of commands is in one of an active state, and a first transition state, where in the first transition state the sequence of commands is transitioning from an inactive state to the active state. The method includes, while the sequence of commands is in the active state or in the first transition state, refraining from executing any operation of a first set of internal memory management operations, each of the first set of internal memory management operations being an extra-sequence operation.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: July 9, 2019
    Assignee: SanDisk IL Ltd.
    Inventors: Amir Mosek, Elad Baram