Abstract: User interface technologies for viewing the state of threads of a target parallel application, such as a massively parallel application intended to run on a GPGPU system, during debugging of the target parallel application are disclosed. The target parallel application includes a kernel, and the kernel includes a set of threads. Coalesced thread information of the threads is presented with the user interface technologies based on user-controllable criteria.

Abstract: A device driver includes a kernel stub and a user-mode module. The device driver may access device registers while operating in user-mode to promote system stability while providing a low-latency software response from the system upon interrupts. Upon receipt of an interrupt, the kernel stub may run an interrupt service routine and write information to shared memory. Control is passed to the user-mode module by a reflector. The user-mode module may then read the information from the shared memory to continue servicing the interrupt.

Abstract: A novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for all installations of a software application, not just software in development mode or at a specific installation. Code coverage bits are implemented in either the instruction set architecture (ISA) of the central processing unit, the executable file of a software application, a companion file to the executable file or a code coverage table residing in memory of the computer system.

Abstract: A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.

Abstract: Processing units are configured to capture the unit state in unit level error status registers when a runtime error event is detected in order to facilitate debugging of runtime errors. The reporting of warnings may be disabled or enabled to selectively monitor each processing unit. Warnings for each processing unit are propagated to an exception register in a front end monitoring unit. The warnings are then aggregated and propagated to an interrupt register in a front end monitoring unit in order to selectively generate an interrupt and facilitate debugging. A debugging application may be used to query the interrupt, exception, and unit level error status registers to determine the cause of the error. A default error handling behavior that overrides error conditions may be used in conjunction with the hardware warning protocol to allow the processing units to continue operating and facilitate in the debug of runtime errors.

Abstract: In a particular embodiment, a method of monitoring interrupts during a power down event at a processor includes activating an interrupt monitor to detect interrupts. The method also includes isolating an interrupt controller of the processor from the interrupt monitor, where the interrupt controller shares a power domain with the processor. The method also includes detecting interrupts at the interrupt monitor during a power down time period associated with the power down event.

Abstract: A method and apparatus for the detection and correction of soft errors existing within an integrated circuit (IC). Run-time check stops are utilized in conjunction with processor-based, hardware mechanisms to detect and correct soft errors. At run-time, each check stop facilitates a snap shot of the hardware and/or software state of the IC to be stored into hardware and/or software based memory. Should a soft error be detected, execution is halted and the executable state of the IC that conforms to a previous check-stop location may be re-established after the soft error(s) are optionally corrected. In alternate embodiments, hardware based mechanisms may be exclusively utilized to both detect and correct the soft errors.

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract: Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first memory to store firmware for the processor; and a second memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to read a portion of the firmware from a predetermined location in the first memory; wherein the test interface is enabled only when the portion of the firmware has a predetermined value.

Abstract: A global processor operating mode is used select whether a processor stops processing when an error is detected or ignores the error and continues processing while overriding values as needed to recover from the error. When a soldier-on mode is enabled the system attempts to recover from the error while also recording the error state of the first error in on-chip registers for later analysis. When the soldier-on mode is not enabled and an error occurs, the system stops processing and the error is reported up to the operating system.

Abstract: A computer readable storage medium with executable instructions specifies the execution of a state machine operating across a set of computing nodes in a distributed computing system. The executable instructions execute a set of operators, where the execution of each operator is under the control of a state machine that periodically invokes pause control states to pause the execution of an operator in response to a violation of a service level agreement specifying an operating condition threshold within the distributed computing system. Partitions of input data are formed that are worked on independently within the distributed computing system. A set of data batches associated with the input data is processed. Data partition control states to process the partitions associated with the set of data batches are specified. Key control states to process a set of keys associated with a data partition of the partitions are defined.

Abstract: An information processing apparatus includes an application management framework for managing the operating state of an application; another framework different from the application management framework; and an application that operates using this other framework. The application management framework has a determination unit adapted to determine whether or not the application is capable of being halted; and a halt control unit adapted to halt the application if the determination unit determines that the application is capable of being halted, and cancel the halting of the application if the determination unit determines that the application is not capable of being halted.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: Embodiments relate to systems and methods for storing machine state history related to detected faults in a package update process. A classification tool can interface with a data store that can store machine state data on a client. The classification tool can record an initial machine state on the client and initiate a package update on the client. The classification tool can further record an updated machine state of the client subsequent to initiating the package update and detect a fault condition in the client subsequent to initiating the package update. The classification tool can examine the initial machine state and the updated machine state to categorize one or more causes of the fault condition as either related to the package update or to systemic conditions of the client. The classification tool can further notify a user of the client of the one or more causes of the fault condition.

Abstract: An error in a web page displayed on a device is detected. The error is assigned to a bucket to indicate a type of the error, and a record describing the current state of the device is generated. Both an indication of the bucket and the record describing the current state of the device are then sent to a server. At the server, error information including error records and bucket identifiers are received from multiple devices. Each error record describes a current state of one of the multiple devices at a time when an error in a web page displayed on the one device was detected. Each bucket identifier corresponds to one of the error records and describes a type of the error associated with that error record. The error records are grouped into multiple baskets based at least in part on the current state information in the error records.

Abstract: Provided is a method for mitigating the effects of an application which crashes as the result of supplemental code (e.g., plug-in), particularly a plug-in from a source other than the source of the operating system of the device or the source of the application that crashes. The method includes executing the application. As the application is running, it may be monitored to determine if normal execution of instructions ceases. When that occurs, the system will make a determination if code from a supplemental code module was the cause of the crash, and will make an evaluation if that supplemental code module is from a source other than the source(s) of the operating system and application in question. In some implementations, remedial steps may be provided, such as providing information on subsequent executions of the application.

Abstract: An information processing system includes a memory, an external storage having a user's area and a system area, and a logging unit collecting communication information in the system. The information processing system further has a unit that receives a network logging activation instruction, and determines whether memory dump information at the point system freezing occurred exists in the system area or not, a unit that copies the network logging file to the system area if the conditions are satisfied, and a unit that writes the communication information stored and maintained in the memory dump information to the copied network logging file.

Abstract: Provided are an apparatus and a method for forcibly terminating a thread blocked on an I/O operation by terminating the I/O operation, transmitting a user-defined signal to the thread blocked on the I/O operation, and temporarily releasing the corresponding thread from a blocked state such that a ThreadDeath Exception is generated with respect to the thread attempting to execute an I/O system call. The apparatus includes a control unit which checks a state of a thread that is included in an application, a signal transmitting unit which transmits a signal for releasing a blocked state of the thread, an operation managing unit which executes a first terminating function on the I/O operation that is included in the thread, and a thread managing unit which executes a second terminating function on the thread.

Abstract: A system and method for mapping exceptions from a first programming model to a second programming model. The system comprises a first device operating a first programming model and a second device operating a second programming model. The first device sends an instruction to, or invokes the second device to execute an instruction. As a result, a fault occurs during execution of the instruction in the second programming model. An exception based on the fault is raised, and returned to the first device. A fault mapping module receives the exception from the first device. The fault mapping module attempts to determine the type of exception received by comparing an identifier with predetermined identifiers indicating exception type. The fault mapping module interprets the exception to generate an interpreted exception recognizable by the first programming model if the exception is determined to be of a predetermined type.

Abstract: An embodiment relates generally to an apparatus for debugging. The apparatus includes a memory configured to store data and an arithmetic logic unit configured to perform logical and arithmetic operations. The apparatus also includes a control unit configured to interface with the memory and arithmetic logic unit and to decode instructions. The control unit is configured to write a data state designated to be overwritten by a currently executing instruction to a buffer allocated in the memory in response to a trace debug flag being set.