Abstract: A method includes performing a file system integrity validation on a host machine having a hypervisor architecture when a file system of a second process is mounted on a file system of a first process. The file system integrity validation occurs independently of booting the host machine.

Abstract: Maintaining functionality during component failures is presented. During application registration, a recovery engine generates a recovery plan for the application. The recovery plan includes recovery actions that correspond to each component that the application intends to access. When an application encounters an unavailable component, the recovery engine provides a recovery action to the application which instructs the application how to proceed, such as accessing a backup component. The recovery engine tracks unavailable components and, when a subsequent application registers that intends to use an unavailable component, the recovery engine provides the subsequent application a recovery action, instructing the subsequent application how to proceed.

Abstract: A software compliance test is typically directed only at particular classes in the inheritance hierarchy. Inherited APIs (classes), which are not the focus of the test, may cause the application under test (AUT) to fail the compliance test since some of the underlying classes differ from a reference implementation. Accordingly, a verification tool employs the same version and implementation of inherited APIs in the reference implementation of these inherited APIs as the application under test. A dynamic class loader examines class inheritance references made by the application under test to determine if the class is included in the API to be tested, or if the class is outside the scope of the API to be tested. If the class corresponds to the API to be tested, then the dynamic loader uses the reference implementation of the API for comparison. Otherwise, the reference implementation employs the same inherited class references as the application under test.

Abstract: A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.

Abstract: In one general embodiment, a method is provided. In operation, one of a plurality of object recognition methods is selected as a default object recognition method. Additionally, a test script is executed on an application. Further, it is detected whether the test script requires interaction with an object on a graphical user interface of the application. If the test script requires interaction with the object on the graphical user interface of the application, the default object recognition method is used to attempt to recognize the object on the graphical user interface of the application. If the object on the graphical user interface of the application cannot be detected with the default object recognition method, an alternate one of the plurality of object recognition methods is used to recognize the object on the graphical user interface of the application and recognition properties of the default object recognition method are updated to be able to recognize the object on the graphical user interface.

Abstract: The system and method of the present invention combine multiple tests (15) into a batch and submit the batch for processing to exercise electronic circuits, for example, a managed network (25) such as a wireless network. The system and method insure that tests (15) are timely run by utilization of a batch submit trigger (42). When a test (15) has completed, the system and method return the results (11) of that particular test (15) to the user, regardless of whether or not the rest of the tests (15) in the batch have completed execution.

Abstract: A system for reporting and/or displaying errors in a system that affect end-user tasks includes mechanisms for gathering, interpreting and displaying application status information in a convenient display. In one implementation, for example, distributed application programs in a system are configured to provide status reports (e.g., positive, negative, pending) to a centralized reporting service. The centralized service stores the status information in a database. An event interpreter module queries the database to identify the status of certain application components that affect or otherwise implicate performance of generalized end-user tasks, such as sending/receiving email, logging-in to the network, accessing the internet, remote computer management, or the like.

Abstract: An improved method and apparatus for time stamping events occurring on a large scale distributed network uses a local counter associated with each processor of the distributed network. Each counter resets at the same time globally so that all events are recorded with respect to a particular time. The counter is stopped when a critical event is detected. The events are masked or filtered in an online or offline fashion to eliminate non-critical events from triggering a collection by the system monitor or service/host processor. The masking can be done dynamically through the use of an event history logger. The central system may poll the remote processor periodically to receive the accurate counter value from the local counter and device control register. Remedial action can be taken when conditional probability calculations performed on the historical information indicate that a critical event is about to occur.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

Abstract: Embodiments of the invention provide techniques for troubleshooting of computer systems using a fault tree analysis. In one embodiment, data parameters describing a status of a system may be monitored to determine the existence of a fault. In the event of a fault, fault tree analysis metadata may be evaluated to attempt to determine a root cause of the fault. If a root cause can be automatically determined, it may be presented to a user in a troubleshooting console, or may be used to trigger an automated corrective action. Alternatively, if a root cause cannot be automatically determined, the user may be presented with additional fault tree analysis metadata and any relevant data parameters in the troubleshooting console, so that the user may determine the root cause of the fault event.

Abstract: When, during debugging, a program failure occurs, the location of the failure is determined. First the address in the stack related to the program failure is found. Then static analysis is performed in order to determine a possible culprit for the failure. For example, when a security cookie has been overwritten, indicating a probable overflow, the location of the security cookie on the stack is determined, and proximate storage structures (such as arrays) which may have overflowed onto the location of the security cookie are determined. Then static analysis is used to determine probable sources (e.g. functions or instructions in a function) for this error. In this way, the root cause of a buffer overflow or similar problem can be identified easily, rather than requiring extensive time and knowledge regarding the working of the compiler, the security cookie, the stack, static analysis, and the source code.

Abstract: A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber, calculating dynamic estimation errors for the precursor and/or purging process, and determining if the dynamic estimation errors can be associated with pre-existing BIST rules for the process. When the dynamic estimation error cannot be associated with a pre-existing BIST rule, the method includes either modifying the BIST table by creating a new BIST rule for the process, or stopping the process when a new BIST rule cannot be created.

Abstract: Techniques for systematically gathering, organizing, and storing diagnostic data related to multiple monitored systems (e.g., multiple instances of a product or multiple products). A centralized repository is provided that is organized in a hierarchical manner to facilitate proper organization of the diagnostic data related to multiple monitored systems. In one embodiment, a root directory comprising one or more subdirectories is provided for storing diagnostic data collected for each monitored system. Multiple root directories may be provided under a common base directory for storing diagnostic data corresponding to multiple monitored systems. This enables correlation of diagnostic data across multiple monitored systems.

Abstract: A system that select tests to exercise a given computer system is described. During operation, the system tests the given computer system using a set of tests, where a given test includes a given load and a given cycling time selected from a range of cycling times. Moreover, for the given test, the system monitors a stress metric in the given computer system. Additionally, the system selects at least one of the tests from the set of tests to exercise the given computer system based on the monitored stress metric.

Abstract: A diagnosability system for automatically collecting, storing, communicating, and analyzing diagnostic data for one or more monitored systems. The diagnosability system comprises several components configured for the collection, storage, communication, and analysis of diagnostic data for a condition detected in monitored system. The diagnosability system enables targeted dumping of diagnostic data so that only diagnostic data that is relevant for diagnosing the condition detected in the monitored system is collected and stored. This in turn enables first failure analysis thereby reducing the time needed to resolve the condition detected in the monitored system.

Abstract: A method for protocol identification by recognizing determinative data among data transmitted through a detected connection using lists of explicit and implicit son protocols associated with each protocol. The kernel of an information system associates to each detected connection a data structure arranged so that it comprises an ordered sequence of the protocol names. The kernel builds the data structure by retrieving the son protocol names in the list associated to the last protocol name of said ordered sequence, the son protocol name for which the associated self identification mechanism recognizes determinant data among transmitted data by adding the retrieved son protocol name to the end of the sequence and by restarting to retrieve the son protocol name for which the associated self identification mechanism recognizes determinant data among transmitted data.

Abstract: A monitoring system and method. The monitoring system receives specified rules related to at least one component within a computing system. The monitoring system receives first data comprising information related to at least one component within a computing system. The monitoring system comprises a repository. The first data is stored within the repository. The first data is analyzed by the monitoring system using specified rules to determine a first health status of the at least one component. The monitoring server indicates for a user the first health status.

Abstract: A system, method and computer program product for dynamically debugging a multi-node network comprising an infrastructure including a plurality of devices, each device adapted for communicating messages between nodes which may include information for synchronizing a timing clock provided in each node. The apparatus comprises a plurality of probe links interconnecting each node with a probe device that monitors data included in each message communicated by a node. Each probe device processes data from each message to determine existence of a trigger condition at a node and, in response to detecting a trigger condition, generates a specialized message for receipt by all nodes in the network. Each node responds to the specialized message by halting operation at the node and recording data useful for debugging purposes. In this manner, debug information is collected at each node at the time of a first error detection and collected dynamically at execution time without manual intervention.

Abstract: A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber; determining a measured dynamic process response for a rate of change for a process parameter; executing a real-time dynamic model to generate a predicted dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the expected process response; and comparing the dynamic estimation error to operational limits.

Abstract: A dynamic probe system for probing a FPGA with at least one core. A trace core is added to the FPGA, the trace core in communication with a plurality of signal banks, each signal bank comprising a plurality of signals in the at least one core. A logic analyzer, in communication with the trace core and selecting the bank of signal to be sent from the trace core to the logic analyzer.

Abstract: An occurrence pattern of an event is detected from an event log based upon information concerning plural kinds of relationships defined among events, such as a simultaneity rule, an order rule, a proximity rule, a cause determination rule, and a result prediction rule and an occurrence pattern of the detected event is output. Accordingly, when an occurrence pattern of an event is detected from event data storing information concerning an occurred event, detailed information about an occurrence pattern of an event can be extracted from an event log.

Abstract: A method for analyzing the root cause of system failures on one or more computers. An event is generated when a computer system detects a system failure. The cause of the failure is determined. The event, including the cause is transmitted from the computer system to a central repository. And the system failure is analyzed in the central repository.

Abstract: An arrangement and method for analyzing the timing of events in a test system including a device under test and a plurality of test instruments connected together by one or more communication connections: time-stamps events in a test routine executed by the test instruments under control of a test program to generate time-stamped event data; communicates the time-stamped event data to a central processor; and processes the time-stamped data to output information about the timing of the events.

Abstract: The exemplary embodiments provide a computer-implemented method, apparatus, and computer-usable program code for reporting operating system faults on an Intelligent Platform Management Interface compliant server. In response to receiving an alert for an operating system fault, the alert for the operating system fault is converted into an IPMI event. The IPMI event is stored in an internal event log. An IPMI system event record is created for the IPMI event. The IPMI event is sent to a host management controller in order to enable monitoring of the operating system fault.

Abstract: A method and apparatus to provide identity management deployment interoperability and compliance verification. In one embodiment, the system also provides on-demand services including automated certification, monitoring, alerting, routing, and translation of tokens for federated identity related interactions between multi-domain identity management systems is provided.

Abstract: A fault detection system for detecting a fault in a process system includes a first circuit configured to modify an input of the process system with a modifying signal. The fault detection system further includes a second circuit configured to receive an output from the process system and configured to determine whether the fault exists based on at least one of a reduction of a signal component and an unexpected transformation of the signal component, wherein the signal component corresponds to a function of the modifying signal.

Abstract: By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.

Abstract: Data is collected relating to the availability of a computing resource such as data identifying a start event that indicates that the computing resource became available for use and data identifying a stop event that indicates that the computing resource became unavailable for use. The data relating to the availability of the computing resource is processed to determine the outage time for the computing resource during a period of time, such as a 24-hour period. The outage time is then utilized to calculate the level of availability for the computing resource during the period of time.

Abstract: The invention relates to optimizing software code execution during state transitions. The system handles changes in execution context using differential rule checking techniques. For instance, when a thread executing in a data processing system changes state, its new state may be subject to different rules than its previous state. To enforce these rules, the thread may be associated with software code that causes certain restrictions, such as memory restrictions, to be applied to the thread. In an interpretive environment, this can be implemented by detecting a state transition in an active thread, and responding to the state transition by associating the thread with a dispatch table that reflects its state change. The dispatch table may cause the thread to be associated with code that enforces those restrictions. In one example, different dispatch tables can be provided, each table reflecting a different state of a thread, and each causing a thread to be subject to different restrictions.

Abstract: An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

Abstract: A method and computer program product for detecting and diagnosing errors in a generic function call and then presenting them in an error message is disclosed. A generic function call is provided for evaluation. A corresponding generic function definition containing sets of dummy arguments that define arguments signatures for associated specific functions is also provided. In a first sorting the generic function call is compared with the argument signatures to determine whether the generic function call contains errors. A second sorting is then used to determine the nature of the errors. An error message describing the nature of the errors is then generated.

Abstract: A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module.

Abstract: Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

Abstract: A method for monitoring a system operating in real-time includes monitoring the system for a triggering event or events, recording data about the system to a first memory in real time prior to and/or for a set time subsequent to when the triggering event occurs, and sending the stored data from the first memory to a second memory or an interface for retrieval.

Abstract: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.

Abstract: A method, apparatus and program storage device for providing control of statistical processing of error data over a multitude of sources using a dynamically modifiable DFT rule set is disclosed. The dispersion frame technique is extended in the present invention to provide dispersion frame rules with user-defined parameters thereby creating a dynamically modifiable rule set.

Abstract: A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detected to generate an enable signal. A stop event, such as a packet trailer, a specified digital event, a time interval or the like, is identified to generate a disable signal. The enable and disable signals are combined to produce a qualification signal that allows a trigger circuit to trigger on a specified anomaly within the portion of the serial data stream defined by the qualification signal.

Abstract: Methods and systems for pre-detecting a hardware hang in a processor. The methods comprise maintaining a count of a number of cycles in a predefined time interval without an instruction being completed; detecting a pre-hang condition if said count is within N counts of a hang limit; initiating trace capture in response to detecting said pre-hang condition; and detecting a hang condition if said count equals said hang limit.

Abstract: A method of supporting the optimization of a test program that is made up of a plurality of actions is described. The method may include applying the test program to a device, recording a protocol having a plurality of entries, each corresponding to an action and each specifying at least the type and the time the action is performed, outputting a graphic representation of the sequence of the actions derived from the protocol highlighting at least one selected type of action performed during the application of the test program.

Abstract: A method and system for testing newly installed or recently upgraded software is presented. All software installation activities are tracked and logged. New and upgrade software is isolated, either physically or logically, and tested using diagnostic software. If the new/upgrade isolated software passes the testing by the diagnostic software, then it is allowed to operate in the presence of other previously installed software. If an error occurs during an execution of the new/upgrade software, either while isolated or in the presence of previously loaded software, a log of other concurrently running software is reviewed to determine a likely software incompatibility with the new/upgrade software.

Abstract: A debugging apparatus is provided for debugging an information storage apparatus. The debugging apparatus includes a debugging control unit, an information converting circuit, and a computer device. The debugging control unit captures raw data and then generates a coded data sequence representing the raw data. The information converting circuit receives the coded data sequence and transforms the coded data sequence into a predetermined format. The computer device is connected to the information converting circuit, and for receiving the coded data sequence in the predetermined format and decoding the coded data sequence to the raw data.

Abstract: A method and system for capturing a state of a distributed computer system is provided. The state is captured in response to an error or event message received by one of the clients and/or server nodes of the system. In response to receipt of the error or event message, the recipient initiates transmission of a special protocol message of affected members of the system. Upon receipt of the message, all recipients will conduct a freeze of their respective operating system image. Depending upon the characteristics of the error or event, the message may be transmitted to a selection of members of the system, or the entire system.

Abstract: A simple, but intelligent watchdog circuit uses an up/down counter for its delay element. A watchdog event will occur if the counter is allowed to over flow or under flow its boundaries (in either direction). The system objective is to keep the counter within its boundaries by controlling the direction of the count. The count direction is simply a function of the Most Significant Bit (MSB) of the counter. Thus, the system must simply monitor the counters MSB and perform a little intelligent to determine the desired count direction.

Abstract: Methods and mechanisms for preventing deadlock in a policy-based computer system are disclosed. In one embodiment, the method includes various machine-implemented steps, such as a step of receiving policy information based upon decisions about system configurations. At least one policy includes at least one action that has a post condition. Satisfaction of the post condition triggers at least one subsequent action or decision. The policy includes an indication whether the at least one subsequent action or decision should proceed if the action fails to satisfy the post condition. The at least one action is executed. Then, if the action fails to satisfy the post condition, a determination is made whether the at least one subsequent action or decision can proceed based upon the indication.

Abstract: Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A number of input/output (I/O) ports are provided to couple signals to and from the ASIC. The circuit includes means for moving internal signals from a subset of the number of different clock domains of multiple frequencies to a different clock domain for monitoring, observation, counting, and debug.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: A metod of performing a service which remotely monitors a Web site includes the steps of monitoring the site for an error and notifying a site representative in the event an error is detected on the site. Advance permission is not obtained prior to sending the notification and a fee is not charged for the service. The appropriate e-mail address to which the notification is sent is identified based on one or more categories and a priority assigned to all e-mail addresses identified on the monitored site. The notification may be sent, alternatively, to the representative of a site linked to the site monitored or to some other interested third party. Subscribers to the monitoring service may be enrolled automatically upon submission of their site to a search engine service or to a domain name registry. The list of service recipients generated by the monitoring service is usable for other commercial purposes.

Abstract: Some embodiments provide a device under test comprising a processing core to support execution debug signals, a debug ring to receive and to transmit the execution debug signals from and to the device under test, a first debug port to receive and transmit the execution debug signals from and to the debug ring, and a second debug port to receive data from observation signal lines of the device under test. The first debug port may transmit execution debug signals to define an event to detect within the device under test, to receive execution debug signals indicating occurrence of the event, and to use a handler to place the device under test in a quiescent state and to instruct the device under test to transmit data of one or more registers. The second debug port may receive the data of the one or more registers from observation signal lines of the device under test.