Performance Monitoring For Fault Avoidance Patents (Class 714/47.1)
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Patent number: 9495234Abstract: Systems and methods for detecting anomalies within a multi-tenant environment are described. Diagnostic tests are performed on one or more components, such as host computing devices. The one or more components send resulting diagnostic information to an electronic device such as a monitoring component that processes the diagnostic information. The electronic device determines whether one or more properties, such as errors, are comprised within the one or more components. Based at least in part on properties that may be found, a correlation may be made between at least two properties.Type: GrantFiled: June 14, 2013Date of Patent: November 15, 2016Assignee: Amazon Technologies, Inc.Inventors: Richard Alan Hamman, Matthew James Eddey
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Patent number: 9471252Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.Type: GrantFiled: February 4, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta
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Patent number: 9471253Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.Type: GrantFiled: February 4, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T Benhase, Lokesh M. Gupta
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Patent number: 9436544Abstract: A method, device and non-transitory computer readable medium that implements error detection and recovery includes receiving from one or more agents monitoring one or more subsystem processes of a business process operating in a cloud based architecture an identification of an error condition in at least one of the subsystem processes. Additionally, any associated information or data necessary to execute the at least one of the subsystem processes with the identified error condition is received. An error recovery process for the at least one of the subsystem processes with the identified error condition is executed by the application management computing device. The recovered at least one of the subsystem processes with the identified error condition is reinitiated using the received information or data corresponding to the at least one of the subsystem processes with the identified error condition.Type: GrantFiled: August 19, 2014Date of Patent: September 6, 2016Assignee: Wipro LimitedInventors: Soham Bhaumik, Hemant Kumar, Amit Krishna, Nithya Ramkumar, Sridhar Krishnaswamy
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Patent number: 9436535Abstract: Systems and methods are provided for analyzing operating metrics of monitored metric sources. Aspects of the present disclosure may present for display information associated with the monitored metric source and the analysis of its operating metrics. Analysis comprises determination of reference values and tolerance levels which represent allowable deviations from the reference values. Input data includes a measurement of an operating parameter and a time stamp. Input data may be saved to a data store for using in future analysis of other input data. When input data is determined to be outside the tolerance level, notifications may be issued to alert administrators or systems of the anomaly.Type: GrantFiled: April 20, 2015Date of Patent: September 6, 2016Assignee: Amazon Technologies, Inc.Inventors: Mathias G. Ricken, Arthur Carré, Miles C. Kaufmann, Aaron T. Olds, Muhammad Ali Siddiqui, Sanjeev K. Verma, Kendra A. Yourtee
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Patent number: 9430404Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, a Solid State Device (SSD) tier is variably shared between the lower-speed cache and the managed tiered levels of storage such that the managed tiered levels of storage are operational on large data segments, and the lower-speed cache is allocated with the large data segments, yet operates with data segments of a smaller size than the large data segments and within the large data segments, where if selected data segments are cached in the lower-speed cache and are determined to become uniformly hot, the selected group from the lower-speed cache are migrated to the SSD tier.Type: GrantFiled: August 11, 2015Date of Patent: August 30, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Karl A. Nielsen
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Patent number: 9411742Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that if a selected group is cached in the lower-speed cache and is determined to become uniformly hot, migrating the selected group from the lower-speed cache to the SSD portion while refraining from processing data retained in the lower-speed cache until the selected group is fully migrated to the SSD portion.Type: GrantFiled: October 5, 2015Date of Patent: August 9, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
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Patent number: 9405575Abstract: This disclosure pertains to systems, methods, and computer readable media for utilizing an unused hardware thread of a multi-core microcontroller of a graphical processing unit (GPU) to gather sampling data of commands being executed by the GPU. The multi-core microcontroller may include two or more hardware threads and may be responsible for managing the scheduling of commands on the GPU. In one embodiment, the firmware code of the multi-core microcontroller which is responsible for running the GPU may run entirely on one hardware thread of the microcontroller, while the second hardware thread is kept in a dormant state. This second hardware thread may be used for gathering sampling data of the commands run on the GPU. The sampling data can be used to assist developers identify bottlenecks and to help them optimize their software programs.Type: GrantFiled: September 9, 2013Date of Patent: August 2, 2016Assignee: Apple Inc.Inventors: Zachary Burka, Serge Metral
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Patent number: 9389894Abstract: The present disclosure relates to flexible processor association for virtual machine instances. One example method includes initializing a virtual machine instance on a particular computing device, the particular computing device including a plurality of physical processors, determining a maximum number of the physical processors available to be associated with the virtual machine instance; initializing a number of virtual processors for use by the virtual machine instance, the same as the maximum number of the physical processors; associating the virtual machine instance with a number of the physical processors less than the maximum number of the physical processors; during execution of the virtual machine instance: identifying a change in a demand metric associated with the virtual machine instance; and adjusting the number of the physical processors associated with the virtual machine instance based on the identified change in the demand metric while maintaining the number of virtual processors.Type: GrantFiled: October 15, 2014Date of Patent: July 12, 2016Assignee: Google Inc.Inventors: Xiao Zhang, Xiaopan Zhang
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Patent number: 9378082Abstract: An improved technique involves mapping differences between current data collected from a component and previous data collected from the component to anomalous behavior of the component. A central diagnosis server collects previous state data such as disk or CPU utilization from components of various data storage systems it supports. The server may store this data, indexed by identifiers such as events linked to the state data, in a central database for later reference. The server then compares current state data being received from a particular data storage system to previous state data stored in the database. In some arrangements, the server selects previous state data based on matching event identifiers corresponding to the current state data and previous state data. The central diagnosis server then determines anomalous behavior based on the difference between current and previous state data.Type: GrantFiled: December 30, 2013Date of Patent: June 28, 2016Assignee: EMC CorporationInventor: Sudhakaran Nair
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Patent number: 9372747Abstract: Reliability of one or more software modules is projected according to a current state in a development life cycle of the software modules and any of various additional indicators. Preferably, a data processing support provider separate from the service-providing enterprise maintains historical field support data concerning significant field defect events with respect to various resources, and uses this data for projecting reliability of the resources. Preferably, software module reliability projections are used to support an analysis of risk of degradation of a service specified in a service requirements specification when provided by a configuration of data processing resources specified in a configuration specification.Type: GrantFiled: July 15, 2015Date of Patent: June 21, 2016Assignee: International Business Machines CorporationInventors: John J. Bird, Terry R. Ulmer
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Patent number: 9348677Abstract: A batching module that inspects call stacks within a stack evaluator to identify current expressions that can be evaluated in batch with other expressions. If such expressions are identified, the corresponding stacks are blocked from further processing and a batch processing request for processing the expressions is transmitted to the application server. The application server processes the expressions in batch and generates a value for each of the expressions. The blocked stacks are then populated with the values for the expressions.Type: GrantFiled: October 22, 2012Date of Patent: May 24, 2016Assignee: Palantir Technologies Inc.Inventors: Eugene E Marinelli, III, Yogy Namara
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Patent number: 9323687Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache.Type: GrantFiled: November 7, 2013Date of Patent: April 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
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Patent number: 9319037Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.Type: GrantFiled: February 3, 2014Date of Patent: April 19, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Arun Sundaresan Iyer, Alok Baluni, Samuel Naffziger, Sriram Sambamurthy
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Patent number: 9310433Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: April 17, 2015Date of Patent: April 12, 2016Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9311253Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, a Solid State Device (SSD) tier is variably shared between the lower-speed cache and the managed tiered levels of storage such that the managed tiered levels of storage are operational on large data segments, and the lower-speed cache is allocated with the large data segments, yet operates with data segments of a smaller size than the large data segments and within the large data segments.Type: GrantFiled: November 7, 2013Date of Patent: April 12, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Lokesh M. Gupta, Karl Nielsen
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Patent number: 9298526Abstract: Various method, system, and computer program product embodiments for facilitating upgrades in a computing storage environment are provided. In one such embodiment, one of an available plurality of rolling upgrade policies is defined by specifying the at least one selectable upgrade parameter, including specifying one of a commencement time and duration of an upgrade procedure. A node down tolerance factor is set for at least one node in the computing storage environment. The node down tolerance factor specifies a percentage of elements of the at least one node taken offline to apply the selected one of the available plurality of rolling upgrade policies during the upgrade window.Type: GrantFiled: April 8, 2015Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin L. Andrews, Anthony J. Ciaravella, Joseph W. Dain, Nikhil Khandelwal
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Patent number: 9218232Abstract: A method for detecting an anomaly in operation of a data analysis device, comprising: receiving present real-time readings of multiple sensors associated with the data analysis device, and maintaining a history of past real-time readings; determining which of said multiple sensors are correlated; computing a deviation between at least some of said present and at least some of said past real-time readings of said correlated sensors; and declaring an anomaly when said deviation exceeds a predetermined threshold.Type: GrantFiled: April 12, 2012Date of Patent: December 22, 2015Assignee: Bar-Ilan UniversityInventors: Eliahu Khalastchi, Gal Kaminka, Raz Lin, Meir Kalech
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Patent number: 9218234Abstract: Systems and methods for executing a memory dump in a computer system are provided. A trigger event is detected in the computer system. The computer system is configured to detect both a kernel panic and a system hang and to execute memory dump if either of the kernel panic or the system hang is detected. The memory dump is executed in the computer system in response to the detecting of the trigger event. The executing of the memory dump includes storing a current context of the computer system in a portion of a memory device. The current context is stored without reserving the portion prior to the detecting of the trigger event. The computer system is restarted and a bootstrap program is executed, where a running space of the bootstrap program is restricted to the portion of the memory device. The bootstrap program is used to upload the current context to a host device.Type: GrantFiled: April 17, 2013Date of Patent: December 22, 2015Assignee: MARVELL WORLD TRADE LTD.Inventor: Lei Wen
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Patent number: 9176552Abstract: Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.Type: GrantFiled: July 9, 2013Date of Patent: November 3, 2015Assignee: ULTRASOC TECHNOLOGIES LTD.Inventor: Andrew Brian Thomas Hopkins
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Patent number: 9179346Abstract: A computing device may obtain n values of a first performance indicator of a network and n values of a second performance indicator of the network. The ith value of the first performance indicator may be based on a measurement of the first performance indicator within an ith time period, and the ith value of the second performance indicator may be based on a measurement of the second performance indicator within the ith time period. A set of aggregate weighted rank values of the first and second performance indicators may be determined. A jth entry in the set of aggregate weighted rank values may be selected, and the jth value of the first performance indicator and the jth value of the second performance indicator may be used to provision the network.Type: GrantFiled: February 24, 2014Date of Patent: November 3, 2015Assignee: Sprint Spectrum L.P.Inventors: Hemanth B. Pawar, Shilpa K. Srivinas, Daniel Vivanco, Krishna Sitaram
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Patent number: 9164853Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: GrantFiled: March 13, 2013Date of Patent: October 20, 2015Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Patent number: 9158606Abstract: Avoiding failure repetition in data processing includes storing a sequence of circumstances leading up to a previous failure, monitoring circumstances in a current process, matching a sequence of circumstances in the current process to a stored sequence of circumstances, and applying rules to determine if the current process should proceed.Type: GrantFiled: January 22, 2010Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Julien Charles Horn, Roger Gordon Lewis, Alan Clive Robinson, Andrew Wright
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Patent number: 9122572Abstract: In one aspect, a service requirements specification specifies data processing resources required to provide a service, and a configuration specification specifies a configuration of data processing resources for providing the service. The service requirements specification and configuration specification are analyzed using resource reliability data for the specified resources to determine a composite risk of degradation of the service. In another aspect, reliability of one or more software modules is projected according to a current state in a development life cycle of the software modules and any of various additional indicators. Preferably, a data processing support provider separate from the service-providing enterprise maintains historical field support data concerning significant field defect events with respect to various resources, and uses this data for projecting reliability of the resources.Type: GrantFiled: March 4, 2013Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventors: John J. Bird, Terry R. Ulmer
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Patent number: 9124490Abstract: Performance metrics may be received from multiple data processing elements associated with a performance metric domain and a consolidated performance metric may be determined. Grouping the performance metrics into performance metric groups may be performed based on their respective associations with different aspects of the data processing elements.Type: GrantFiled: March 15, 2013Date of Patent: September 1, 2015Inventor: Kevin Patrick Burns
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Patent number: 9086874Abstract: A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.Type: GrantFiled: June 7, 2012Date of Patent: July 21, 2015Assignee: Morgan/Weiss Technologies Inc.Inventors: Morgan Johnson, Frederick G. Weiss
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Patent number: 9043659Abstract: In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2012Date of Patent: May 26, 2015Assignee: Intel CorporationInventors: Enric Herrero Abellanas, Xavier Vera, Javier Carretero Casado, Tanausu Ramirez, Nicholas Axelos, Daniel Sanchez
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Patent number: 9043651Abstract: Aspects of the present invention provide a tool for analyzing and remediating an update-related failure. In an embodiment, a failure state of a computer system that has been arrived at as a result of an update is captured. A semantic diff that includes the difference between the failure state and at least one of an original state or a completion state is then computed. This semantic diff is transformed into a feature vector format. Then the transformed semantic diff is analyzed to determine a remediation for the update. Failure and/or resolution signatures can be constructed using the semantic diff and contextual data, and these signatures can be used in comparison and analysis of failures and resolutions.Type: GrantFiled: August 2, 2012Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Vasanth Bala, Niyu Ge, Ea-Ee Jan, Darrell C. Reimer, Lakshminarayanan Renganarayana, Xiaolan Zhang
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Patent number: 9043658Abstract: An asset health monitoring system (AHMS) can assign a confidence indicator to some or all the services of a computing service provider. In response to drops in the confidence indicators, the AHMS can automatically initiate testing of services and/or computing assets associated with the services in order to raise confidence that a particular service and its computing assets will perform correctly. Further, the AHMS can automatically initiate remediation procedures for the particular service and/or specific computing assets that fail the confidence testing. By automatically triggering testing and/or remediation procedures, the AHMS can increase reliability of the computing service provider by preemptively identifying problems.Type: GrantFiled: May 31, 2012Date of Patent: May 26, 2015Assignee: Amazon Technologies, Inc.Inventors: Michael David Marr, Matthew D. Klein
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Patent number: 9043657Abstract: A method to prevent failure on a server computer due to internally and/or externally induced shock and/or vibration. The method includes acquiring, by at least one sensor, analog acceleration data of components in a server computer. The data is then converted to digital format and stored within a motor drive assembly processor memory unit. The processor analyzes the stored data for existence of machine degradation. In response to detecting the existence of machine degradation, the motor drive assembly processor initiates remediation procedures. The remediation procedures include controlling rotating speed of moving devices or performing a complete system shut down.Type: GrantFiled: November 30, 2012Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Budy D Notohardjono, Arkadiy O. Tsfasman
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Publication number: 20150143181Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.Type: ApplicationFiled: January 22, 2015Publication date: May 21, 2015Inventors: Yanyang Xiao, Alexandre Pierre Palus, Karl Friedrich Greb, Kevin Patrick Lavery, Paul Krause
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Patent number: 9037921Abstract: The relative health of data storage drives may be determined based, at least in some aspects, on data access information and/or other drive operation information. In some examples, upon receiving the operation information from a computing device, a health level of a drive may be determined. The health level determination may be based at least in part on operating information received from a client entity. Additionally, a storage space allocation instruction or operation may be determined for execution. The allocation instruction or operation determined to be performed may be based at least in part on the determined health level.Type: GrantFiled: March 29, 2012Date of Patent: May 19, 2015Assignee: Amazon Technologies, Inc.Inventors: Marc J. Brooker, Tobias L. Holgers, Madhuvanesh Parthasarathy, Danny Wei
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Patent number: 9037923Abstract: Various method, system, and computer program product embodiments for facilitating upgrades in a computing storage environment are provided. In one such embodiment, one of an available plurality of rolling upgrade policies registering at least one selectable upgrade parameter for an upgrade window is selected. A node down tolerance factor is set for at least one node in the computing storage environment. The node down tolerance factor specifies a percentage of elements of the at least one node taken offline to apply the selected one of the available plurality of rolling upgrade policies during the upgrade window.Type: GrantFiled: March 12, 2013Date of Patent: May 19, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin L. Andrews, Anthony J. Ciaravella, Joseph W. Dain, Nikhil Khandelwal
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Patent number: 9038076Abstract: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.Type: GrantFiled: August 12, 2013Date of Patent: May 19, 2015Assignees: Synopsys, Inc., Fujitsu Semiconductor LimitedInventors: Mark David Lippett, Ayewin Oung
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Patent number: 9037922Abstract: A set of techniques is described for monitoring and analyzing crashes and other malfunctions in a multi-tenant computing environment (e.g. cloud computing environment). The computing environment may host many applications that are executed on different computing resource combinations. The combinations may include varying types and versions of hardware or software resources. A monitoring service is deployed to gather statistical data about the failures occurring in the computing environment. The statistical data is then analyzed to identify abnormally high failure patterns. The failure patterns may be associated with particular computing resource combinations being used to execute particular types of applications. Based on these failure patterns, suggestions can be issued to a user to execute the application using a different computing resource combination.Type: GrantFiled: May 1, 2012Date of Patent: May 19, 2015Assignee: Amazon Technololgies, Inc.Inventors: Luis Felipe Cabrera, Eric Jason Brandwine, James R. Hamilton, Jonathan A. Jenkins, Matthew D. Klein, Nathan Thomas, Pradeep Vincent
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Patent number: 9032257Abstract: A first interface board includes a first signal processing unit that performs a predetermined process on a signal. A second interface board includes a second signal processing unit that performs the predetermined process on a signal. When no failure occurs in both interface boards, a switching control unit selects the first interface board. When a failure occurs in the first interface board, the switching control unit selects the second interface board. When there is no failure in both the interface boards and the first interface board does not satisfy a predetermined degradation condition, the electrical power supply control unit supplies electrical power to the first interface board and prohibits the supply of electrical power to the second interface board. When there is no failure in both the interface boards but the predetermined degradation condition is satisfied, the electrical power supply control unit supplies electrical power to both the interface boards.Type: GrantFiled: November 14, 2012Date of Patent: May 12, 2015Assignee: Fujitsu LimitedInventors: Nobuo Sashida, Kazushige Saito, Kazuhiko Hata
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Publication number: 20150127995Abstract: Differential health-check systems and accompanying methods provide health-checking and reporting of one or more information management systems in reference to a first time period before and a second time period after a triggering event. A triggering event may be an upgrade of at least part of the information management system, or a restore operation completed in the information management system for example following a disaster, or any number of other events, etc. The health-checking and reporting may comprise a comparison of one or more performance metrics of one or more components and/or operations of the information management system during the first and second time periods.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: CommVault Systems, Inc.Inventors: Sanjay Harakhchand Kripalani, Parag Gokhale
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Patent number: 9026862Abstract: Systems and methods for monitoring operational performance of at least one application containing no explicit instrumentation are described. Data relating to the operational performance of the application can be obtained and provided to a telemetry server for analysis without the use of diagnostic instrumentation within the application. Generic and targeted performance data can be obtained using responsiveness components within a computing operating system.Type: GrantFiled: December 2, 2010Date of Patent: May 5, 2015Inventors: Robert W. Dreyfoos, Jason Carl Hendrickson, Brian D. Wentz, Prashant Ratanchandani, Pavan Kumar Josyula Venkata
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Patent number: 9026307Abstract: A vehicle control system including: a first vehicle control unit configured to include a first vehicle control unit configured to include a first processor installed with a real-time OS; and a second vehicle control unit configured to include a second processor installed with a real-time OS and a third processor installed with a multimedia OS, wherein the first processor and the second processor are configured to perform communication between the first vehicle control unit and the second vehicle control unit, and a communication function of the second processor and a communication function of the third processor are configured to perform communication between the second processor and the third processor.Type: GrantFiled: January 17, 2008Date of Patent: May 5, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Keisuke Okamoto, Nobuhide Sugimoto
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Publication number: 20150121152Abstract: A multi-core processor system includes a first resource, a first core, a second resource, and a second core. The first core runs a first operating system (OS), and the first resource is allocated to the first OS. The second core runs a second OS, and the second resource is exclusively allocated to the second OS. The first OS and the second OS are designed for running at the same time, and the second OS is configured for monitoring or debugging the first resource, the first core, or the first OS.Type: ApplicationFiled: October 29, 2014Publication date: April 30, 2015Inventors: Alpus PC Chen, Chun-Wei Chen, Elysee YH Hsieh, Kelvin Shieh
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Patent number: 9021313Abstract: A system and method are provided for enhancing approximate computing by a computer system. In one example, an interface is provided comprising a variable-identifier module and a bit-priority module. The variable-identifier module is configured to identify one or more variables of data that are to be processed by the computer system with approximate precision. Approximate precision is a precision level at which a hardware device does not guarantee full data-correctness for the one or more variables. The bit-priority module is configured to assign bit-priorities to the one or more variables. The bit-priorities include relative levels of importance among bits of each of the one or more variables. The relative levels of importance include at least high-priority bits and low-priority bits.Type: GrantFiled: November 28, 2012Date of Patent: April 28, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Karin Strauss, Adrian Sampson, Luis Henrique Ceze
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Patent number: 9021314Abstract: Methods, apparatus, and computer-accessible storage media for remotely monitoring and diagnosing storage gateways. Status information may be collected locally on the gateways and uploaded to a service provider via gateway-initiated connections. The uploaded information may be stored to status data store(s). Status proxy(s) on the provider network may analyze the information in the status data store(s) for one or more gateways to detect error conditions on individual gateways or patterns or error conditions on multiple gateways. Upon detecting an error condition on a gateway, the proxy may alert another process, for example an administrator process on the local network that includes the respective gateway. The other process may then message the gateway to address the condition. Information for particular gateways may be provided to clients on request. Information collected from multiple gateways may be viewed and analyzed by the service provider to detect patterns related to gateway design.Type: GrantFiled: January 24, 2014Date of Patent: April 28, 2015Assignee: Amazon Technologies, Inc.Inventors: James Christopher Sorenson, III, Yun Lin, Ardis G. Maison, Nishanth Alapati
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Patent number: 9009542Abstract: An asset health monitoring system (AHMS) can assign a confidence indicator to some or all the monitored computing asset in a data center, such as computing systems or networking devices. In response to drops in the confidence indicators, the AHMS can automatically initiate testing of computing assets in order to raise confidence that the asset will perform correctly. Further, the AHMS can automatically initiate remediation procedures for computing assets that fail the confidence testing. By automatically triggering testing of assets and/or remediation procedures, the AHMS can increase reliability for the data center by preemptively identifying problems.Type: GrantFiled: May 31, 2012Date of Patent: April 14, 2015Assignee: Amazon Technologies, Inc.Inventors: Michael David Marr, Matthew D. Klein
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Patent number: 9003239Abstract: Resolving virtual machine (VM) issues, by executing VM and operating system (OS) diagnostic monitors, including, monitoring a set of VM and OS health status metrics of a system at a first level, analyzing data of the monitored health status metrics to determine that an instability has occurred when the data exceeds defined bounds for the health status metrics, responding to the instability by monitoring additional VM and OS health status metrics, whereby a level of monitoring of the system is increased from the first level to a second level, greater than the first level, identifying the instability, repairing the system by taking corrective action based on the identified instability; and removing at least one of the set of monitoring and profiling tools to reduce the level of monitoring to a third level once the instability has been resolved, wherein the third level is less than the second level.Type: GrantFiled: May 3, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Lisa M. W. Bradley, Kevin Grigorenko, Rohit D. Kelapure, Dana L. Price
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Patent number: 9003233Abstract: In accordance with aspects of the disclosure, systems and methods are provided for monitoring one or more classes for detecting suspected memory leaks in a production environment. The systems and methods may include identifying which of the one or more classes hold at least one static or non-static field of collection or array type, accessing the one or more classes that hold the at least one static or non-static fields of collection or array type, and tracking a size for each field of each class by periodically sampling the size of each field over an interval, processing the size data for each field of each class, and detecting suspected memory leaks of each class by identifying which of the one or more fields of each class exhibits suspect behavior in the size over the interval.Type: GrantFiled: December 31, 2012Date of Patent: April 7, 2015Assignee: BMC Software, Inc.Inventors: Gilad Arbel Komissar, Eyal Koren, Asaf Dafner
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Patent number: 8996924Abstract: A monitoring device including: a receiving unit configured to receive a malfunction notice of a data processing device, the data processing device being connected to the monitoring device which monitors running condition through a network; a malfunction device identification unit configured to identify a data processing device that is malfunctioning based on the received malfunction notice; a data obtaining unit configured to obtain running data and device data of the data processing device that is malfunctioning and an another data processing device; and a malfunction cause identification unit configured to identify a cause of the malfunction, based on the obtained running data and the obtained device data.Type: GrantFiled: December 21, 2011Date of Patent: March 31, 2015Assignee: Fujitsu LimitedInventor: Mitsuru Maejima
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Patent number: 8996751Abstract: An information handling system includes a processor, a memory communicatively coupled to the processor, and an information storage device coupled to the processor via an input/output (I/O) bus for communicating I/O data between the processor and the information storage device. The device further receives a specification of reporting criteria for information storage device parameters.Type: GrantFiled: January 11, 2013Date of Patent: March 31, 2015Assignee: Dell Products, LPInventors: David M. Pereira, James P. Giannoules, Chandrashekar Nelogal
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Patent number: 8996915Abstract: Test data generation and scale up for database testing using unique common factor sequencing can include selecting a column of a table for which test data is needed and generating test data for the column that replicates cardinality characteristics of an existing production dataset and that includes a local predicate of a workload.Type: GrantFiled: June 29, 2012Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Austin Clifford, Enda McCallig, Gary F. Murtagh
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Patent number: 8996923Abstract: A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.Type: GrantFiled: November 29, 2012Date of Patent: March 31, 2015Assignee: Intel CorporationInventors: Christopher J. Hughes, Jesus Corbal, Mark J. Charney, Milind B. Girkar, Elmoustapha Ould-Ahmed-Vall, Robert Valentine
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Patent number: 8990635Abstract: Techniques for managing errors within an application are provided. Embodiments monitor errors occurring in each of a plurality of portions of the application while the application is executing. An error occurring in a first one of the plurality of portions of the application is detected. Additionally, upon detecting the error occurring in the first portion, embodiments determine whether to prevent subsequent executions of the first portion of the application.Type: GrantFiled: December 22, 2011Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Michael J. Branson, John M. Santosuosso, Brandon W. Schulz