Of Peripheral Subsystem Patents (Class 714/5.1)
  • Patent number: 10289500
    Abstract: One embodiment provides a storage system. The storage system includes storage system control logic to identify at least one target storage device in response to detection of a failed storage device, request a state of a target device logical block address (LBA) from each of the at least one target storage device, and read data associated with a mapped device LBA from each target storage device and write the data to at least one replacement storage device. Another embodiment provides a storage device. The storage device includes device control logic to determine a state of a target device logical block address (LBA) in response to a request; a host interface to provide a reply to the request, the reply including a state indicator related to the state of the target device LBA; a map table including a plurality of device LBAs and respective state indicators; and non-volatile memory (NVM) including data related to at least one mapped LBA.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventor: Jonmichael P. Hands
  • Patent number: 10185619
    Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Theodros Yigzaw, Ashok Raj, Robert Swanson, Mohan J. Kumar
  • Patent number: 10073642
    Abstract: A method for operating a data storage device including a plurality of memory regions. The method includes performing a read operation for a first memory region, increasing a read count based on read sequences of the first memory region and a second memory region which has been read before the read operation for the first memory region, and performing a management operation for the plurality of memory regions based on the read count.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: September 11, 2018
    Assignee: SK Hynix Inc.
    Inventor: Ik Joon Son
  • Patent number: 10042577
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by identifying a data object to access within a DSN. The method continues by identifying a vault ID based on the data object. The method continues by obtaining an object ID based on the data object. The method continues by selecting at least one generation ID based on generation status. The method continues, for each generation ID, by generating at least one set of slice names using the vault ID, the generation ID, and the object ID. The method continues, for each set of slice names, by generating a set of slice access requests that includes the set of slice names and accessing the DSN utilizing the set of slice access requests.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wesley B. Leggette, Jason K. Resch, Eric G. Smith, Sebastien Vas, Yogesh R. Vedpathak
  • Patent number: 10017188
    Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Axel Freiwald, Bejoy Mathews, Antonio Vilela
  • Patent number: 9959175
    Abstract: Systems and methods for a backing up and/or restoring data in a cloud based application are provided. Objects that are deleted in bulk are restored in bulk. The relationships between the objects that were deleted are determined at the time of backup and used during the restore process. The restored objects have the same relationships as the original objects even when the objects are not identical. The restore process accounts for data or information in the objects that cannot be restored or that is assigned by the web application to which the objects are restored.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 1, 2018
    Assignee: Spanning Cloud Apps, LLC
    Inventors: Brandon Mayes, Joel Rosinbum, Patricia Cifra, Gregory L. Alexander
  • Patent number: 9950710
    Abstract: A device for operating an apparatus comprising a first controller configured to be controlled by a first control signal, a second controller configured to be controlled by a second control signal, a control unit operatively connected to the first controller and the second controller, wherein the first controller and the second controller are both configured to operate the apparatus.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Axel Freiwald, Bejoy Mathews, Antonio Vilela
  • Patent number: 9921915
    Abstract: A method for recovering a baseboard management controller (BMC) by determining, by a basic input/output system (BIOS), whether a BMC recovery mode is generated by a recovery mode jumper being triggered. The system performing the method can further install, if the recovery jumper is not triggered, a BMC firmware update driver and detect, if the recovery jumper is not triggered, a BMC image. The system that performs the method can further update, if the recovery jumper is not triggered, the BMC firmware and copy to a backup image, if the recovery jumper is not triggered, the BMC firmware update.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: March 20, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventor: Ming-Hung Hung
  • Patent number: 9916216
    Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) is assigned to backup the master PHB that satisfies the error threshold. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse P. Arroyo, Anjan Kumar Guttahalli Krishna
  • Patent number: 9912191
    Abstract: Maintenance of reliable and highly available electronic systems to perform servicing and preventive maintenance may need to be performed without interruption of operations. Removal of circuit cards from a chassis may render the connectors on a chassis vulnerable to inadvertent short circuiting of power sources by stray metallic objects. A configuration where the power is removed from a connector as the circuit card is being extracted eliminates his possibility. The control circuits for the power supply connections and the power supplies are themselves redundant so that they may be similarly serviced.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 6, 2018
    Assignee: VIOLIN SYSTEMS LLC
    Inventors: John R. Sisler, John C. Ottesen, Russell T. Baca, Jean-Phillipe Fricker
  • Patent number: 9779044
    Abstract: A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that is exclusive to a particular task during a duration of time. The processor core accesses the task memory location of the local memory during the execution of the particular task, and modifies to the block of data stored in the task memory location. The extent monitor monitors a write operation the processor core to the local memory to determine a first most-extreme address of the task memory location modified by the execution of the particular task during the duration of time. The processor core also executes a write back instruction to write back to a shared memory location less than the entire block of data based upon the most-extreme address.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 3, 2017
    Assignee: NXP USA, Inc.
    Inventor: William C. Moyer
  • Patent number: 9747028
    Abstract: Techniques for addressing performance degradation when a computer system is in a memory constrained state while running one or more applications are described herein. While executing, a computer system may monitor system memory and record one or more tracked sample types and may use the collection of tracked sample types to aggregate memory size equivalents to the tracked sample types and calculate a simulated memory pressure. The simulated memory pressure may be applied to the system by allocating memory from a memory manager, thereby reducing memory pressure.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: August 29, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Nicholas Alexander Allen
  • Patent number: 9747058
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 29, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gi-Won Oh, Ju-Yun Jung, Soo-Hyeong Kim, Hyun-Joong Kim
  • Patent number: 9703629
    Abstract: Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: July 11, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Sateesh Desireddi, Nagi Reddy Chodem, Sachin Krishne Gowda
  • Patent number: 9703744
    Abstract: In a storage subsystem adopting HDD and PCIe-SSD as storage media, as a method for preventing the complication of having to select a removal method while considering the drive type inserted to the drive slot since the method for removing the HDD differs from the method for removing the PCIe-SSD according to the prior art, the present invention provides an LED for displaying whether it is possible to remove the HDD or the PCIe-SSD inserted to the slot of a drive enclosure, wherein when an HDD is inserted in the drive slot, the LED displays that removal of the HDD is enabled when power supply to the HDD is stopped, and when PCIe-SSD is inserted to the drive slot, the LED displays that removal of the SSD is enabled when Downstream Port Containment (DPC) is triggered in the downstream port of the PCIe switch to which the SSD is connected.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 11, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Masanori Takada, Naoya Okada
  • Patent number: 9679600
    Abstract: Some embodiments include a cold storage system that processes an input/output (I/O) request. The cold storage system can have a buffer rack and one or more archival storage racks. The buffer rack can be closer to an I/O drive of the cold storage system than the archival storage racks. The cold storage system can operate a fetcher robot to pre-fetch a first data storage medium from the archival storage racks to the buffer rack. The cold storage system can operate a buffer robot to move a second data storage medium from a slot in the buffer rack to the I/O drive. The cold storage system can execute, according to the I/O request, an I/O operation on the second data storage medium at the I/O drive.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 13, 2017
    Assignee: Facebook, Inc.
    Inventor: Jason David Adrian
  • Patent number: 9671772
    Abstract: One embodiment provides an apparatus. The apparatus includes a contextual clothing controller. The contextual clothing controller includes clothing selection logic. The clothing selection logic is to identify a clothing article based, at least in part, on a predicted target clothing characteristic. The clothing selection logic is further to determine a location of the identified clothing article in a storage system.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Shahar Taite, Tomer Rider
  • Patent number: 9658892
    Abstract: Embodiments of the invention relate to management of hybrid workloads, including serial and parallel workload optimizations, in a shared pool of configurable computer resources. Resource utilization in the shared pool is dynamically tracked, and employed for assessing a set of servers a parallel access protocol should utilize for one or more I/O requests in conjunction with any serial workload optimizations. Accordingly, the load balancing embodies a diverse set of workloads to support dynamic and equitable allocation.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dean Hildebrand, Sandip Agarwala
  • Patent number: 9652726
    Abstract: A computer-implemented method, computer program product, and computing system for obtaining a simulation modeling file. One or more values is associated with one or more variables included within the simulation modeling file. The simulation modeling file is executed to generate at least one result set. The at least one result set is iteratively rendered while the at least one result set is generated.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: May 16, 2017
    Assignee: X Systems, LLC
    Inventors: Nigel James Brock, Geoffrey John George Wilby
  • Patent number: 9613102
    Abstract: A method of ranking data visualizations is performed at a computing device having one or more processors and memory. The memory stores one or more programs for execution by the one or more processors. A user selects a set of data fields from a set of data. The computing device identifies a plurality of data visualizations based on the data fields selected by the user. For each of the plurality of data visualizations, a score is computed based on a set of ranking criteria. A first ranking criterion of the set of ranking criteria is based on values of one or more of the user-selected data fields in the set of data. A ranked list of the data visualizations is created, which is ordered according to the computed scores of the data visualizations. The ranked list is presented to the user.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: April 4, 2017
    Assignee: TABLEAU SOFTWARE, INC.
    Inventors: Anushka Anand, Jock Douglas Mackinlay, Kanit Wongsuphasawat
  • Patent number: 9606735
    Abstract: An operational management server manages a storage device that includes a plurality of types of disks having different performances. A setting unit sets a target value of a performance to a volume produced by using the different types of the disks. An allocation rate management unit determines allocation rates of the respective types of the disks included in the volume on the basis of the target value set by the setting unit, and instructs the storage device to reproduce the volume in accordance with the determined allocation rates.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Hamano, Toshiharu Makida, Kiyoshi Sugioka, Motohiro Sakai
  • Patent number: 9609264
    Abstract: A method, system, and non-transitory computer-readable storage medium for implementing backup recording of events are disclosed. The method may include detecting, by a personal video recorder (PVR) cluster coordinator, an interruption in a current or scheduled recording of an event at a first PVR. The method may further include determining, by the PVR cluster coordinator, a PVR cluster corresponding to the first PVR in response to the detection, the PVR cluster comprising a plurality of PVRs and including the first PVR. The method may further include facilitating, by the PVR cluster coordinator, a backup recording of the interrupted recording at a serving PVR in the PVR cluster after determining the PVR cluster corresponding to the first PVR. Further, the PVR cluster coordinator may be implemented by at least one computer processor.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 28, 2017
    Assignee: WIPRO LIMITED
    Inventors: Mohammed Junaid Kottikulam, Dhanya Unnikrishnan, Saira Thampi
  • Patent number: 9570198
    Abstract: It is determined that a read count has reached one of a set of read count thresholds. An initial test page which corresponds to the read count threshold that has been reached is selected from a set of initial test pages. There is at least one page that is not in the set of initial test pages and is victimized by an offending page that also victimizes a page in the set of initial test pages. A test read is performed on the selected test page and the results of the test read of the selected test page are evaluated for read disturb noise.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: February 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jason Bellorado, Zheng Wu, Lingqi Zeng
  • Patent number: 9521087
    Abstract: A system and method for serving requests using multiple release cycles is disclosed. The data release application includes a controller, a configuration data engine, a matching engine and a rendering engine. The controller receives a request from a client. The configuration data engine determines a set of criteria and a collection of release datasets corresponding to configuration data. The matching engine matches the request with the set of criteria and determines a combination of release cycle and release stage for servicing the request. The rendering engine retrieves a release dataset from the collection of release datasets that corresponds to the combination of release cycle and release stage and generates a response based on the release dataset.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: December 13, 2016
    Assignee: Google Inc.
    Inventors: Konstantinos Panteleimon Krikellas, Venkat Venugopalan
  • Patent number: 9507703
    Abstract: In a storage control apparatus, an acquiring unit acquires first information indicating the frequency of random access to a first logical region and second information indicating the data size of random access, based on the content of access from the information processing apparatus. A controlling unit determines the size of storage areas to be allocated to a second logical region based on the second information indicating the data size of random access when the first information indicates that the frequency of random access is equal to or greater than a threshold value. The controlling unit creates the second logical region using a plurality of storage devices. The controlling unit controls access from the information processing apparatus such that the access is made to the second logical region instead of the first logical region.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiko Muroyama, Masahiro Yoshida, Tadashi Matsumura, Noriyuki Yasu, Motoki Sotani
  • Patent number: 9501397
    Abstract: A data writing method and a memory controller and a memory storage apparatus using the same are provided. The data writing method includes grouping a plurality of physical blocks into a plurality of physical units, grouping the physical units into at least a data area and a free area, and configuring a plurality of logical units for mapping to the physical units of the data area. The data writing method also includes getting a physical unit from the free area, writing data in at least one of the logical units into the gotten physical unit, and writing an end mark into the gotten physical unit, and in the gotten physical unit, the end mark follows the data belonging to the at least one logical unit. Thereby, the storage space of each physical unit can be effectively used, and the lifespan of the memory storage apparatus can be prolonged.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: November 22, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Yi-Hsiang Huang
  • Patent number: 9477550
    Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Benjiman L. Goodman, Luis A. Lastras-Montano, Eric E. Retter, Kenneth L. Wright
  • Patent number: 9476657
    Abstract: Techniques for controlling a data center cooling system include polling a plurality of control devices associated with the data center cooling system for a respective state of each of the control devices; receiving, from each of the plurality of control devices, a response that includes the respective state; aggregating the responses from the plurality of control devices; executing a control algorithm that includes the aggregated responses as an input to the algorithm and an output that includes a setpoint of the plurality of control devices; and transmitting the output to the plurality of control devices.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: October 25, 2016
    Assignee: Google Inc.
    Inventors: Nathaniel Edward Pettis, Andrew H. Tibbits
  • Patent number: 9465706
    Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is reset, the host computing device may include a PCI communication path for maintaining communication between the system resources and the I/O devices. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state. The host may monitor the errors generated by a plurality of master PHBs and select a master PHB that satisfies an error threshold. The second PHB (i.e., a servant PHB) and the selected master PHB are synchronized, and the second PHB is coupled to the PCI communication path between the master PHB and a PCI switch. The master PHB can then be reset while the second PHB maintains PCI communication between the host and the I/O devices.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse P. Arroyo, Anjan Kumar Guttahalli Krishna
  • Patent number: 9442839
    Abstract: A non-volatile storage system comprises a controller and one or more memory die in communication with the controller. The controller sends data and an initial address in conjunction with a request to program the data to one of the memory die. The memory die comprises a plurality of non-volatile storage elements and one or more control circuits. The one or more control circuits attempt to program the data to the non-volatile storage elements at the initial address and determine that programming of the data at the initial address fails. The one or more managing circuits automatically identify a new address in the memory die without the memory die being instructed of the new address by the controller and program the data at the new address on the memory die without the data being re-transmitted from the controller to the memory die.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Aditya Pratap Sharma, N. Balasiva Kumar, Vimal Kumar Jain
  • Patent number: 9436407
    Abstract: Methods and systems for cursor remirroring are disclosed. A mirroring process is initiated for a plurality of chunks stored by a master node. The mirroring process comprises visiting a sequence of one or more of the chunks and, for at least some of the chunks, copying chunk data or metadata to a slave node. During the initiated mirroring process, a request is received for a write operation on one of the chunks stored by the master node. If the chunk in the request has been visited in the mirroring process, the write operation is performed on the master node and on the slave node. If the chunk in the request has not been visited, the write operation is performed on the master node and postponed on the slave node until the chunk in the request has been visited in the mirroring process.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: September 6, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Jianhua Fan, Kerry Quintin Lee, Danny Wei, Tate Andrew Certain
  • Patent number: 9423984
    Abstract: The storage system includes a plurality of storage devices. A storage controller is configured to manage a plurality of pages in a pool provided by at least one of the plurality of storage devices, to provide a virtual storage area to a host by allocating one or more pages from the pool dynamically, in which the virtual storage area is formed with a data area and a control information area. The storage controller is further configured to expand the virtual storage area on a unit basis, where the unit is a set of a given size area of the data area and a given size area of the control information area. In response to a write request from the host, the storage controller is configured to store data into the data area and to store control information for accessing to the data into the control information area.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: August 23, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Kohei Tatara, Yoshiaki Eguchi, Hisaharu Takeuchi
  • Patent number: 9411667
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Sarathy Jayakumar, Mohan J. Kumar, Jose A. Vargas
  • Patent number: 9407953
    Abstract: Various embodiments reduce disruptions in recorded programming, by automatically recording retransmissions of prior programming. In one embodiment, a recording manager is provided for execution on a receiving device, such as a set-top box. The recording manager detects a disruption in a recorded program. In response, the recording manager automatically records, or schedules a recording of, a later transmission of the same program. This abstract is provided to comply with rules requiring an abstract, and it is submitted with the intention that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 2, 2016
    Assignee: EchoStar Technologies L.L.C.
    Inventor: Phuc H. Nguyen
  • Patent number: 9389958
    Abstract: In one embodiment, a file system driven RAID rebuild technique is provided. A layered file system may organize storage of data as segments spanning one or more sets of storage devices, such as solid state drives (SSDs), of a storage array, wherein each set of SSDs may form a RAID group configured to provide data redundancy for a segment. The file system may then drive (i.e., initiate) rebuild of a RAID configuration of the SSDs on a segment-by-segment basis in response to cleaning of the segment (i.e., segment cleaning). Each segment may include one or more RAID stripes that provide a level of data redundancy (e.g., single parity RAID 5 or double parity RAID 6) as well as RAID organization (i.e., distribution of data and parity) for the segment. Notably, the level of data redundancy and RAID organization may differ among the segments of the array.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: July 12, 2016
    Assignee: NetApp, Inc.
    Inventors: Rajesh Sundaram, Bharat Baddepudi, Jeffrey S. Kimmel, T. Byron Rakitzis
  • Patent number: 9378093
    Abstract: Methods, apparatus and computer programs have been provided for mitigating a problem of non-optimal recovery from storage device failures. A method involves determining a required write performance for rebuilding data of a failed device, based at least partly on the potential read performance of storage devices in a data rebuild; and allocating a virtual storage area within available storage, which allocation of virtual storage is based at least partly on the required write performance. Data is rebuilt by writing to the allocated virtual storage area, and data recovery is completed by migrating this rebuilt data to at least one data storage device such as a spare physical storage device within the array.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alastair Cooper, Gordon D. Hutchison
  • Patent number: 9324458
    Abstract: Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-joong Kim, Tae-young Oh
  • Patent number: 9311304
    Abstract: A type of a storage subsystem that has been connected to a computing device is detected as one of a number of types including a first type and a second type (602). The first type of storage subsystem has a number of storage devices in which data to be stored on the storage subsystem is duplicated within the storage subsystem itself. The second type of storage subsystem has a number of storage devices in which the data to be stored on the storage subsystem is not duplicated within the storage subsystem itself. A data duplication policy for the storage subsystem is set in accordance with the type that has been determined (608).
    Type: Grant
    Filed: June 20, 2010
    Date of Patent: April 12, 2016
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Paul Boerger
  • Patent number: 9311187
    Abstract: A method begins by a dispersed storage (DS) processing module receiving a request to store data in a dispersed storage network and determining dispersed storage error encoding parameters for encoding the data into sets of encoded data slices. The method continues with the DS processing module determining whether the request includes a desired write reliability indication. When the request includes the desired write reliability indication, the method continues with the DS processing module determining whether storage of the sets of encoded data slices is meeting the desired write reliability indication. When storage of a set of encoded data slices is not meeting the desired write reliability indication, the method continues with the DS processing module determining a storage compliance process for the set of encoded data slices to meet the desired write reliability indication and executing the storage compliance process for the set of encoded data slices.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: April 12, 2016
    Assignee: CLEVERSAFE, INC.
    Inventors: Jason K. Resch, Wesley Leggette
  • Patent number: 9285998
    Abstract: For data processing in a distributed computing storage environment by a processor device, the distributed computing environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, groups of data segments and clumped hot ones of the data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to use a Solid State Drive (SSD) portion of the tiered levels of storage; uniformly hot groups of data segments are determined using a first, largest granulated, heat map for a selected one of the group of the data segments; and a second heat map, which is smaller than the first and having the largest granularity of the first heat map, is used to determine the clumped hot groups.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
  • Patent number: 9262089
    Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and changing a logical address of the at least one data segment to point to the target.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 9262088
    Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, and reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 9215066
    Abstract: Information in a data set of a copy-on-write file system may be made inaccessible. A first key for encrypting a data set of a copy-on-write file system is generated and wrapped with a second key. An encrypted data set is created with the first key. The wrapped first key is stored with the encrypted data set. A command to delete the encrypted data set is received and the second key is altered or changed to make information in the encrypted data set of the copy-on-write file system inaccessible.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: December 15, 2015
    Assignee: Oracle America, Inc.
    Inventors: Darren James Moffat, James Prescott Hughes
  • Patent number: 9195577
    Abstract: Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 24, 2015
    Assignee: Intel Corporation
    Inventors: Ruchir Saraswat, Matthias Gries
  • Patent number: 9165164
    Abstract: Provided is a cryptographic processing apparatus for a storage medium, including: a location information conversion unit that stores a conversion result in a buffer, the conversion result obtained by performing a conversion process on location information indicating a location of data to be accessed on the storage medium; and a data cryptographic processing unit that performs cryptography processing on the data using the conversion result stored in the buffer, the cryptography processing being one of encryption and decryption.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masao Manabe
  • Patent number: 9158673
    Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: October 13, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Cheng-Chung Song
  • Patent number: 9135173
    Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, a Solid State Device (SSD) tier is variably shared between the lower-speed cache and the managed tiered levels of storage such that the managed tiered levels of storage are operational on large data segments, and the lower-speed cache is allocated with the large data segments, yet operates with data segments of a smaller size than the large data segments and within the large data segments.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta, Karl A. Nielsen
  • Patent number: 9122604
    Abstract: Method for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ronald E. Freking, Elizabeth A. McGlone, Nicholas V. Tram, Curtis C. Wollbrink
  • Patent number: 9123409
    Abstract: A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: September 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sean Eilert, Mark Leinwander
  • Patent number: 9104741
    Abstract: A method, apparatus, article of manufacture, and system are presented for establishing redundant computer resources. According to one embodiment, in a system including a plurality of processor devices and a plurality of storage devices, the processor devices, the storage devices and the management server being connected via a network, the method comprises storing device information relating to the processor devices and the storage devices and topology information relating to topology of the network, identifying at least one primary computer resource, selecting at least one secondary computer resource suitable to serve as a redundant resource corresponding to the at least one primary computer resource based on the device information and the topology information, and assigning the at least one secondary computer resource as a redundant resource corresponding to the at least one primary computer resource.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 11, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Akira Fujibayashi