Abstract: An information processing apparatus is disclosed. A processor acquires an upper limit and a lower limit of a probability of a false positive for each of multiple tests based on data-after-aggregation pertinent to a presence or absence of a specific event occurrence acquired by multiple testing, and sets a value from multiple upper limits being acquired. The processor calculates the probability of the false positive with respect to each of tests having lower limits less than the value, and acquires a set of probabilities of the false positive.

Abstract: A position detecting apparatus includes a signal detecting unit that detects a plurality of periodic signals, a correction unit configured to correct the plurality of periodic signals using a correction value to generate a plurality of correction signals, a first calculating unit configured to generate a plurality of displacement signals based on the plurality of correction signals and to calculate the position based on the plurality of displacement signals, a second calculating unit configured to calculate a reliability based on the plurality of displacement signals, and a correction value adjusting unit configured to adjust the correction value based on the reliability. The second calculating unit calculates a first reliability corresponding to a first correction value and a second reliability corresponding to a second correction value, and changes the first correction value to the second correction value when the second reliability is higher than the first reliability.

Abstract: An approach for performing mobile visual search uses deep variant coding of images to reduce the amount of data transmitted from mobile devices to a search server and to provide more efficient indexing and searching on the search server. The amount of data used to represent an image varies depending upon the content of the image and is less than conventional fixed bit length hashing approaches. Denser regions of a feature space are represented by more encoding bits and sparser regions of the feature space are represented by fewer encoding bits, so that the overall number of encoding bits for an image feature is reduced. The approach generally involves determining a set of hash functions that provide deep hashing with more evenly-distributed hash buckets. One or more additional hash functions may be selectively generated for particular hash buckets that contain more than a specified number of images.

Abstract: A method of soft decoding received signals. The method comprises defining quantisation intervals for a signal value range, determining a number of bits detected in each quantisation interval, a number of bits in each quantisation interval that are connected to unsatisfied constraints and a probability that the error correction code is unsatisfied, determining an overall bit error rate based on the probability that the error correction code is unsatisfied, determining a log likelihood ratio for each quantisation interval based on the overall bit error rate, the number of bits detected in each quantisation interval and the number of bits in each quantisation interval that are connected to unsatisfied constraints and performing soft decoding using the log likelihood ratios.

Abstract: A method and apparatus for adaptive calibration scheduling is disclosed. A calibration circuit may perform calibrations of a delay applied to a data strobe conveyed from a memory controller to the memory, and may also calibrate a reference voltage. After calibrating the data strobe delay, a current width of an eye opening and a current score are determined. If the eye opening is not less than a minimum threshold and the current score is within a specified range of a reference score, the reference voltage calibration, if conditionally scheduled, is inhibited. The results of the calibration may be recorded in a history table. A timer may advance a pointer provided to a sequence table at a rate determined by information stored in the history table. Information stored in an entry of the sequence table may indicate which calibration procedures are to be performed during the next calibration cycle.

Abstract: Systems and methods are disclosed for implementing error correction control regions (ECC) in a memory device without the need to ECC protect the entire memory device. An exemplary method comprises defining one or more ECC regions in a memory device, the memory device coupled to a system on a chip (SoC). An ECC block is provided on the SoC, the ECC block in communication with the one or more ECC regions in the memory device. A determination is made with the ECC block whether to store data in a first of the one or more ECC regions. Responsive to the determination ECC bits are generating for, and interleaved with, the received data and interleaved ECC bits and data are caused to be written to the first ECC region. Otherwise, received data is sent to a non-ECC region of the memory device.

Abstract: A controller for a solid state drive is proposed. The solid state drive comprises memory cells each one for storing a symbol among a plurality of possible symbols that the memory cell is designed to store. The controller comprises a unit for encoding information bits into encoded bits; a unit for mapping the encoded bits into the symbols, wherein the symbols are determined based on a plurality of allowed symbols, among the possible symbols, that the memory cells are allowed to store, whereas the symbols, among the possible symbols, other than the allowed symbols define forbidden symbols not allowed to be stored in the memory cells; a unit for demapping read symbols and for providing an indication of the reliability of the read symbols based on the forbidden symbols; and a unit for soft decoding the read symbols according to the reliability indication thereby obtaining the information bits.

Abstract: Embodiments are provided for early termination of an iterative process of determining channel directions and transmissions in multi-user multiple-input and multiple-output (MU-MIMO) communications systems. In an embodiment, a base station or a user equipment (UE) calculates a multi-user channel matrix using a first iteration of a null-space singular value decomposition (SVD) based iterative zero-forcing (I-ZF) algorithm for multi-user MU-MIMO. The base station or UE repeats updating the multi-user channel matrix using a next iteration of the algorithm and the multi-user channel matrix calculated in a previous iteration, until the diagonal elements of the multi-user channel matrix are greater than the off-diagonal elements by a predefined threshold. Upon determining that the diagonal elements are greater than the off-diagonal elements by the predefined threshold, a plurality of transmission signals are calculated using the last updated multi-user channel matrix.

Abstract: A tool for testing a double data rate (“DDR”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye.

Abstract: A method and system for identification of a deviation from a periodic behavior pattern in a sequence of multimedia content segments are provided. The system comprises receiving the sequence of multimedia content segments; generating at least one signature for each multimedia content segment of the sequence of multimedia content segments; comparing at least two signatures generated for at least two consecutive multimedia content segments to detect a periodic behavior pattern; upon detecting the periodic behavior pattern, comparing at least one signature generated for at least a subsequently received multimedia content segment to at least one signature representing the detected multimedia content segment to identify a deviation from the periodic behavior pattern; and upon identifying the deviation from the periodic behavior pattern, generating a notification with respect to the at least one deviation.

Abstract: Serializer-Deserializer (SerDes) operation is optimized for signals based on signal error statistics. Forward Error Correction (FEC) may provide feedback of error statistics or error correction statistics to a SerDes tuner, which uses the statistics to selectively tune or adjust SerDes operating parameters, such as vertical and horizontal sampling or slicing offsets, gain and equalization, to decrease the bit error rate (BER). Statistics report which bits and patterns are corrected and to what values. Knowledge of expected and actual signals is leveraged to correlate detected errors with underlying problems and solutions to optimize SerDes operation. Each node in a network, such as a Ethernet Passive Optical Network (EPON), is enabled to fine tune its operation independently for each logical or physical channel.

Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.

Abstract: An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval.

Abstract: In an error correction device, a frame generation section receives pulse signals as temperature information of a power switching element transmitted from a PWM comparator. The frame generation section sets a first correction pulse signal, a second correction pulse signal and the temperature information sequentially into each frame. A pulse width of the first correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 100%. A pulse width of the second correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 50%. A microcomputer receives the temperature information through a photocoupler and corrects the received temperature information. The microcomputer calculates a temperature detection value of the power switching element on the basis of the corrected temperature information.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.

Abstract: Tools and techniques are described for synchronization and collaboration within peer-to-peer and client/server environments. These tools may provide methods that include establishing peer-to-peer relationships between two or more client systems. These relationships enable the client systems to create respective local instances of workspaces, shared between the client systems to allow them to collaborate with one another. The client systems may participate in peer-to-peer synchronization flows with one another, with the synchronization flows representing updates made local to the shared workspaces of the client systems. The methods may also establish establishing a client/server relationship between one of the client systems and a server system. Through this client/server relationship, the client and server systems may participate in client/server synchronization flows, with these flows representing updates made to the local shared workspace at the client system.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: In an error correction device, a frame generation section receives pulse signals as temperature information of a power switching element transmitted from a PWM comparator. The frame generation section sets a first correction pulse signal, a second correction pulse signal and the temperature information sequentially into each frame. A pulse width of the first correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 100%. A pulse width of the second correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 50%. A microcomputer receives the temperature information through a photocoupler and corrects the received temperature information. The microcomputer calculates a temperature detection value of the power switching element on the basis of the corrected temperature information.

Abstract: A sensor device for an electronic apparatus, including a sensing structure for generating a first detection signal, and a dedicated integrated circuit connected to the sensing structure for detecting a first event associated with the electronic apparatus and for generating a first interrupt signal upon detection of the first event. The dedicated integrated circuit detects the first event as a function of a temporal evolution of the first detection signal, and in particular as a function of values assumed by the first detection signal within one or more successive time windows, and of a relation between the values.

Abstract: A method of securely transferring data. The source data stored in a source memory (NV_MEM) is compared with the transferred data (COPY_ELT_X_V_MEM) that has been copied from the source memory (NV_MEM) into a “destination” memory (V_MEM). The method consists in reading from the source memory (NV_MEM) an integrity value (PI_ELT_X) associated with an element (ELEMENT_X_NV_MEM) such as file containing the source data, in calculating the integrity of a reconstituted element made up of the transferred data (COPY_ELT_X_V_MEM) associated, where appropriate, with the data of the source element (ELEMENT_X_NV_MEM) other than the data that was transferred, and in deciding that the transferred data (COPY_ELT_X_V_MEM) is identical to the source data when the integrity calculation gives a value identical to the integrity value of the source element (PI_ELT_X). The method applies to transferring data between components of a smart card.

Abstract: A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as Dn. Symbols located in the FIFO before Dn are referred to as Dn?x. Symbols located in the FIFO after Dn are referred to as Dn+x. Dn differs from the other FIFO symbols in that its signal level can be measured with an adjustable error slicer. The ISI effect of any Dn?k upon Dn can be measured, and thus any PR[k] measured, by measuring the average signal level of Dn when only certain types of data streams occur in the FIFO.

Abstract: A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract: Methods and apparatus are provided for computing a probability value of a received value in communication or storage systems. A probability value for a received value in a communication system or a memory device is computed by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the probability value using the set of parameters associated with the identified segment.

Abstract: A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.

Abstract: A computationally-simplified approach to expected symbol value determination is based on classifying soft bit information corresponding to symbols in a received communication signal as being reliable or unreliable, and computing expected symbol values for the symbols based on the classified soft bit information. Classification can be carried out by “quantizing” the soft bit information to coarsely indicate whether individual symbol bits are known with high or low probability. Using quantized soft bit information greatly simplifies expected symbol value calculation, yet the calculated values still reflect a scaling corresponding to the underlying reliability of the soft bit information.

Abstract: A method and apparatus for dynamically adjusting power of a transmitter is herein described. A transmitter transmits a pattern to a receiver at a differential voltage. The length of the pattern, in one embodiment, is selected to be a reasonable length training pattern, as not to incur an extremely long training phase. If errors are detected at the receiver in the pattern, the transmitter steps the differential voltage until errors are not detected in the pattern at the receiver. The differential voltage, where no errors are detected, is scaled by a proportion of a target confidence level to a measured confidence level associated with the reasonable length training pattern. As a result, a training phase is potentially reduced and power is saved while not sacrificing confidence levels in error rates in the data exchange between the transmitter and receiver.

Abstract: One embodiment of the invention includes a quantum system. The system includes a superconducting qubit that is controlled by a control parameter to manipulate a photon for performing quantum operations. The system also includes a quantum resonator system coupled to the superconducting qubit and which includes a first resonator and a second resonator having approximately equal resonator frequencies. The quantum resonator system can represent a first quantum logic state based on a first physical quantum state of the first and second resonators with respect to storage of the photon and a second quantum logic state based on a second physical quantum state of the first and second resonators with respect to storage of the photon.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic of the identified defective memory cells. The data is encoded using the selected ECC and the encoded data is stored in the group of the analog memory cells. In an alternative method, an identification of one or more defective memory cells among the analog memory cells is generated. Analog values are read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells. The analog values are processed using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.

Abstract: According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result.

Abstract: Provided are an apparatus and method for generating a soft bit metric and a multi-level (M-ary) Quadrature Amplitude Modulation (QAM) receiving system using the same. The apparatus includes an analog to digital converter for converting an analog symbol signal of a demodulated I (Inphase) or Q (Quadrature) channel into a digital signal, a scaler for scaling the converted digital signal based on a reference value used for determining a space between symbols, a positive integer converter for calculating a positive integer of the scaled digital I or Q channel symbol signal, a sign determinator for determining a sign of the scaled digital I or Q channel symbol signal, and a bit information converter for converting the scaled digital I or Q channel symbol signal into soft bit metric information per bit on the basis of the calculated positive integer and the determined sign value.

Abstract: A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a predetermined frequency in synchronization with a reference strobe signal. A latch circuit latches the signal to be tested at an edge timing of an output signal of the oscillator. A gate circuit is provided between a clock terminal of the latch circuit and the oscillator, and makes the output signal of the oscillator pass therethrough for a predetermined period. A clock transfer circuit loads the output signal of the latch circuit at an edge timing of the output signal of the oscillator and performs retiming on the output signal of the latch circuit by using a reference clock.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: The present specification describes techniques and apparatus that adjust filter tap values to be used in filtering a data value input to a detector and/or that increase or decrease a threshold value used to determine whether to adjust the filter tap values.

Abstract: Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern determined according to a test signal to be supplied to the device under test; a timing signal generating section that generates a timing signal indicating a timing for supplying the test signal to the device under test; a digital filter that filters the test pattern to output a jitter control signal representing jitter corresponding to the test pattern; a jitter injecting section that injects the timing signal with jitter by delaying the timing signal according to the jitter control signal; and a waveform shaping section that generates the test signal formed according to the test pattern, with the timing signal into which the jitter is injected as a reference.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; data stream inputs below the first threshold and above the third threshold are a “0” if both the second and third bits are “1” values, and as a “1” if either of the second and third values is a “1”; data stream inputs above the second threshold and below the third threshold are a “1” if both the second and third bits are a “0” value, and as a “0” if either of the second and third values is a “0”.

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: In a digital broadcast receiver, when a bit error rate (BER) is larger than a threshold in a BER determining part, power is supplied to a first tuner and a second tuner for diversity reception. When the BER is smaller than the threshold, power supply to one of the first tuner and the second tuner is stopped for single reception. This structure allows power supply to one of the tuners to be stopped in excellent reception environments, thus reducing power consumption.

Abstract: A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

Abstract: A circuit for generating tracking error signal using differential phase detection, comprising a quadrant photodetector for receiving optical signal and inducting splitting signal A, splitting signal B, splitting signal C and splitting signal D, two adders for generating group signal (A+C) and group signal (B+D). A plurality of equalizers for receiving, equalizing and amplifying splitting signal A, splitting signal B, splitting signal C, splitting signal D, group signal (A+C) and group signal (B+D). A plurality of phase detectors for receiving the output of equalizers and comparing phase difference of splitting signal A and group signal (A+C), group signal (A+C) and splitting signal B, splitting signal C and group signal (B+D), and group signal (B+D) and splitting signal D, and outputting a plurality of adjustment signals respectively. A circuit for eliminating the phase difference by adding and subtracting some adjustment signals with same phase difference.