Abstract: A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for filtering the signal and generating a first filtered signal, a second band-pass filter with center frequency around a second frequency value for filtering the signal and generating a second filtered signal, a first comparator for comparing the first filtered signal with a reference level and generating a first compared signal, a second comparator for comparing the second filtered signal with the reference level and generating a second compared signal, a clock generator for generating a reference clock having a frequency close to the first frequency value according to the second compared signal, and a detection module for generating a bit signal representing the information according to the first compared signal and the reference clock.

Abstract: A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a plurality of LBIST channels do not contribute to a particular test and excluding from that particular test each LBIST channel that does not contribute to that particular test.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.

Abstract: An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine responsive to said sequence of logic values to switch the electronic system between different modes of operation.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; data stream inputs below the first threshold and above the third threshold are a “0” if both the second and third bits are “1” values, and as a “1” if either of the second and third values is a “1”; data stream inputs above the second threshold and below the third threshold are a “1” if both the second and third bits are a “0” value, and as a “0” if either of the second and third values is a “0”.

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract: A boundary scan technique to generate toggling waveform such as a square wave signal to perform structural testing is disclosed. An instr_extesttoggle command is provided that enables IEEE 1149.1 boundary scan cell to selectively generate the toggling signal on the pre-specified output pads of the integrated circuit. The frequency of the toggling signal may be controlled by the JTAG clock signal and the frequency of the toggling signal may be independent of the length of the boundary scan chain. Such an approach circumvents provisioning test points on the interconnects of a printed circuit board.

Abstract: Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages.

Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: A detection apparatus detecting an error component contained in two signals (A, B) approximated by a cosine and sine functions representing an object position, the detection apparatus including an arithmetic portion (3, 4) which reduces an error contained in the signals (A, B) based on an error prediction value to output two error correction signals (A*, B*), a phase arithmetic portion (5) which calculates a phase (?) based on the error correction signals (A*, B*), an arithmetic storage unit (9, 10) which stores the error correction signals (A*, B*) and a plurality of sampling values of the phase (?), and a Fourier transform portion (11, 12) which obtains coefficients ?k, ?k, ?k, and ?k in the following two expressions: A*=?0+?1 cos ?+?1 sin ?+ . . . +?k cos k?+?k sin k? B*=?0+?1 cos ?+?1 sin ?+ . . . +?k cos k?+?k sin k? (k?2) wherein the arithmetic portion (3, 4) updates the error prediction value using the coefficients.

Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

Abstract: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing compara

Abstract: A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data “eye” samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data “eye” samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.

Abstract: A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator; and determining parametric information pertaining to the I/O circuit of the device under test from the phase signal.

Abstract: A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.

Abstract: An eye violation and excess jitter trigger for a digital signal uses a mask within a unit interval of the digital signal, such as a rectangular mask having corners defined by a high threshold, a low threshold, an early clock and a late clock, the early and late clocks being derived from a reference clock. The reference clock may be a recovered clock derived from the digital signal or from high and low threshold comparator outputs, or may be an external clock. For the excess jitter trigger, which is a special case of the eye violation trigger, the high and low thresholds are essentially equal. A status of the digital signal with respect to the mask is determined using the high and low thresholds and the early and late clocks, and a violation signal is output when the status indicates that a portion of the digital signal crossed into the mask. The violation signal may then be used to trigger data acquisition or for other purposes.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.

Abstract: An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared integrated circuit pin 14. The functional signal and the diagnostic signal have relative forms such that they can be simultaneously communicated and respective independent physical communication channels provided therefore. Examples are the diagnostic signal being used to frequency, phase, amplitude or otherwise modulate a functional signal being passed. A diagnostic interface circuit 18 is provided to recover the diagnostic signal from the combined functional and diagnostic signal or to combine the functional and diagnostic signals.

Abstract: This invention discloses a method of accurately detecting the current bit in a SDPSK modulated signal at the receiver. The proposed method calculates the current bit from the past-detected bits and the past symbols. Each past symbol estimates the current bit. Each of these estimates is summed up to provide the final estimate of the bit. The proposed method for the reception of SDPSK modulated data improves the bit error rate performance. The proposed method can be applied in any communication system that uses SDPSK modulation.

Abstract: A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detected to generate an enable signal. A stop event, such as a packet trailer, a specified digital event, a time interval or the like, is identified to generate a disable signal. The enable and disable signals are combined to produce a qualification signal that allows a trigger circuit to trigger on a specified anomaly within the portion of the serial data stream defined by the qualification signal.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extract data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: A system and method are provided for five-level non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing a five-level threshold; comparing the first bit estimate to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; and, in response to the comparisons, determining the value of the first bit. Establishing a five-level threshold includes: establishing thresholds to distinguish a first bit value when the second and third bit values are a “1” value, when the second bit value is a “1” and the third bit value is a “0”, when the second bit value is a “0” and the third bit value is a “1”, when the second and third bit values are a “0” value, and an approximate midway threshold.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

Abstract: A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively aligning either a capture edge or a launch edge of the clock of each domain with a corresponding edge of at least one other domain of the interacting synchronous clock domains to determine the cross-domain paths to be tested between a source domain and a destination domain; clocking memory elements in each domain at respective domain clock rates to launch signal transitions from source memory elements in source domains; and for each pair of interacting clock domains under test, capturing, in the destination domain, circuit responses to signal transitions launched along paths originating from the source domain and selectively disabling capturing, in the source domain, of circuit responses to signal

Abstract: An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and zeros.

Abstract: This digital transmission system is provided with a transmitting apparatus that transmits digital data signals and a receiving apparatus that receives the digital data signals transmitted over a transmission path, compares the signals with a predetermined threshold value, and performs decision reproduction. The receiving apparatus is formed by: decision circuits that receive the input of reception signals, discriminate between the respective reception signals using a plurality of threshold values, and output decision results; and a selection circuit that, based on the decision results output from the decision circuit, selects one decision result from one threshold value from among the decision results from each of the plurality of threshold values, and outputs the selected decision result. As a result, the receiving apparatus is able to individually select which decision result to use from which threshold value.

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Abstract: A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a fuse set for providing a constant signal by using the output from the test mode enable confirmation section in case of the test mode, regardless of elimination or non-elimination of a fuse.

Abstract: An optical signal receiving equipment including an optical-electrical converter configured to convert optical signals into electronic signals; first deciders configured to transform the electronic signals into first binary signals; a second decider configured to transform the electronic signals into a second binary signal; a decision encoder configured to compute identification signals based on the plurality of first binary signals, and to compute reliability information of the computed identification signals; a converter configured to combine the identification signals and the second binary signal to combined identification signals; and a controller configured to execute an initial identification of the electronic signals in any one of the plurality of first deciders by using an initial threshold level in the plurality of first deciders, to measure an average amplitude of the electronic signals, and to correct the threshold level of the plurality of first deciders based on a variation of the average amplitud

Abstract: A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

Abstract: A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.

Abstract: A data decoding method judges a signal state where there is a transition from a low level to a high level or from a high level to a low level at the center portion of a bit interval as logical “1” or “0”, and a signal state where a low level continues or a high level continues over the entire bit interval as logical “0” or “1”. The method has the steps of: measuring a first time duration in which the bit series signal transitions from a low level to the next low level, measuring a second time duration in which the bit series signal transitions from a high level to the next high level, and deciding a logical “0” or “1” value for the target bit to be decided based on the combination of the first time duration and the second time duration measured for the target bit.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

Abstract: The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may be used to optimize threshold values by maximizing the mutual information. In another embodiment, an adaptive scheme may be used to optimize threshold values based on a pre-knowledge of the noise in the channel. In a further embodiment, an adaptive scheme may be used to optimize threshold values by without pre-knowledge of the noise in the channel.

Abstract: A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”) and logic for activating a match_OR signal when at least one of one or more designated bits of the selected N-bit portion of the data is a logic 1 or if there are no designated bits.

Abstract: Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding to the first set of signals. When the first control signal and a first function signal are asserted, the corresponding second signals of are asserted in response and a function is performed on the boards. But, if any of the second signals are asserted, none of the first signals is asserted in response. Test signals on boards are thereby isolated from test signals coupled to all the boards on the system, so a fault on any signal in any second set of signals will not propagate to the first set of signals.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.