Spare Row Or Column Patents (Class 714/711)
  • Patent number: 10636509
    Abstract: A memory test apparatus according to the present embodiment comprises a first storage medium temporarily retaining a test result of memory cells of a device under test in a plurality of divided portions based on data output from the device under test. A first processor reads the divided test result from the first storage medium to compress the test result. A second storage medium is provided to respectively correspond to a plurality of the devices under test and receives the compressed test result from the first processor and saves the compressed test result.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tetsuharu Kojima
  • Patent number: 10481796
    Abstract: A method for screening bad data columns in a data storage medium comprising a plurality of data columns includes: labeling or recording a plurality of bad data columns as a bad data column group, wherein the bad data columns are selected from the data columns in the data storage medium, each of the bad data column groups labels or records a position and a number of the bad data columns; determining whether the total number of the bad data columns is greater than a total number of the bad data column groups; and if yes, labeling or recording any two bad data columns of the bad data columns spaced apart by P data columns as one of the bad data column groups, wherein P is a positive integer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 19, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Sheng-Yuan Huang, Yu-Ping Chang
  • Patent number: 10475524
    Abstract: A memory controller includes an interface and circuitry. The interface is configured to communicate with a memory device, which includes multiple memory cells, and which applies refreshing to the memory cells by repeatedly inverting data stored in the memory cells. The circuitry is configured to store input data in a group of the memory cells, to read the stored input data from the group of the memory cells to produce read data, the read data has an actual polarity that is either un-inverted or inverted due to the refreshing of the memory cells in the group, to analyze the read data for identifying the actual polarity of the read data, and to recover the input data from the read data based on the identified actual polarity.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 12, 2019
    Assignee: Apple Inc.
    Inventors: Assaf Shappir, Eyal Gurgi
  • Patent number: 10346301
    Abstract: A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Gu Jo, Yong-Ju Kim
  • Patent number: 10261689
    Abstract: A method for screening bad data columns in a data storage medium comprising a plurality of data columns includes: a) labeling or recording a plurality of bad data columns as bad data column group, wherein the bad data columns are selected from the data columns, and each bad data column group labels or records a position and a number of the bad data columns; b) determining whether at least one bad data column is not labeled or recorded; and c) if yes, labeling or recording any two bad data columns spaced apart by P data columns and the P data columns as one of the bad data column groups, wherein P is a positive integer.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 16, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Sheng-Yuan Huang, Yu-Ping Chang
  • Patent number: 9953725
    Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ye-Sin Ryu, Sang-Uhn Cha, Hoi-Ju Chung, Seong-Jin Cho
  • Patent number: 9812180
    Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: November 7, 2017
    Inventor: Hare Krishna Verma
  • Patent number: 9715944
    Abstract: A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0?i?n?1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lior Binyamini, Stefan Payer, Wolfgang Penth, Ido Rozenberg
  • Patent number: 9666309
    Abstract: Provided are a method and device for repairing memory. The method includes: determining spare lines with priority to be used for repair, and searching for a repair solution by using the spare line with priority and failure counters for lines without priority.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: May 30, 2017
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Sungho Kang, Keewon Cho
  • Patent number: 9646125
    Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: May 9, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Mark C. Hakey, Jason D. Hibbeler, James S. Nakos, Tak H. Ning, Kenneth P. Rodbell, Ronald D. Rose, Henry H. K. Tang, Larry Wissel
  • Patent number: 9632884
    Abstract: Maintaining operability of a network-connected data processing apparatus is provided. In response to a requirement for failover from a first resource to a second resource, one or more processors tests an availability of the second resource, wherein the first and second resources are redundant resources of a network-connected data processing apparatus that is communicatively coupled to at least one host computer. In response to a positive determination of the availability of the second resource, one or more processors initiates the failover; and in response to a negative determination of the availability of the second resource, one or more processors provides an indication of unavailability.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: William Bittles, Andrew D. Martin, Timothy F. McCarthy
  • Patent number: 9626244
    Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-soo Sohn, Kwang-il Park, Chul-woo Park, Jong-pil Son, Jae-youn Youn, Hoi-ju Chung
  • Patent number: 9525422
    Abstract: According to an embodiment, a reconfigurable semiconductor integrated circuit includes memories connected in parallel, a logic circuit whose logic is defined according to data output of one of the memories, a signal output unit, and a switching unit. The signal output unit includes output terminals corresponding to the respective memories. Each terminal outputs a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit. The signal output unit is configured to output the selection signal in a cyclic manner over the terminals so that one terminal outputs the selection signal and the others output the non-selection signal. The switching unit is configured to set a route between a first output terminal and a second output terminal of the terminals to an open state or a closed state. The route bypasses at least a single output terminal.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masato Oda
  • Patent number: 9490033
    Abstract: In an example embodiment, a method may include collecting, at a controller within an integrated circuit, defect information indicative of defects identified during a built-in self-test (BIST) operation performed on plural memories embedded within the integrated circuit. Fuses within the integrated circuit may be blown based on the defect information collected automatically and without software intervention. The fuses blown may be used to inform a built-in self-repair (BISR) operation performed on the plural memories.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Cavium, Inc.
    Inventors: Steven W. Aiken, David A. Carlson
  • Patent number: 9471418
    Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Jin Ahn, Yong-Hyeon Kim, Sung-Up Choi, Yong-Kyeong Kim
  • Patent number: 9268879
    Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes receiving, at a hardware accelerator, a first instruction to project a first plurality of database rows, where each of the first plurality of database rows has one or more variable-length columns. The first plurality of database rows are projected, by a computer processor, to produce a first plurality of projected rows. This projection is performed at streaming rate.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 9224504
    Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Siamack Nemazie, Ebrahim Abedifard
  • Patent number: 9123395
    Abstract: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: September 1, 2015
    Assignee: SK hynix Inc.
    Inventors: Seung-Wook Kwak, Sang-Hoon Shin, Keun-Soo Song
  • Patent number: 9087611
    Abstract: Memory blocks in an integrated circuit (IC) chip can be repaired by employing automated test equipment external to the IC chip to aid in burning fuses on the IC chip by encoding the fuses with binary-encoded numbers. Each binary-encoded number represents a bit position of each “1” bit of a repair control word corresponding to a defective memory location. During a repair sequence preceding operation of the IC chip, the binary-encoded numbers are read out of the fuses and used to form a serial stream of repair chain information.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 21, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Donald F. McCarthy
  • Patent number: 9043661
    Abstract: Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Nicholas Hendrickson
  • Patent number: 8982596
    Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 17, 2015
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Patent number: 8937845
    Abstract: A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: January 20, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Piyush Kumar Mishra, Ashish Sharma
  • Publication number: 20150012784
    Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Siamack Nemazie, Ebrahim Abedifard
  • Patent number: 8918684
    Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: December 23, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hiroto Kinoshita
  • Patent number: 8887013
    Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: November 11, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Ebrahim Abedifard
  • Patent number: 8874832
    Abstract: A method for managing a flash memory that includes a plurality of primary cells and a plurality of spare cells includes interrogating the flash memory to determine which spare cells have been used to replace respective primary cells and using at least a portion of a remainder of the spare cells as reference cells.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 28, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Mark Murin, Eran Sharon
  • Patent number: 8874979
    Abstract: According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Anil B. Lingambudi, Saravanan Sethuraman, Kenneth L. Wright
  • Patent number: 8869007
    Abstract: According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Anil B. Lingambudi, Saravanan Sethuraman, Kenneth L. Wright
  • Patent number: 8799717
    Abstract: Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Stephen Bowers, Gurkirat Billing, Samuel David Post
  • Patent number: 8775881
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8767488
    Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: July 1, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Patent number: 8769356
    Abstract: A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-Soo Yu, Chul-Woo Park, Uk-Song Kang, Joo-Sun Choi, Hong-Sun Hwang, Jong-Pil Son
  • Patent number: 8762801
    Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: June 24, 2014
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou
  • Patent number: 8726106
    Abstract: Disclosed herein is a semiconductor device that includes selection lines selected based on an access address, a first hit signal generation circuit activating a first hit signal when the access address is coincident with a programmed address that designates a defective selection line included in the selection lines, and a first redundant selection line selected when the first hit signal is activated. The first hit signal generation circuit deactivates the first hit signal when a value of the access address is in a first address range even if the access address is coincident with the programmed address.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 13, 2014
    Inventor: Hidekazu Noguchi
  • Patent number: 8713382
    Abstract: A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 29, 2014
    Assignee: Advantest Corporation
    Inventor: Makoto Tabata
  • Patent number: 8667324
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 8619481
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • Patent number: 8621291
    Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: December 31, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroto Kinoshita
  • Patent number: 8615689
    Abstract: A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: William J. Kabelac, Barry M. Trager, Shmuel Winograd
  • Patent number: 8601329
    Abstract: A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: December 3, 2013
    Assignee: Advantest Corporation
    Inventors: Masaru Doi, Kazuhiro Shibano
  • Patent number: 8601327
    Abstract: A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: December 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mun-Phil Park
  • Patent number: 8527819
    Abstract: A method for data storage includes performing an erasure operation on a group of analog memory cells (32). One or more of the memory cells in the group, which failed the erasure operation, are identified as erase-failed cells. A storage configuration that is used for programming the analog memory cells in the group is modified responsively to the identified erase-failed cells. Data is stored in the group of the analog memory cells using the modified storage configuration.
    Type: Grant
    Filed: October 12, 2008
    Date of Patent: September 3, 2013
    Assignee: Apple Inc.
    Inventors: Ofir Shalvi, Shai Winter, Naftali Sommer, Dotan Sokolov
  • Patent number: 8522099
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8495435
    Abstract: An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus includes an address swap cache. The apparatus also includes memory segment swap logic that is capable of detecting a reproducible fault at a first address targeting a memory segment. Once detected, the logic remaps the first address targeting the faulty memory segment with a second address targeting another memory segment. The logic stores the two addresses in an entry in the address swap cache. Then the memory segment swap logic receives a memory transaction that is targeting the first physical address and use the address to perform a lookup process in the address swap cache to determine if an entry exists that has the faulty address. If an entry does exist for that address, the logic then swaps the second address into the memory transaction for the first address.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: July 23, 2013
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, Lawrence D. Blankenbeckler
  • Patent number: 8495436
    Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.
    Type: Grant
    Filed: June 17, 2012
    Date of Patent: July 23, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Deepak Agrawal, Rachna Lalwani
  • Publication number: 20130139010
    Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
    Type: Application
    Filed: January 25, 2013
    Publication date: May 30, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Patent number: 8438431
    Abstract: A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Edward C. McCain, Lisa Nayak, Gerard M. Salem
  • Patent number: 8427893
    Abstract: A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy memory cell corresponding to the unprogrammed signal when the first redundancy enable signal from the first control unit or a second redundancy enable signal from the second control unit is activated. Thus, the redundancy memory cell access circuit is tested simultaneously with testing of the redundancy memory cell for minimized testing and programming times.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eunsung Seo
  • Patent number: 8423837
    Abstract: An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.
    Type: Grant
    Filed: February 13, 2010
    Date of Patent: April 16, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhir K. Madan, David J. Toops, Robert J. Landers
  • Patent number: 8423841
    Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 16, 2013
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou