Abstract: A side-channel attack countermeasure that leverages implementation diversity and dynamic partial reconfiguration as mechanisms to reduce correlation in the power traces measured during a differential power analysis (DPA) attack. The technique changes the underlying hardware implementation of any encryption algorithm using dynamic partial reconfiguration (DPR) to resist side-channel-based attacks.

Abstract: An apparatus, computer-readable medium, and computer-implemented method for parallelization of a computer program on a plurality of computing cores includes receiving a computer program comprising a plurality of commands, decomposing the plurality of commands into a plurality of node networks, each node network corresponding to a command in the plurality of commands and including one or more nodes corresponding to execution dependencies of the command, mapping the plurality of node networks to a plurality of systolic arrays, each systolic array comprising a plurality of cells and each non-data node in each node network being mapped to a cell in the plurality of cells, and mapping each cell in each systolic array to a computing core in the plurality of computing cores.

Abstract: A memory includes: a memory array; a nonvolatile memory circuit suitable for storing a plurality of data sets each including flag information and multi-bit data; a plurality of repair register sets suitable for receiving and storing the multi-bit data included in the data sets whose flag information is marked for repair among the data sets during a boot-up operation; a plurality of setting register sets suitable for storing setting information included in the data sets whose flag information is marked for setting among the data sets during the boot-up operation; and a repair circuit suitable for repairing a defect in the memory array based on the multi-bit data stored in the repair register sets.

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract: A system includes a multidimensional array of homogenous Functional Configurable Units (FCUs), coupled using a multidimensional array of switches, and a parameter store on the device which stores parameters that tag a subarray of FCUs as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged subarray, by changing the routing through the array of switches. As a result, a multidimensional array of FCUs having unusable elements can still be used.

Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.

Abstract: Memories, and their operation, might include a plurality of content addressable memory (CAM) cells each for storing a respective data value, a match signal generator configured to generate an indication whether each CAM cell of the plurality of CAM cells indicates a match between its respective data value and a respective received signal value, and a plurality of storage elements each for storing a respective data value, wherein each storage element of the plurality of storage elements corresponds to a respective CAM cell of the plurality of CAM cells in a one-to-one relationship, and wherein each storage element of the plurality of storage elements is responsive to the indication of the match signal generator to generate a data signal indicative of the respective data value of that storage element if a match of their corresponding CAM cells is indicated.

Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.

Abstract: A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.

Abstract: A computing system includes: a memory device including a memory cells; a memory controller configured to control the memory device; and a host configured to detect an occurrence of an error in a first memory cell of the memory device while performing an operation corresponding to a workload and transmit, to the memory controller, a target address corresponding to the first memory cell and a request for a test operation on adjacent memory cells that are adjacent to the first memory cell. The memory controller controls the memory device to perform the test operation on the adjacent memory cells by using at least one of a Built-In Self-Test (BIST) engine or a scrub engine based on the target address and generate memory error information including information associated with a second memory cell in which the error occurs, the second memory cell being one of the adjacent memory cells. The host controls an access to the second memory cell based on the memory error information.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

Abstract: Methods, apparatus, and processor-readable storage media for learning machine behavior related to install base information and determining event sequences based thereon are provided herein. An example computer-implemented method includes parsing data storage information based at least in part on parameters related to install base information comprising temporal parameters and event-related parameters; formatting the parsed set of data storage information into a parsed set of sequential data storage information compatible with a neural network model; training the neural network model using the parsed set of sequential data storage information and additional training parameters; predicting, by applying the trained neural network model to the parsed set of sequential data storage information, a future data unavailability event and/or a future data loss event; and outputting an alert based at least in part on the predicted future data unavailability event and/or predicted future data loss event.

Abstract: An indirection mapping data structure can maintain a mapping between logical block addresses used by a host computer and physical data storage locations on a solid state drive. Changes to the indirection mapping data structure can be stored in journals. When a journal is full, the journal can be stored to a predetermined location on the cluster block determined based on the number of entries stored by the journal, leading to a number of journals scattered throughout the cluster block at predetermined locations. Each physical chunk of media, whether written with data or marked as defective is journaled. Such a journaling scheme, where the journal locations are predetermined and each physical chunk of media is journaled is referred to as physical media-aware spatially coupled journaling. During replay the spatially coupled journals can be retrieved from the predefined locations within cluster blocks and used to rebuild the indirection mapping data structure.

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, tire package test, tire module test or the mounting test is failed.

Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape. The head is used to write contiguously to the magnetic tape a first preamble, followed by a first sync mark, followed by symbols of a first data sector, followed by a second sync mark, followed by a second preamble, followed by a third sync mark, followed by symbols of a second data sector.

Abstract: Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

Abstract: An electronic device (201) of a transportation means comprises a power bus input interface (202), a power bus output interface (203), and a data bus interface (204). The device comprises voltage reducing means (205) for selectively performing a controlled voltage reduction between the power bus input interface (202) and the power bus output interface (203). The reduced operating voltage is lower than the operating voltage received via the power bus input interface (202) but higher than zero. The device is arranged to use (1201, 1202) said voltage reducing means depending in a predetermined manner on whether or not the device has performed addressing operations to carry out addressed data communication by means of said data bus.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.

Abstract: Systems, apparatuses and methods provide technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion are substituted for the one or more failed memory cells.

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Abstract: A computing problem management method, system, and non-transitory computer readable medium, include detecting an impending problem of the computing system, spawning a plurality of replicas when detecting the impending problem, introducing a plurality of new impending problems on the plurality of replicas for the launching to launch versions of an action to resolve, and learning a version that resolves each of the plurality of new impending problems.

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair address and a plane locator. A match circuit generates a repair enable flag based on the plane locator, wherein the repair status represents enable, disable, and/or unused setting for the repair address with respect to implementing a global replace for the repair address with redundant cells on a repair plane.

Abstract: Provided is a method for sending digital data over a number of channels wherein a sender performs the following steps: encoding source data having a first number of source symbols, the encoding being such that an error correction code is generated from the source data, the error correction code comprising a second number of repair symbols higher than the first number as well as identifiers where each identifier is assigned to a corresponding repair symbol, the error correction code adding redundancy to the source data; encrypting each repair symbol by an encryption process which is based on a shared secret between the sender and a receiver, where the encryption process for a respective repair symbol depends on the identifier assigned to the respective repair symbol; feeding pairs of the encrypted repair symbols and the assigned identifiers to the number of channels which are connected to the receiver.

Abstract: A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

Abstract: Memory devices are disclosed. A memory device may include a memory array including a number of memory cells partitioned into a number of memory segments. Each of the number of memory segments may include a redundant memory-cell group configurable to be accessed instead of a defective memory-cell group of the memory segment. The memory device may also include a set of latches configurable to indicate that a redundant memory-cell group of a memory segment of the number of memory segments is to be accessed instead of a defective memory-cell group of the memory segment. The set of latches may include segment latches configurable to indicate the memory segment or a status of the set of latches. The set of latches may also include address latches configurable to indicate the defective memory-cell group within the memory segment. Related systems and methods are also disclosed.

Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. Wherein, the storage circuit stores the fuse data and outputs it as a storage signal and the parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal, the fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal, the error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.

Abstract: A method begins or continues by a computing device of a dispersed storage network (DSN) determining an error with a first write request in a first zone of a plurality of zones of a memory device of a storage unit of DSN, where the first zone includes a first set of sequential blocks that are in a first logical and physical location of the memory device. The method continues with the computing device abandoning pending write requests to the first zone. The method continues with reassigning the first write request to a second zone of the memory device, where the second zone includes a second set of sequential blocks that are in a second logical and physical location of the memory device.

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

Abstract: Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells.

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks.

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

Abstract: A determination can be made that an error control operation associated with user data has failed. An initial operating characteristic associated with the error control operation that failed can be identified. A complementary operating characteristic to replace the operating characteristic associated with the error control operation that failed can be determined. The error control operation for the user data can be performed based on the complementary operating characteristic.

Abstract: According to an embodiment, a management device includes: a setting memory configured to store an access method indicating which of a first access process of performing writing or reading with respect to data transferred from a non-volatile memory to a first memory, or a second access process of directly performing writing or reading with respect to data stored in the non-volatile memory, is to be executed for each of the plurality of pages; and circuitry configured to select any page set to the second access process among the plurality of pages, as an exchange target page, when a write amount with respect to the non-volatile memory is larger than a set value, and change an access method of the exchange target page from the second access process to the first access process.

Abstract: Systems and methods for automatic repair, replacement, and/or configuration of various network devices within a communications network are disclosed. The system may receive indication of a failed network device and automatically perform diagnostic on the network device to determine any problems associated with the hardware and/or software components within the network device. Subsequently one or more repair, replacement, and/or configuration procedures may be automatically initiated in an attempt to resolve the problems and restore the failed network device.

Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.

Abstract: An indirection mapping data structure can maintain a mapping between logical block addresses used by a host computer and physical data storage locations on a solid state drive. Changes to the indirection mapping data structure can be stored in journals. When a journal is full, the journal can be stored to a predetermined location on the cluster block determined based on the number of entries stored by the journal, leading to a number of journals scattered throughout the cluster block at predetermined locations. Each physical chunk of media, whether written with data or marked as defective is journaled. Such a journaling scheme, where the journal locations are predetermined and each physical chunk of media is journaled is referred to as physical media-aware spatially coupled journaling. During replay the spatially coupled journals can be retrieved from the predefined locations within cluster blocks and used to rebuild the indirection mapping data structure.

Abstract: A data storage device includes a memory device and a controller. The memory device includes at least an MLC block. The MLC block includes a plurality of physical pages. The controller is coupled to the memory device. When the controller determines that a sudden power-off has occurred during a previous write operation for writing data onto the MLC block, the controller finds a predetermined page that has been attacked by the sudden power-off, double programs the predetermined page and a first page that is directly related to the predetermined page and dummy programs a plurality of second pages that are indirectly related to the predetermined page.

Abstract: Systems and methods for virtualization technology that enhances memory page hinting to better support data integrity verification. An example method may comprise: determining, by a processing device executing a hypervisor, an integrity mark of a guest operating system, the integrity mark being associated with content of one or more memory pages; detecting, by the hypervisor, that a memory page is released by the guest operating system; verifying, by the hypervisor, content of the memory page in view of the integrity mark of the guest operating system; and evicting, by the hypervisor, the content of the memory page in response to the verifying.

Abstract: Virtual field programmable gate array (VFPGA) duplicates and/or emulates a field programmable gate array through the use of base hardware and firmware that uses RAM as ROM or EPROM and provides control and monitoring and manipulation through the use of elementary and basic device functionality commands (machine code primitives) to accommodate the needs of polymorphic cipher engine software so that the software achieves the same results as thou it had access to programmable logic arrays, gate and logic blocks found in field programmable gate array chips.

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.