Abstract: The processing for deciding the remedy as being possible or impossible and the processing for remedying bit fails can be both executed in a short time on the basis of bit mask processing. Fail data are transferred from the tester to the redundancy processor (in Step S101), and the number of the fail addresses stored in the buffer memory is compared with the maximum number of fail bits (in Step S103). Further, the line fail detection and the remedy processing are both executed (in Step S105), and the redundancy processor decides whether the number of the line fails exceeds the number of the spare rows and the number of the spare columns or not (in Step S107). Further, the bit mask processing is executed for the fail addresses (in Step S109) to decide the remedy possibility (in Step S111). Here, the maximum remediable number of the bit mask processings can be calculated on the basis of "the number of row spares R+the number of the column spares".

Abstract: A method is disclosed for providing error correction for an array of disks using non-volatile random access memory (NV-RAM). Non-volatile RAM is used to increase the speed of RAID recovery from a disk error(s). This is accomplished by keeping a list of all disk blocks for which the parity is possibly inconsistent. Such a list of disk blocks is much smaller than the total number of parity blocks in the RAID subsystem. The total number of parity blocks in the RAID subsystem is typically in the range of hundreds of thousands of parity blocks. Knowledge of the number of parity blocks that are possibly inconsistent makes it possible to fix only those few blocks, identified in the list, in a significantly smaller amount of time than is possible in the prior art. The technique for safely writing to a RAID array with a broken disk is complicated. In this technique, data that can become corrupted is copied into NV-RAM before the potentially corrupting operation is performed.

Abstract: A storage data reconstruction system including: a plurality of storage units for storing therein divided data, the plural independent storage units forming a set; units for storing therein ECC data corresponding to the divided data; a spare storage unit for storing therein a reconstructed data; an I/O-reconstruction control circuit; a timer; a data reconstructing table for storage unit which has failed; and a circuit for reconstructing faulty data. When a failure occurs in any of the storage units, the failure is detected by an error check, a state of the failure is discriminated, a preferred processing suitable for the state of the failure is selected from a processing of a normal access or read/write and a data reconstruction processing, and the selected processing is carried out, or the frequency of the processing of the normal access or read/write and the data reconstruction processing, or the ratio of the amount of the data reconstruction processing within a unit time, is set.

Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

Abstract: A method and circuit for testing cells in a memory device is disclosed. Data is written to the cells and then the cells are read in groups. For example, groups of four cells are read together. Output bits of the four cells are compressed in a compression circuit to generate compressed data, and the compressed data is checked to determine if one or more of the four cells was defective and produced an incorrect output bit. If one of the cells was defective, each cell is read in a sequence and its output bit is tested to determine which of the four cells is defective. The defective cell is replaced with a redundant cell.