Abstract: A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.

Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.

Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.

Abstract: A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel.

Abstract: A reconfigurable device test scheme is provided for making a test of a reconfigurable device with configuration data which is loaded a smaller number of times. A reconfigurable device used herein holds a plurality of configuration data and is capable of instantaneously switching which configuration is implemented thereby. Specifically, one transfer configuration data and one or more test configuration data are previously loaded in a configuration memory of the reconfigurable device, and a test is made while sequentially switching the transfer configuration data and the test configuration data. In this way, the same configuration data need not be reloaded over and over, so that the test can be made with a smaller number of times of loading as compared with before.

Abstract: Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device, assigning each of the plurality of the scanning elements to one of the plurality of the scan chains based on the first preference information and the second preference information.

Abstract: A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.

Abstract: A method for evaluation of a field programmable gate array (FPGA), the method includes: configuring the FPGA to execute, in parallel, an evaluation program and an additional program; wherein an execution of the additional program is being evaluated by the evaluation program; and executing, by the FPGA the evaluation program and the additional program; wherein the executing includes receiving, by a memory controller of the FPGA, captured signals from multiple points of interest of the FPGA; and transferring, by the memory controller of the FPGA, at least a portion of the captured signals to at least one memory space of a memory block via memory channels of the FPGA.

Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

Abstract: A semiconductor device comprises processing logic arranged to execute program instructions. The semiconductor device further comprises signature generation logic arranged to receive at least one value from at least one internal location of the semiconductor device, and to generate a current signature value, based on the at least one received value. Validation logic is arranged to validate the current signature value generated by the signature generation logic. The processing logic is further arranged, upon execution of a signature validation instruction, to enable the validation of the current signature value provided by the validation logic.

Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.

Abstract: A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels.

Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.

Abstract: In one embodiment, a method of detecting corruption of configuration memory is provided. A bitstream of a circuit design that includes at least a first module and a second module is generated. Configuration memory cells used to implement each of the first and second modules are determined. The configuration memory cells are programmed with the bitstream. After programming, configuration memory cells used to implement the first module are checked for corruption at a first frequency, and configuration memory cells used to implement the second module are checked for corruption at a second frequency, with the first frequency being different from the second frequency.

Abstract: A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.

Abstract: Reconstruction methods and devices are disclosed for scan chains in physical design that is based on two-way priority selection. The structural reconstruction method in the scan chains, in the first place, establishes a first preference sequence for a certain number of scanning elements in each of these scan chains as well as a secondary preference sequence for these scan chains in each of these scanning elements respectively. Then, two-way selection is executed between the scan chains and scanning elements based on the corresponding first preference sequence and secondary preference sequence, so that these scanning elements can be redistributed to these scan chains. The structural reconstruction method and device in the invention conduct an integrated optimization for a global scan chain, where the global wiring length is shortened dramatically and the wiring efficiency is improved.

Abstract: Methods and circuits for zeroization verification of the memory in an integrated circuit (IC) are provided. One method includes sequentially reading frames from a block of the memory, and sequentially performing a logical operation between each of the frames and the content of a signature register. The result of the logical operation is stored back in the signature register. In another operation, a hardware logical comparison is made between a device hardwired signature block and the content of the signature register, after the logical operations for all the frames have been performed. The device hardwired signature block is a hardware implemented constant that is unavailable for loading in registers of the IC. The block of the memory is verified to hold a fixed value when the result of the hardware logical comparison indicates that the device hardwired signature block is equal to the content of the signature register.

Abstract: Methods and apparatus useful for improving the performance of testing and diagnostic operations on user circuit designs potentially across multiple phases of the development lifecycle and across multiple implementation technologies are described. As one example, a single testing and diagnostic stimulus source can variously provide test pattern data to different potential instantiations of the user circuit design by supporting and selectively utilizing a number of DUT-facing communication channels.

Abstract: An embodiment of the invention relates to an integrated circuit that includes an identifier reader which may be, e.g., a physically unclonable function reader that generates a unique and reproducible identifier for the integrated circuit, and a related method. An error correction code may be employed to correct an error in the value of the reproducible identifier. Values of signals in the integrated circuit are selectively inverted dependent on values of the reproducible identifier, and an error corrector uses the values of the reproducible identifier to restore the values of the signals. The signals may be produced as outputs of look-up tables that selectively invert the values of the signals dependent on the value of the reproducible identifier. The signals may be inputs to the integrated circuit, internal signals, outputs, or state data. A test may validate a state of the integrated circuit and disable operation if the test fails.

Abstract: Some embodiments provide a method of dynamically tracking data values in a configurable integrated circuit (IC). The method, during a run time of the configurable IC, receives a request for a data value and dynamically configures the configurable IC to monitor the data value. In some embodiments, the method, in dynamically configuring the configurable IC, dynamically configures a debug network of the configurable IC. In some such embodiments, the method, in dynamically configuring the configurable IC, further dynamically configures a set of configurable routing circuits of the configurable IC. In some embodiments the configuration is performed while the IC is implementing a user design circuit.

Abstract: Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

Abstract: In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.

Abstract: An integrated circuit (“IC”) in which a debug signal is fed back within a core block is disclosed. The core block generates the debug signal. The core block includes a hardened routing that routes the debug signal within the core block. The IC also includes a programmable routing, coupled to the core block, to route the debug signal external to the core block. The hardened routing transmits the debug signal at a faster rate than the programmable routing. Further, the IC includes a selection device, coupled to the hardened routing and the programmable routing, to select one of: the hardened routed signal or the externally routed signal. In addition, the IC includes an external debug circuit, coupled to the programmable routing, to condition the externally routed signal.

Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.

Abstract: Various techniques are provided for synchronizing serial data signals received by electronic systems or devices such as programmable logic devices (PLDs). In one example, a method of synchronizing data includes receiving a serial data signal at a device. The serial data signal operates independently of the device. The method also includes oversampling the serial data signal to provide a plurality of samples distributed over bit periods of the serial data signal. The method further includes filtering the samples to correct errors in the samples. In addition, the method includes extracting a plurality of data bit values from the samples under the control of a clock signal associated with the device without adjusting a frequency of the clock signal. Each data bit value is associated with one of the bit periods of the serial data signal.

Abstract: Fault tolerant programming of a programmable device advantageously occurs via a host controller that first queries the programmable device through a Boundary scan interface to identify the device. Thereafter, host controller selects a program file in accordance with the device identity for subsequent downloading via the Boundary scan interface to program the device. Thereafter, the host controller verifies that successful programming has occurred.

Abstract: A method of calculating total power usage of a field programmable gate array (FPGA) without external components generates at least one coefficient based on a power equation and a given FPGA logic design, wherein the power equation calculates FPGA power as a function of temperature and voltage. The at least one coefficient is applied to the power equation along with internally generated temperature and voltage measurement values. The temperature measurement and the voltage measurement values are applied to the power equation with the at least one coefficient applied to calculate a power measurement based on the temperature measurement value and the voltage measurement value. The at least one coefficient is generated by taking an FPGA design and iteratively simulating the design in a power estimation tool over a range of temperature and input voltage values. A characterization data set is generated and curve fitted to the power equation to produce the at least one coefficient.

Abstract: An integrated hardware and software debugging system debugs software running on a processor and debugs hardware blocks that perform operations separate from the processor. Cycle traces are recorded for hardware block operations and the data is presented to a user through the same interface used for software debugging. Where hardware blocks are implemented in configurable circuitry (such as an FPGA) from source code, hardware debugging is linked to the source code to simulate stepping through the source code.

Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.

Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.

Abstract: Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation, after which the integrated circuit includes a configuration controller coupled to a buffer, an internal configuration access port, and an error checker. A portion of a second bitstream is loaded into the buffer for a dynamic partial configuration mode of operation. The portion of the second bitstream loaded into the buffer is validated with the error checker as being acceptable, after which the portion of the second bitstream is instantiated in the programmable circuitry via the internal configuration access port.

Abstract: A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a judging unit that judges whether length of the candidate path is longer than a predetermined length; and a determining unit that determines whether to determine the candidate path as a target path to be subjected to a fault simulation based on a result of judgment.

Abstract: A system for testing a circuit. The system comprises a first circuit mounted on an embedded first circuit board and a test circuit mounted on the embedded first circuit board. The system further comprises a second circuit board on the first circuit board, the second circuit board including a second circuit and a test device external to the first and second circuit board. The test circuit is effective to send at least one first test signal from the test circuit to the first circuit, receive a first response of the at least one first test signal from the first circuit, and forward the first response to the test device.

Abstract: A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC.

Abstract: A program-controlled unit including a monitoring device, which compares a value, depending on the flow of the program executed by the program-controlled unit, with a preset value, in response to a particular event or in relation to a particular point in time. Errors occurring in a program-controlled unit can thus be detected in a reliable and economical manner under all circumstances.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package.

Abstract: In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.

Abstract: Method and apparatus for self-checking and self-correcting memory states of a programmable resource is described. Programmable resource of an integrated circuit has a first core and a second core instantiated therein. A first internal configuration port and a second internal configuration port of the integrated circuit are respectively connected to the first core and the second core. The second core is coupled to the first core for monitoring operation of the first core with the second core, and the second core is configured to obtain control responsive to a failure of the first core or the first internal configuration port for a self-correcting mode.

Abstract: A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal.

Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.

Abstract: Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a programmable logic device integrated circuit by receiving configuration data with the differential communications circuitry and storing the received configuration data in nonvolatile memory. The nonvolatile memory may be located in an external integrated circuit such as a configuration device or may be part of the programmable logic device integrated circuit. The stored configuration data may be loaded into configuration memory in the programmable logic device to program the device to perform a desired custom logic function. The differential communications circuitry may be used to handle boundary scan tests and programmable scan chain tests. During user mode operations the differential communications circuitry carries user data traffic.

Abstract: A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.

Abstract: Testing an integrated circuit (IC) having numerous terminals coupled to numerous digitally controlled impedance (DCI) modules, where the numerous DCI modules control configurable impedances of the numerous terminals. The IC further includes a control circuit having outputs coupled to enable inputs of the numerous DCI modules, where operating the IC in a test mode configures the control circuit to selectively couple a control signal to the enable terminals of the numerous DCI modules. One DCI module of the numerous DCI modules can be enabled at a time facilitating testing of the configurable impedances of the I/O terminals.

Abstract: Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design is identified. The chain of flip-flops includes first and second control signals. A shift register is instantiated in a logical description of the circuit design for the chain of flip-flops. A shift register is instantiated in the logical description for the chain of flip-flops. First and second control chains of flip-flops are instantiated in the logical description for the first and second control signals, respectively. A multiplexer is instantiated in the logical description and is configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains.